From patchwork Tue Jul 10 01:14:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 141499 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp3267310ljj; Mon, 9 Jul 2018 18:14:34 -0700 (PDT) X-Google-Smtp-Source: AAOMgpe72SrbKhyGbPFAQJ6lb/UOXTD6lIyC9IaCmHw51eIijhzSiz1eUMPpBGSHslF9BfLqScxo X-Received: by 2002:a63:d80f:: with SMTP id b15-v6mr7218527pgh.347.1531185274119; Mon, 09 Jul 2018 18:14:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531185274; cv=none; d=google.com; s=arc-20160816; b=kgl0c4voHwfsdzBKx7jKB33vUzuF0pS37jau1aJ5es+6HnSg9cwdG/xj6jtdRsf5em MnGwT7iKCHnyizE1moFVZQYP82Re5KmHOvhqiukwl/zAVdf3q3zFdXlTvuensvnENf8S susHeDwnYqlQnLvdoAyl/socXUbeUKSUkRCBnsxbpwzSDn9I7b/yNIjb5ZLLvEo/4NUn JrWJI4wfR6Gr/oaKnV5f6PIUXCmYES6rToRFyw4ITDEozSuL57NU6j+MIqjwzzxECGbw zWvBIeccZPr69ldaVwXcpGU7Peqgl4fjY8SHhY8/8lAhk2UXQVI14PsW20ZLydfLfbBu /U9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Q4ozquygVOi1wfiB+tdEG9CKf6KORn+86ximYKdAQ4Y=; b=ZRsxoKSKRT6T5L3jEc77DB5k735vwiIbHXl4yHUh8Iq0saD8VFf6wGDnlQTgFk7ue9 5hFQhS4RxubX+cnP7Ak38PI10p20cDZRl3Uyh7sQPl+qLbkowUWOY3q/Oej8zidAelBD JaZU9gAD0Np4wORfppuaT7I+q0yF7IC24Gn5ZyD/R5InmT7iu97MTHaSqM0h7UzkxZDS 0gkmkCYtUA8iD3w9VHLsB7VOxEg1ndfkDxrbZYXPjkeJU5ziTKD1Jh8KGyA3F0l2gtnq E69RNAgjfO6GFMyGW/OjdvfQQVYZcg7MQo7eQcmuABnWcCpDIN1H5Pz3UMIe12BJrBl/ EeqQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w185-v6si14490859pgb.599.2018.07.09.18.14.33; Mon, 09 Jul 2018 18:14:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754655AbeGJBO2 (ORCPT + 12 others); Mon, 9 Jul 2018 21:14:28 -0400 Received: from mx.socionext.com ([202.248.49.38]:55907 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754572AbeGJBOZ (ORCPT ); Mon, 9 Jul 2018 21:14:25 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 10 Jul 2018 10:14:24 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 1B94D60034; Tue, 10 Jul 2018 10:14:24 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Tue, 10 Jul 2018 10:14:24 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 4C85D1A11BB; Tue, 10 Jul 2018 10:14:23 +0900 (JST) From: Kunihiko Hayashi To: Philipp Zabel , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 1/2] dt-bindings: reset: uniphier: add USB3 core reset support Date: Tue, 10 Jul 2018 10:14:16 +0900 Message-Id: <1531185257-16444-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531185257-16444-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1531185257-16444-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings for reset control of USB3 core implemented in UniPhier SoCs. The reset control belongs to USB3 glue layer. Signed-off-by: Kunihiko Hayashi --- .../devicetree/bindings/reset/uniphier-reset.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt index 93efed6..101743d 100644 --- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt +++ b/Documentation/devicetree/bindings/reset/uniphier-reset.txt @@ -118,3 +118,59 @@ Example: other nodes ... }; + + +USB3 core reset +--------------- + +USB3 core reset belongs to USB3 glue layer. Before using the core reset, +it is necessary to control the clocks and resets to enable this layer. +These clocks and resets should be described in each property. + +Required properties: +- compatible: Should be + "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC + "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC + "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC + "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC +- #reset-cells: Should be 1. +- reg: Specifies offset and length of the register set for the device. +- clocks: A list of phandles to the clock gate for USB3 glue layer. + According to the clock-names, appropriate clocks are required. +- clock-names: Should contain + "gio", "link" - for Pro4 SoC + "link" - for others +- resets: A list of phandles to the reset control for USB3 glue layer. + According to the reset-names, appropriate resets are required. +- reset-names: Should contain + "gio", "link" - for Pro4 SoC + "link" - for others + +Example: + + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_rst: reset@0 { + compatible = "socionext,uniphier-ld20-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + regulator { + ... + }; + + phy { + ... + }; + ... + }; From patchwork Tue Jul 10 01:14:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 141500 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp3267472ljj; Mon, 9 Jul 2018 18:14:47 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcpqkeTIeyr1D2vJeDHoMM+CulHRphm5ywyw0ZRKykM/LoOtX5hXkjfMAEEbakcJQOYfjpX X-Received: by 2002:a63:1262:: with SMTP id 34-v6mr14953637pgs.154.1531185287534; Mon, 09 Jul 2018 18:14:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531185287; cv=none; d=google.com; s=arc-20160816; b=HEWdqaAYVD9trf/q3wU+4iZ87KSXmo8c1xUfoCWlwhKXczO4nXZ99FGpuj0dkzwfFm FIs5pf1dMbmfaAX5mT8ac/mr0vEp2VQGICpRfmUWbJENsOB9xh5LlqtIDJueoyZIPzkU tIxO2CHSl/arzt+P/fn6xtUb1UPKY0CjPwdy7cSF0pEthUp0A2FHWnxuaCF163QMaTGv fpzClViShSMeaR5KL3hjwLuflMTkLBpDGY/i0T+2UTw9H7atTtIj+2D47nE1SqVx7C0u TGdDyKLe20grxZ2WfxMV3cggEwL4rJX5EgSDmR+1pVkFp11eLhGQEMJpoiEjiLyYFK8W 6iVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=juqYeNQRjf03Ca5cJAjkuOzClsbhsFrXQTtCH7Lpejc=; b=igW2KeutFOvTF86xTxyAiKyvWjq6dZAl8lGegz8lsc0N2xDqCG+VyXWjHoC9OoKckc O7dTB3nHraNrVNGb+gfJJilQUIR9a4i1SvQoVa7zGXgevA6CcOmAZjWtMIRwjhNqBi+W dxz2ie5AFV6Ag7aEFY6Hxh5FxTzBITo/gxChTWiQ9XU63EknebV8V9v+VjLFZRTSWq5P F5HAepMwMC/J+23/rmz8upBgikyjxcSLS3S8OJZOgWHAprPuYHtxVoiXGSZCPjySKXGk 4Wq7WUvQ22KdHghnVcJPyUsAmJ26qGCeL/RqFZmPRCCH7iUd8yTM007bQT0VZzOmAAn0 1Keg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j30-v6si9223264pgm.26.2018.07.09.18.14.47; Mon, 09 Jul 2018 18:14:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754678AbeGJBOm (ORCPT + 12 others); Mon, 9 Jul 2018 21:14:42 -0400 Received: from mx.socionext.com ([202.248.49.38]:55914 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754596AbeGJBO0 (ORCPT ); Mon, 9 Jul 2018 21:14:26 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 10 Jul 2018 10:14:25 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 2898560034; Tue, 10 Jul 2018 10:14:25 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Tue, 10 Jul 2018 10:14:25 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 70FAC1A11BB; Tue, 10 Jul 2018 10:14:24 +0900 (JST) From: Kunihiko Hayashi To: Philipp Zabel , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 2/2] reset: uniphier: add USB3 core reset control Date: Tue, 10 Jul 2018 10:14:17 +0900 Message-Id: <1531185257-16444-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531185257-16444-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1531185257-16444-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a reset line to enable USB3 core implemented in UniPhier SoCs. This reuses only the reset operations in reset-simple, because the reset-simple doesn't handle any SoC-dependent clocks and resets. This reset line is included in the USB3 glue layer, and it's necessary to enable clocks and deassert resets of the layer before using this reset line. Signed-off-by: Kunihiko Hayashi --- drivers/reset/Kconfig | 10 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-uniphier-usb3.c | 171 ++++++++++++++++++++++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100644 drivers/reset/reset-uniphier-usb3.c -- 2.7.4 diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index c0b292b..6b45067 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -138,6 +138,16 @@ config RESET_UNIPHIER Say Y if you want to control reset signals provided by System Control block, Media I/O block, Peripheral Block. +config RESET_UNIPHIER_USB3 + tristate "USB3 reset driver for UniPhier SoCs" + depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF + default ARCH_UNIPHIER + select RESET_SIMPLE + help + Support for the USB3 core reset on UniPhier SoCs. + Say Y if you want to control reset signals provided by + USB3 glue layer. + config RESET_ZYNQ bool "ZYNQ Reset Driver" if COMPILE_TEST default ARCH_ZYNQ diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index c1261dc..2638ac4 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -20,5 +20,6 @@ obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o +obj-$(CONFIG_RESET_UNIPHIER_USB3) += reset-uniphier-usb3.o obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o diff --git a/drivers/reset/reset-uniphier-usb3.c b/drivers/reset/reset-uniphier-usb3.c new file mode 100644 index 0000000..ffa1b19 --- /dev/null +++ b/drivers/reset/reset-uniphier-usb3.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// reset-uniphier-usb3.c - USB3 reset driver for UniPhier +// Copyright 2018 Socionext Inc. +// Author: Kunihiko Hayashi + +#include +#include +#include +#include +#include + +#include "reset-simple.h" + +#define MAX_CLKS 2 +#define MAX_RSTS 2 + +struct uniphier_usb3_reset_soc_data { + int nclks; + const char * const *clock_names; + int nrsts; + const char * const *reset_names; +}; + +struct uniphier_usb3_reset_priv { + struct clk_bulk_data clk[MAX_CLKS]; + struct reset_control *rst[MAX_RSTS]; + struct reset_simple_data rdata; + const struct uniphier_usb3_reset_soc_data *data; +}; + +static int uniphier_usb3_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct uniphier_usb3_reset_priv *priv; + struct resource *res; + resource_size_t size; + const char *name; + int i, ret, nr; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->data = of_device_get_match_data(dev); + if (WARN_ON(!priv->data || priv->data->nclks > MAX_CLKS || + priv->data->nrsts > MAX_RSTS)) + return -EINVAL; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + size = resource_size(res); + priv->rdata.membase = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->rdata.membase)) + return PTR_ERR(priv->rdata.membase); + + for (i = 0; i < priv->data->nclks; i++) + priv->clk[i].id = priv->data->clock_names[i]; + ret = devm_clk_bulk_get(dev, priv->data->nclks, priv->clk); + if (ret) + return ret; + + for (i = 0; i < priv->data->nrsts; i++) { + name = priv->data->reset_names[i]; + priv->rst[i] = devm_reset_control_get_shared(dev, name); + if (IS_ERR(priv->rst[i])) + return PTR_ERR(priv->rst[i]); + } + + ret = clk_bulk_prepare_enable(priv->data->nclks, priv->clk); + if (ret) + return ret; + + for (nr = 0; nr < priv->data->nrsts; nr++) { + ret = reset_control_deassert(priv->rst[nr]); + if (ret) + goto out_rst_assert; + } + + spin_lock_init(&priv->rdata.lock); + priv->rdata.rcdev.owner = THIS_MODULE; + priv->rdata.rcdev.nr_resets = size * BITS_PER_BYTE; + priv->rdata.rcdev.ops = &reset_simple_ops; + priv->rdata.rcdev.of_node = dev->of_node; + priv->rdata.active_low = true; + + platform_set_drvdata(pdev, priv); + + ret = devm_reset_controller_register(dev, &priv->rdata.rcdev); + if (ret) + goto out_rst_assert; + + return 0; + +out_rst_assert: + while (nr--) + reset_control_assert(priv->rst[nr]); + + clk_bulk_disable_unprepare(priv->data->nclks, priv->clk); + + return ret; +} + +static int uniphier_usb3_reset_remove(struct platform_device *pdev) +{ + struct uniphier_usb3_reset_priv *priv = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < priv->data->nrsts; i++) + reset_control_assert(priv->rst[i]); + + clk_bulk_disable_unprepare(priv->data->nclks, priv->clk); + + return 0; +} + +static const char * const uniphier_pro4_clock_reset_names[] = { + "gio", "link", +}; + +static const struct uniphier_usb3_reset_soc_data uniphier_pro4_data = { + .nclks = ARRAY_SIZE(uniphier_pro4_clock_reset_names), + .clock_names = uniphier_pro4_clock_reset_names, + .nrsts = ARRAY_SIZE(uniphier_pro4_clock_reset_names), + .reset_names = uniphier_pro4_clock_reset_names, +}; + +static const char * const uniphier_pxs2_clock_reset_names[] = { + "link", +}; + +static const struct uniphier_usb3_reset_soc_data uniphier_pxs2_data = { + .nclks = ARRAY_SIZE(uniphier_pxs2_clock_reset_names), + .clock_names = uniphier_pxs2_clock_reset_names, + .nrsts = ARRAY_SIZE(uniphier_pxs2_clock_reset_names), + .reset_names = uniphier_pxs2_clock_reset_names, +}; + +static const struct of_device_id uniphier_usb3_reset_match[] = { + { + .compatible = "socionext,uniphier-pro4-usb3-reset", + .data = &uniphier_pro4_data, + }, + { + .compatible = "socionext,uniphier-pxs2-usb3-reset", + .data = &uniphier_pxs2_data, + }, + { + .compatible = "socionext,uniphier-ld20-usb3-reset", + .data = &uniphier_pxs2_data, + }, + { + .compatible = "socionext,uniphier-pxs3-usb3-reset", + .data = &uniphier_pxs2_data, + }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, uniphier_usb3_reset_match); + +static struct platform_driver uniphier_usb3_reset_driver = { + .probe = uniphier_usb3_reset_probe, + .remove = uniphier_usb3_reset_remove, + .driver = { + .name = "uniphier-usb3-reset", + .of_match_table = uniphier_usb3_reset_match, + }, +}; +module_platform_driver(uniphier_usb3_reset_driver); + +MODULE_AUTHOR("Kunihiko Hayashi "); +MODULE_DESCRIPTION("UniPhier USB3 Reset Driver"); +MODULE_LICENSE("GPL");