From patchwork Wed May 26 18:28:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 448212 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp5476251jac; Wed, 26 May 2021 11:28:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzHF4CPqiGMPnB+7CqIpwK45fbbZxhcW+dKFmV/W3HNcNiGY7Jkz1QAgopX9JIWXDdkcfJ3 X-Received: by 2002:a5d:9804:: with SMTP id a4mr27340781iol.164.1622053696722; Wed, 26 May 2021 11:28:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622053696; cv=none; d=google.com; s=arc-20160816; b=C/cRGYFwdtGdVK4yfmMUpajwKXIw3iqZKW50wbVScKR+YeA6tRvE52ryjPOK/oxngf T81E2+YmtwkvWrjvcHh7RzrG5K4ycremfHVftLHrWZN3ulG0t90qzFuOqobKnb44WeNP isQTiavjik8Z227QqMeM4wtWXRfGdlPGHHzQeVZNNHPoXOLTStdcHPGL1BmmjQl2/kwy ks8K7YHIzrc2ea/g2DTyCfFLd5iIKG3SAKGiKOyGMm9sME23iVF1lsP1LSTns1ATsSr4 70+Dl/MyDYGMww5lDD3XOEwUuTmVI++t+GQTU92j+Nfrvh1Xcu+rBp/A0wc3swRcs/Rb MnWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=8xGGRMWSUmIXRc3g7rCaGNqJOT2Gb6dpWAylSpBDmWg=; b=UPULwyzI566PIGjACAbIhHfbgOR1AfS2lU1YkzULzcfulaS1MAnWZVheZceYLTHQgT ac+aAT7NPozGm+CEj/f5HOkptCHBZb7AKOUkV+SHRILRhQ9OEzTIFMkgujKtAwu3vEOb ibJiJgiORNevyxTzywEnPjMDw27EOJyks29Il1q3j0hqO5K8oDNe/sG4raXUm+ptcDFp kvSnkTiFpI4gmBd+Zy/Csi8bfOBJPbOJ7rdsMq6+137A7IeA4PtH16e3ZZ/nFT5dWjYo 50MUgwd/rKzCcavbppVHaP+Bbn6DcdbwqtMbLWq2+uI4dAELD7tmp4xTulTsumfvKEWo T0vw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n12si99222jat.1.2021.05.26.11.28.16; Wed, 26 May 2021 11:28:16 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235493AbhEZS3r (ORCPT + 7 others); Wed, 26 May 2021 14:29:47 -0400 Received: from foss.arm.com ([217.140.110.172]:48480 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232262AbhEZS3r (ORCPT ); Wed, 26 May 2021 14:29:47 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8E3F0143B; Wed, 26 May 2021 11:28:15 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6FEFA3F73B; Wed, 26 May 2021 11:28:14 -0700 (PDT) From: Sudeep Holla To: devicetree@vger.kernel.org Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, Rob Herring , Cristian Marussi , Kevin Hilman , Neil Armstrong , Jerome Brunet Subject: [PATCH 1/8] dt-bindings: firmware: arm, scpi: Move arm, scpi-shmem to json schema Date: Wed, 26 May 2021 19:28:00 +0100 Message-Id: <20210526182807.548118-2-sudeep.holla@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526182807.548118-1-sudeep.holla@arm.com> References: <20210526182807.548118-1-sudeep.holla@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move the SRAM and shared memory binding for SCPI into the existing Generic on-chip SRAM. We just need to update the compatible list and there-by remove the whole old text format binding for the same. Cc: Rob Herring Cc: Kevin Hilman Cc: Neil Armstrong Cc: Jerome Brunet Signed-off-by: Sudeep Holla --- .../devicetree/bindings/arm/arm,scpi.txt | 15 --------------- Documentation/devicetree/bindings/sram/sram.yaml | 1 + 2 files changed, 1 insertion(+), 15 deletions(-) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt index bcd6c3ec471e..bcb8b3d61e68 100644 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt @@ -56,21 +56,6 @@ Sub-nodes node. It can be non linear and hence provide the mapping of identifiers into the clock-output-names array. -SRAM and Shared Memory for SCPI -------------------------------- - -A small area of SRAM is reserved for SCPI communication between application -processors and SCP. - -The properties should follow the generic mmio-sram description found in [3] - -Each sub-node represents the reserved area for SCPI. - -Required sub-node properties: -- reg : The base offset and size of the reserved area with the SRAM -- compatible : should be "arm,scp-shmem" for Non-secure SRAM based - shared memory - Sensor bindings for the sensors based on SCPI Message Protocol -------------------------------------------------------------- SCPI provides an API to access the various sensors on the SoC. diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index c1a5afa73cfe..e9946ed15964 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -80,6 +80,7 @@ description: |+ - amlogic,meson8b-smp-sram - amlogic,meson-gxbb-scp-shmem - amlogic,meson-axg-scp-shmem + - arm,scpi-shmem - renesas,smp-sram - rockchip,rk3066-smp-sram - samsung,exynos4210-sysram From patchwork Wed May 26 18:28:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 448213 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp5476277jac; Wed, 26 May 2021 11:28:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxD+m27Z58ON/rpCApx2kvmAK73DYccsZYRztAmNFK6lx7+iGEafDUaTqoI/eJIYteDsgtc X-Received: by 2002:a02:aa97:: with SMTP id u23mr4394537jai.13.1622053697691; Wed, 26 May 2021 11:28:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622053697; cv=none; d=google.com; s=arc-20160816; b=ICuHXt3SjzADz1pdcmV+cik/UzIawk1GUDjwJ6cjYU5qOywQfP7JUcr4klxV12xMq/ 53Aw1vTUKpFdAtqypRhvTOLAHZyvVsfom0K7AObdF4eSi2mv0FK77JKK/0Bx4vbkslOV NVAn99GA5Ful6lk/yg4md8vvn2uR0Ul6lhmHX3JNsX0Yuje8ytpN+955Ehrm1vkxKSXE 7PreOjyQTluNoOxz/tieUN3JNzJH1GXMovbYT4eaENTra1Fr9O9RlgTAieJ8sqQKURJb /bvsjxnncIVGprvNY+LcbuPY8fkV7k2a4aO5OBFRqIrHjy/sw4jWk6SEMsgNM8YrQXYm 2ltQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=s4Bw8VPc0aGAtOv5UUvf8+xtOXOMBF/VdbWp+OunHgk=; b=VgAqX9ZT7i+RuJvCucLV+DzcfMyrM5EPyQXlChXTbthr7DoXLJOAUdCbhs4R5IYoYi WXC6W5ZZcnf+0VOJGfFzroFTXSNXUr3Wl9FE+ABnM0yTb79JLi3cVOdKg2J9QgBT9BSq Ls3bnkQ5mh22EsRqkofXpYApdPjpkO5dk6cNU3RXa1TkOl6Wk/9K2dZF07CU+FYgt0mg RGikGqW7WymPRUo+SuXh9qnESv8VXZT4HSr/VQkqLCmbgkmOEHx7RODHd9UMuu0pWeJE Ixmgr8LbjW6e21LVV+2SVkbGCaMPudPWCmLi+Fqy0G2GQPgCP90GOTotDLV2cjp9gZfY rKiA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n12si99222jat.1.2021.05.26.11.28.17; Wed, 26 May 2021 11:28:17 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235501AbhEZS3s (ORCPT + 7 others); Wed, 26 May 2021 14:29:48 -0400 Received: from foss.arm.com ([217.140.110.172]:48486 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232262AbhEZS3s (ORCPT ); Wed, 26 May 2021 14:29:48 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A8C691476; Wed, 26 May 2021 11:28:16 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BFF8A3F73B; Wed, 26 May 2021 11:28:15 -0700 (PDT) From: Sudeep Holla To: devicetree@vger.kernel.org Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, Rob Herring , Cristian Marussi , Florian Fainelli Subject: [PATCH 2/8] dt-bindings: firmware: arm, scmi: Move arm, scmi-shmem to json schema Date: Wed, 26 May 2021 19:28:01 +0100 Message-Id: <20210526182807.548118-3-sudeep.holla@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526182807.548118-1-sudeep.holla@arm.com> References: <20210526182807.548118-1-sudeep.holla@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move the SRAM and shared memory binding for SCMI into the existing Generic on-chip SRAM. We just need to update the compatible list and there-by remove the whole old text format binding for the same. Cc: Rob Herring Cc: Cristian Marussi Cc: Florian Fainelli Signed-off-by: Sudeep Holla --- .../devicetree/bindings/arm/arm,scmi.txt | 15 --------------- Documentation/devicetree/bindings/sram/sram.yaml | 1 + 2 files changed, 1 insertion(+), 15 deletions(-) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/arm/arm,scmi.txt b/Documentation/devicetree/bindings/arm/arm,scmi.txt index 667d58e0a659..b7be2000afcb 100644 --- a/Documentation/devicetree/bindings/arm/arm,scmi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scmi.txt @@ -106,21 +106,6 @@ signal binding[5]. - #reset-cells : Should be 1. Contains the reset domain ID value used by SCMI commands. -SRAM and Shared Memory for SCMI -------------------------------- - -A small area of SRAM is reserved for SCMI communication between application -processors and SCP. - -The properties should follow the generic mmio-sram description found in [4] - -Each sub-node represents the reserved area for SCMI. - -Required sub-node properties: -- reg : The base offset and size of the reserved area with the SRAM -- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based - shared memory - [0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/power/power-domain.yaml diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index e9946ed15964..364d66db1b03 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -80,6 +80,7 @@ description: |+ - amlogic,meson8b-smp-sram - amlogic,meson-gxbb-scp-shmem - amlogic,meson-axg-scp-shmem + - arm,scmi-shmem - arm,scpi-shmem - renesas,smp-sram - rockchip,rk3066-smp-sram From patchwork Wed May 26 18:28:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 448214 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp5476292jac; Wed, 26 May 2021 11:28:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwpSSglnPsbfQrHtSdVYYYX3ptiWOR8IkGHuAR2qFz9o1SGIZkcOBSNYPb9/jfgEGHWX6X8 X-Received: by 2002:a02:5289:: with SMTP id d131mr4530000jab.121.1622053698881; Wed, 26 May 2021 11:28:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622053698; cv=none; d=google.com; s=arc-20160816; b=nqfX/5EVlZGDw6iFrt7vKjOmIVOhDGJras1eoSaHUO6g8bl0keaTxW8dCxH6qimNXq TQSyiDhiGsDd/9AMsY6Rw4keUou/qODsVVmzFyvYsWAGghhhsmje5MNypKVlueqP/Xtz SVvLrr969fcU2wlLV6oHkF5erCuNZwMrt7+e6LDrwkFUyhUd811AjKCktiG1mgM0KjnM r59d2E88+Q/gNA4SZxiaYZvRPg43d7gylwudGYhOVROgnoa7Sq7U9OmyeqT2BZ+VTS/J t9IwRsUlw83sz3iWpB4sWndkK3bm02U4H0XI++yUmQgYLB9q3uN3DyE5LKxsswYYwq0e fESw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=P4VJS/0EZeU7YB2hkU3pjOxNxMqUInuxFzSR5qXMCSA=; b=aEpyIeztfbAYUq4ZzJUFTrn1XmjSH/I5WsZmLky3nQ2Ex2ooo5EkXzATG5u67ZX9Sn grcyktmTmajfl3dHcJTA+US4Aya4wTSJUKZyv0iAhlVt3v8/wTvTZUBF1VhWrKuVIkjl QIj4H3KOukRSLgH509AB4RuBkbuqbGIlootrxq3rvgEJmjrPkOYeGKgocM6105GgkQYg Ka/jSrOX4PUZnEaBWbCmtMVHhJfK4W8vsVUnqLyKBfPThz4EGSiAo226jSEATXCBH/Cr uxt+aLHEOWP0KM//AhEqcK1GRce2yDwJ1LaYmlVVrUB5kBQPWKCHmIAxJAgEl9bNuOEw Hazg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n12si99222jat.1.2021.05.26.11.28.18; Wed, 26 May 2021 11:28:18 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235504AbhEZS3t (ORCPT + 7 others); Wed, 26 May 2021 14:29:49 -0400 Received: from foss.arm.com ([217.140.110.172]:48492 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232262AbhEZS3t (ORCPT ); Wed, 26 May 2021 14:29:49 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AC8801477; Wed, 26 May 2021 11:28:17 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DBA8B3F73B; Wed, 26 May 2021 11:28:16 -0700 (PDT) From: Sudeep Holla To: devicetree@vger.kernel.org Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, Rob Herring , Cristian Marussi Subject: [PATCH 3/8] dt-bindings: firmware: juno, scpi: Move to sram.yaml json schema Date: Wed, 26 May 2021 19:28:02 +0100 Message-Id: <20210526182807.548118-4-sudeep.holla@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526182807.548118-1-sudeep.holla@arm.com> References: <20210526182807.548118-1-sudeep.holla@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit a90b15e0ad72 ("Documentation: bindings: decouple juno specific details from generic binding") moved the juno specific bindings into separate file. Though there was no need for juno specific binding, it has been used unfortunately for whatever stupid reason I added it for. Let us move the same to the generic sram.yaml schema and remove the old text format binding. Cc: Rob Herring Signed-off-by: Sudeep Holla --- .../devicetree/bindings/arm/juno,scpi.txt | 26 ------------------- .../devicetree/bindings/sram/sram.yaml | 2 ++ 2 files changed, 2 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/juno,scpi.txt -- 2.25.1 diff --git a/Documentation/devicetree/bindings/arm/juno,scpi.txt b/Documentation/devicetree/bindings/arm/juno,scpi.txt deleted file mode 100644 index 2ace8696bbee..000000000000 --- a/Documentation/devicetree/bindings/arm/juno,scpi.txt +++ /dev/null @@ -1,26 +0,0 @@ -System Control and Power Interface (SCPI) Message Protocol -(in addition to the standard binding in [0]) - -Juno SRAM and Shared Memory for SCPI ------------------------------------- - -Required properties: -- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM - -Each sub-node represents the reserved area for SCPI. - -Required sub-node properties: -- reg : The base offset and size of the reserved area with the SRAM -- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based - shared memory on Juno platforms - -Sensor bindings for the sensors based on SCPI Message Protocol --------------------------------------------------------------- -Required properties: -- compatible : should be "arm,scpi-sensors". -- #thermal-sensor-cells: should be set to 1. - For Juno R0 and Juno R1 refer to [1] for the - sensor identifiers - -[0] Documentation/devicetree/bindings/arm/arm,scpi.txt -[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 364d66db1b03..0d494af609b7 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -28,6 +28,7 @@ description: |+ contains: enum: - mmio-sram + - arm,juno-sram-ns - atmel,sama5d2-securam - rockchip,rk3288-pmu-sram @@ -80,6 +81,7 @@ description: |+ - amlogic,meson8b-smp-sram - amlogic,meson-gxbb-scp-shmem - amlogic,meson-axg-scp-shmem + - arm,juno-scp-shmem - arm,scmi-shmem - arm,scpi-shmem - renesas,smp-sram From patchwork Wed May 26 18:28:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 448215 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp5476307jac; Wed, 26 May 2021 11:28:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwgw8mAVZFj7KtL+ewXed050FoegJKJbBdFkIXWUAvXuzVhzyCoJx4StgPeh1HTgCH1xqtH X-Received: by 2002:a05:6638:1382:: with SMTP id w2mr4552321jad.78.1622053700581; Wed, 26 May 2021 11:28:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622053700; cv=none; d=google.com; s=arc-20160816; b=baIRj+aS3HSRwJHYDyNSvNsH72zzDGFn5X1ZMnG+bg/92/a3wjQk/e0jSRnZI4y3v/ 1ctMaUYS/xoPmU9OERSNkQYP+KxN/HpyaSUDPAMs3Q1w8qbvt35wNynG7H0WSU/Syc5s ZB3nAwNcckad+96ehvuq5leYTLEEP6gMR1QnAuDuNA7zHfYo4C6mXCZX8p5UiTpxCtzQ 3iNZzij5nRRQmVRDlNv8u6GeenOpaQwuby481Kmg8KI5fi68kkPK1EPaSMwvPRWq/M/b CIOCvTjhP4E+cFdJQ+i8Y71XFvmVJ+Ba4WrycsfSxtQf4EtyO9hJXsdoL9wZSa3PtwfT 0XKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=NUWOWjQ31QJx8BkSKTOvt4zNa4MNCc1Y8Lc5N6TUv3w=; b=CYj/hPrAntDCKvs4WsUe2dT6x6zRhCpTlbLuY1Qww1TnVSY7ZTiCQ1Khag/CtLFtGw mo3gXrwnZ1lXnbZF6tMBOq0HYXa9gIWowIyIq9g+hTVRLC5ba+pfyrhW5MVDYSabHQur jcFFJLG2cTviX7f/GIpKpwiL52ZvrjI7oQ8S9QfmQBD4K7MC50DKHT1/eUkaWDjqQ0n6 bGRyPnoSszo5D+Fq2o/AgsS7/byfSpeIsNDAymQY6+RPB/win4HArqQ04HoUlSEya9zi ERbDJEDF98DtsyfV+R4VE/nILyhGUTCTb/rY8UXz8K5A3Pp8vsLGwUZkQGfLFDo/UCQL 0VkQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n12si99222jat.1.2021.05.26.11.28.20; Wed, 26 May 2021 11:28:20 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235505AbhEZS3v (ORCPT + 7 others); Wed, 26 May 2021 14:29:51 -0400 Received: from foss.arm.com ([217.140.110.172]:48502 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232262AbhEZS3u (ORCPT ); Wed, 26 May 2021 14:29:50 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 08CC013A1; Wed, 26 May 2021 11:28:19 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DF98E3F73B; Wed, 26 May 2021 11:28:17 -0700 (PDT) From: Sudeep Holla To: devicetree@vger.kernel.org Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, Rob Herring , Cristian Marussi , Kevin Hilman , Neil Armstrong , Jerome Brunet Subject: [PATCH 4/8] dt-bindings: firmware: amlogic, scpi: Move arm, scpi-shmem to json schema Date: Wed, 26 May 2021 19:28:03 +0100 Message-Id: <20210526182807.548118-5-sudeep.holla@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526182807.548118-1-sudeep.holla@arm.com> References: <20210526182807.548118-1-sudeep.holla@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org "amlogic,meson-gxbb-scp-shmem" is already in the Generic on-chip SRAM binding though "amlogic,meson-gxbb-scpi" is missing which is now added. Also remove the whole old text format binding for the same. Cc: Rob Herring Cc: Kevin Hilman Cc: Neil Armstrong Cc: Jerome Brunet Signed-off-by: Sudeep Holla --- .../devicetree/bindings/arm/amlogic,scpi.txt | 12 ------------ Documentation/devicetree/bindings/sram/sram.yaml | 1 + 2 files changed, 1 insertion(+), 12 deletions(-) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt index 5ab59da052df..ebfe302fb747 100644 --- a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt +++ b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt @@ -5,18 +5,6 @@ Required properties - compatible : should be "amlogic,meson-gxbb-scpi" -AMLOGIC SRAM and Shared Memory for SCPI ------------------------------------- - -Required properties: -- compatible : should be "amlogic,meson-gxbb-sram" - -Each sub-node represents the reserved area for SCPI. - -Required sub-node properties: -- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared - memory on Amlogic GXBB SoC. - Sensor bindings for the sensors based on SCPI Message Protocol -------------------------------------------------------------- SCPI provides an API to access the various sensors on the SoC. diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 0d494af609b7..c73a27c995ad 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -28,6 +28,7 @@ description: |+ contains: enum: - mmio-sram + - amlogic,meson-gxbb-sram - arm,juno-sram-ns - atmel,sama5d2-securam - rockchip,rk3288-pmu-sram From patchwork Wed May 26 18:28:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 448216 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp5476318jac; Wed, 26 May 2021 11:28:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzxScfyE06oFUDPE+zHS3CJGcSsxuZv3BFATI1Pj0DjHeMjViRH6r32KE3xmnpvTjHoY4z4 X-Received: by 2002:a6b:3119:: with SMTP id j25mr23461630ioa.64.1622053701720; Wed, 26 May 2021 11:28:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622053701; cv=none; d=google.com; s=arc-20160816; b=t6BBvS1xQ4rrZBypMnxBQQKG3cCCy98n3OZLAqG9dyX6805aAVqAQbmsFSt5k3bTcZ LYLMAAHx7/r2tuM3bb9aZ8yO1cP5sC3ZaavTOlgc78iMEv2J+wbmy1itjrTcldD2IY+J gqFVARlWMztmUuNfCyCzBNhiwtdpPw0qKiRr6E0oR0WtRxXrM6LljLWdH+WoreiVZ1pM v5YaH8YrIxmTTufMHOdiEkGTEtMW7KGxn439+QEPsqCYIEZQ15J4Yo8M7vVcBcaanGWn OLzcZx0Z72GRwbnYisUuignGECmjaPGi1pzzLP83g4NoC/TaHYRDf0YAKJTRAemNZgpF mUjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=aE8OHamfJUksLkHrPiCzbnWE0mTSK7De6xD7YZXiNvg=; b=d+UesUqmqQ5mh52mAGIxVbr/bhA1FLoKAdnEEue9HKBHZO2kwxAitY59dHCzapSG3J bGOqQLYqCE3f1fOdvoKa/v8FzapjIhcirhdN785srKupOBCF4jBlBKHzEeAgioVku361 9f5uFYVFhFbCyG8XNUD43cOC0F61BE2xp4bZ2SrzyrYrdLcUVgcVm1GSFr+aig23femD V4ijPxjIMD9a8aR8i0lpXvTW3lYwNcfdTjvilm1I9kRQEmxu4PZVYbLCKwUA93+9uOzQ dztQshAqSFJnnaVKqTkuY4FncJw1c4XiMGPJZYbLvP4bWLSoR9e0/By1jfzpZ1kbLbIJ fcMg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n12si99222jat.1.2021.05.26.11.28.21; Wed, 26 May 2021 11:28:21 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235507AbhEZS3w (ORCPT + 7 others); Wed, 26 May 2021 14:29:52 -0400 Received: from foss.arm.com ([217.140.110.172]:48516 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232262AbhEZS3w (ORCPT ); Wed, 26 May 2021 14:29:52 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 74DBD1476; Wed, 26 May 2021 11:28:20 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3D06D3F73B; Wed, 26 May 2021 11:28:19 -0700 (PDT) From: Sudeep Holla To: devicetree@vger.kernel.org Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, Rob Herring , Cristian Marussi , Kevin Hilman , Neil Armstrong , Jerome Brunet Subject: [PATCH 5/8] dt-bindings: firmware: arm, scpi: Convert to json schema Date: Wed, 26 May 2021 19:28:04 +0100 Message-Id: <20210526182807.548118-6-sudeep.holla@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526182807.548118-1-sudeep.holla@arm.com> References: <20210526182807.548118-1-sudeep.holla@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the old text format binding for System Control and Power Interface (SCPI) Message Protocol into the new and shiny YAML format. Cc: Rob Herring Cc: Kevin Hilman Cc: Neil Armstrong Cc: Jerome Brunet Cc: Viresh Kumar --- .../devicetree/bindings/arm/arm,scpi.txt | 204 ------------- .../bindings/firmware/arm,scpi.yaml | 284 ++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 285 insertions(+), 205 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/arm,scpi.txt create mode 100644 Documentation/devicetree/bindings/firmware/arm,scpi.yaml -- 2.25.1 diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt deleted file mode 100644 index bcb8b3d61e68..000000000000 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ /dev/null @@ -1,204 +0,0 @@ -System Control and Power Interface (SCPI) Message Protocol ----------------------------------------------------------- - -Firmware implementing the SCPI described in ARM document number ARM DUI 0922B -("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used -by Linux to initiate various system control and power operations. - -Required properties: - -- compatible : should be - * "arm,scpi" : For implementations complying to SCPI v1.0 or above - * "arm,scpi-pre-1.0" : For implementations complying to all - unversioned releases prior to SCPI v1.0 -- mboxes: List of phandle and mailbox channel specifiers - All the channels reserved by remote SCP firmware for use by - SCPI message protocol should be specified in any order -- shmem : List of phandle pointing to the shared memory(SHM) area between the - processors using these mailboxes for IPC, one for each mailbox - SHM can be any memory reserved for the purpose of this communication - between the processors. - -See Documentation/devicetree/bindings/mailbox/mailbox.txt -for more details about the generic mailbox controller and -client driver bindings. - -Clock bindings for the clocks based on SCPI Message Protocol ------------------------------------------------------------- - -This binding uses the common clock binding[1]. - -Container Node -============== -Required properties: -- compatible : should be "arm,scpi-clocks" - All the clocks provided by SCP firmware via SCPI message - protocol much be listed as sub-nodes under this node. - -Sub-nodes -========= -Required properties: -- compatible : shall include one of the following - "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based. - These clocks don't provide an entire range of values between the - limits but only discrete points within the range. The firmware - provides the mapping for each such operating frequency and the - index associated with it. The firmware also manages the - voltage scaling appropriately with the clock scaling. - "arm,scpi-variable-clocks" - all the clocks that are variable and provide full - range within the specified range. The firmware provides the - range of values within a specified range. - -Other required properties for all clocks(all from common clock binding): -- #clock-cells : Should be 1. Contains the Clock ID value used by SCPI commands. -- clock-output-names : shall be the corresponding names of the outputs. -- clock-indices: The identifying number for the clocks(i.e.clock_id) in the - node. It can be non linear and hence provide the mapping of identifiers - into the clock-output-names array. - -Sensor bindings for the sensors based on SCPI Message Protocol --------------------------------------------------------------- -SCPI provides an API to access the various sensors on the SoC. - -Required properties: -- compatible : should be "arm,scpi-sensors". -- #thermal-sensor-cells: should be set to 1. This property follows the - thermal device tree bindings[2]. - - Valid cell values are raw identifiers (Sensor ID) - as used by the firmware. Refer to platform details - for your implementation for the IDs to use. - -Power domain bindings for the power domains based on SCPI Message Protocol ------------------------------------------------------------- - -This binding uses the generic power domain binding[4]. - -PM domain providers -=================== - -Required properties: - - #power-domain-cells : Should be 1. Contains the device or the power - domain ID value used by SCPI commands. - - num-domains: Total number of power domains provided by SCPI. This is - needed as the SCPI message protocol lacks a mechanism to - query this information at runtime. - -PM domain consumers -=================== - -Required properties: - - power-domains : A phandle and PM domain specifier as defined by bindings of - the power controller specified by phandle. - -[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/thermal/thermal*.yaml -[3] Documentation/devicetree/bindings/sram/sram.yaml -[4] Documentation/devicetree/bindings/power/power-domain.yaml - -Example: - -sram: sram@50000000 { - compatible = "arm,juno-sram-ns", "mmio-sram"; - reg = <0x0 0x50000000 0x0 0x10000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x50000000 0x10000>; - - cpu_scp_lpri: scp-shmem@0 { - compatible = "arm,juno-scp-shmem"; - reg = <0x0 0x200>; - }; - - cpu_scp_hpri: scp-shmem@200 { - compatible = "arm,juno-scp-shmem"; - reg = <0x200 0x200>; - }; -}; - -mailbox: mailbox0@40000000 { - .... - #mbox-cells = <1>; -}; - -scpi_protocol: scpi@2e000000 { - compatible = "arm,scpi"; - mboxes = <&mailbox 0 &mailbox 1>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: scpi_clocks@0 { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>, <1>, <2>; - clock-output-names = "atlclk", "aplclk","gpuclk"; - }; - scpi_clk: scpi_clocks@3 { - compatible = "arm,scpi-variable-clocks"; - #clock-cells = <1>; - clock-indices = <3>, <4>; - clock-output-names = "pxlclk0", "pxlclk1"; - }; - }; - - scpi_sensors0: sensors { - compatible = "arm,scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - - scpi_devpd: scpi-power-domains { - compatible = "arm,scpi-power-domains"; - num-domains = <2>; - #power-domain-cells = <1>; - }; -}; - -cpu@0 { - ... - reg = <0 0>; - clocks = <&scpi_dvfs 0>; -}; - -hdlcd@7ff60000 { - ... - reg = <0 0x7ff60000 0 0x1000>; - clocks = <&scpi_clk 4>; - power-domains = <&scpi_devpd 1>; -}; - -thermal-zones { - soc_thermal { - polling-delay-passive = <100>; - polling-delay = <1000>; - - /* sensor ID */ - thermal-sensors = <&scpi_sensors0 3>; - ... - }; -}; - -In the above example, the #clock-cells is set to 1 as required. -scpi_dvfs has 3 output clocks namely: atlclk, aplclk, and gpuclk with 0, -1 and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0 -and pxlclk1 with 3 and 4 as clock-indices. - -The first consumer in the example is cpu@0 and it has '0' as the clock -specifier which points to the first entry in the output clocks of -scpi_dvfs i.e. "atlclk". - -Similarly the second example is hdlcd@7ff60000 and it has pxlclk1 as input -clock. '4' in the clock specifier here points to the second entry -in the output clocks of scpi_clocks i.e. "pxlclk1" - -The thermal-sensors property in the soc_thermal node uses the -temperature sensor provided by SCP firmware to setup a thermal -zone. The ID "3" is the sensor identifier for the temperature sensor -as used by the firmware. - -The num-domains property in scpi-power-domains domain specifies that -SCPI provides 2 power domains. The hdlcd node uses the power domain with -domain ID 1. diff --git a/Documentation/devicetree/bindings/firmware/arm,scpi.yaml b/Documentation/devicetree/bindings/firmware/arm,scpi.yaml new file mode 100644 index 000000000000..9c115e9c1536 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/arm,scpi.yaml @@ -0,0 +1,284 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2021 ARM Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/arm,scpi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: System Control and Power Interface (SCPI) Message Protocol bindings + +maintainers: + - Sudeep Holla + +description: | + Firmware implementing the SCPI described in ARM document number ARM DUI + 0922B ("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be + used by Linux to initiate various system control and power operations. + + This binding is intended to define the interface the firmware implementing + the SCPI provide for OSPM in the device tree. + + [0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html + +properties: + $nodename: + const: scpi + + compatible: + oneOf: + - description: SCPI compliant firmware complying to SCPI v1.0 or above + items: + - const: arm,scpi + - description: | + SCPI compliant firmware complying to all unversioned releases prior + to SCPI v1.0 + items: + - const: arm,scpi-pre-1.0 + + mboxes: + description: | + List of phandle and mailbox channel specifiers. All the channels reserved + by remote SCP firmware for use by SCPI message protocol should be + specified in any order. + minItems: 1 + + shmem: + description: | + List of phandle pointing to the shared memory(SHM) area between the + processors using these mailboxes for IPC, one for each mailbox SHM can + be any memory reserved for the purpose of this communication between the + processors. + minItems: 1 + +additionalProperties: + type: object + +patternProperties: + "^(sensors|power-domains)(-[0-9a-f]+)?$": + type: object + description: | + Each sub-node represents one of the controller - power domains or sensors. + + properties: + compatible: + oneOf: + - const: arm,scpi-sensors + - const: arm,scpi-power-domains + + "^clocks(-[0-9a-f]+)?$": + type: object + description: | + Each sub-node represents one of the types of clock controller - + indexed or full range. + + "arm,scpi-dvfs-clocks" - all the clocks that are variable and index + based. These clocks don't provide an entire range of values + between the limits but only discrete points within the range. The + firmware provides the mapping for each such operating frequency + and the index associated with it. The firmware also manages the + voltage scaling appropriately with the clock scaling. + + "arm,scpi-variable-clocks" - all the clocks that are variable and + provide full range within the specified range. The firmware + provides the range of values within a specified range. + + properties: + compatible: + oneOf: + - const: arm,scpi-dvfs-clocks + - const: arm,scpi-variable-clocks + +required: + - compatible + - mboxes + - shmem + +allOf: + - if: + properties: + compatible: + contains: + const: arm,scpi-sensors + then: + properties: + '#thermal-sensor-cells': + const: 1 + + required: + - '#thermal-sensor-cells' + + - if: + properties: + compatible: + contains: + const: arm,scpi-power-domains + then: + properties: + '#power-domain-cells': + const: 1 + + num-domains: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Total number of power domains provided by SCPI. This is needed as + the SCPI message protocol lacks a mechanism to query this + information at runtime. + + required: + - '#power-domain-cells' + - num-domains + + - if: + properties: + compatible: + contains: + enum: + - arm,scpi-dvfs-clocks + - arm,scpi-variable-clocks + then: + properties: + '#clock-cells': + const: 1 + clock-output-names: + $ref: /schemas/types.yaml#/definitions/string-array + clock-indices: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + The identifying number for the clocks(i.e.clock_id) in the node. + It can be non linear and hence provide the mapping of identifiers + into the clock-output-names array. + + required: + - '#clock-cells' + - clock-output-names + - clock-indices + +examples: + - | + firmware { + scpi { + compatible = "arm,scpi"; + mboxes = <&mhuA 1>; + shmem = <&cpu_scp_hpri>; /* HP-NonSecure */ + + scpi_devpd: power-domains-0 { + compatible = "arm,scpi-power-domains"; + num-domains = <2>; + #power-domain-cells = <1>; + }; + + clocks { + scpi_dvfs: clocks-0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>, <1>, <2>; + clock-output-names = "atlclk", "aplclk","gpuclk"; + }; + + scpi_clk: clocks-1 { + compatible = "arm,scpi-variable-clocks"; + #clock-cells = <1>; + clock-indices = <3>, <4>; + clock-output-names = "pxlclk0", "pxlclk1"; + }; + }; + + scpi_sensors: sensors-0 { + compatible = "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + + sram@50000000 { + compatible = "mmio-sram"; + reg = <0x0 0x50000000 0x0 0x10000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x10000>; + + cpu_scp_lpri: scp-sram-section@0 { + compatible = "arm,scpi-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_hpri: scp-sram-section@200 { + compatible = "arm,scpi-shmem"; + reg = <0x200 0x200>; + }; + }; + + mhuA: mailbox@2b2f0000 { + #mbox-cells = <1>; + compatible = "arm,mhu", "arm,primecell"; + reg = <0 0x2b2f0000 0 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + gpu@ffe40000 { + compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; + reg = <0x0 0xffe40000 0x0 0x10000>; + interrupts = <0 160 4>, <0 161 4>, <0 162 4>; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&scpi_clk 1>; + power-domains = <&scpi_devpd 8>; + resets = <&scpi_reset 0>, <&scpi_reset 1>; + }; + + display@20930000 { + compatible = "intel,keembay-display"; + reg = <0x0 0x20930000 0x0 0x3000>; + reg-names = "lcd"; + interrupts = <0 33 4>; + clocks = <&scpi_clk 0x83>, + <&scpi_clk 0x0>; + clock-names = "clk_lcd", "clk_pll0"; + + port { + disp_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + + thermal-zones { + soc-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&scpi_sensors0 3>; + + trips { + mpu0_crit: mpu0_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + }; + }; + + cpus { + #size-cells = <0>; + #address-cells = <2>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index bd7aff0c120f..6a12597a86e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17696,7 +17696,7 @@ M: Sudeep Holla R: Cristian Marussi L: linux-arm-kernel@lists.infradead.org S: Maintained -F: Documentation/devicetree/bindings/arm/arm,sc[mp]i.txt +F: Documentation/devicetree/bindings/firmware/arm,sc[mp]i.yaml F: drivers/clk/clk-sc[mp]i.c F: drivers/cpufreq/sc[mp]i-cpufreq.c F: drivers/firmware/arm_scmi/ From patchwork Wed May 26 18:28:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 448217 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp5476337jac; Wed, 26 May 2021 11:28:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwj8dW7J+Jgrw8I2JB1dPY6txV1NQ21kKO0BAIun9YuNWjdFm3nq90KQ2xN1lvvgMvge16q X-Received: by 2002:a05:6e02:1bae:: with SMTP id n14mr30076376ili.129.1622053703507; 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[23.128.96.18]) by mx.google.com with ESMTP id n12si99222jat.1.2021.05.26.11.28.23; Wed, 26 May 2021 11:28:23 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235513AbhEZS3y (ORCPT + 7 others); Wed, 26 May 2021 14:29:54 -0400 Received: from foss.arm.com ([217.140.110.172]:48524 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232262AbhEZS3x (ORCPT ); Wed, 26 May 2021 14:29:53 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 759991477; Wed, 26 May 2021 11:28:21 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A721A3F73B; Wed, 26 May 2021 11:28:20 -0700 (PDT) From: Sudeep Holla To: devicetree@vger.kernel.org Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, Rob Herring , Cristian Marussi Subject: [PATCH 6/8] dt-bindings: mailbox : arm, mhu: Fix arm, scpi example used here Date: Wed, 26 May 2021 19:28:05 +0100 Message-Id: <20210526182807.548118-7-sudeep.holla@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526182807.548118-1-sudeep.holla@arm.com> References: <20210526182807.548118-1-sudeep.holla@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that the arm,scpi binding is converted to YAML format, the following errors are seen when doing `make DT_CHECKER_FLAGS=-m dt_binding_check` >From schema: Documentation/devicetree/bindings/firmware/arm,scpi.yaml Documentation/devicetree/bindings/mailbox/arm,mhu.example.dt.yaml: scpi@2f000000: $nodename:0: 'scpi' was expected Documentation/devicetree/bindings/mailbox/arm,mhu.example.dt.yaml: scpi@2f000000: reg: [[0, 788529152, 0, 512]] is not of type 'object' Documentation/devicetree/bindings/mailbox/arm,mhu.example.dt.yaml: scpi@2f000000: 'shmem' is a required property Fix those error following the SCPI bindings. Cc: Rob Herring Cc: Viresh Kumar --- Documentation/devicetree/bindings/mailbox/arm,mhu.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml index d07eb00b97c8..bfdc3e33565e 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml @@ -126,9 +126,15 @@ additionalProperties: false clock-names = "apb_pclk"; }; - mhu_client_scpi: scpi@2f000000 { + scpi { compatible = "arm,scpi"; - reg = <0 0x2f000000 0 0x200>; mboxes = <&mhuB 1 4>; /* HP-NonSecure, 5th doorbell */ + shmem = <&cpu_scp_hpri>; /* HP-NonSecure */ + + scpi_devpd: power-domains-0 { + compatible = "arm,scpi-power-domains"; + num-domains = <2>; + #power-domain-cells = <1>; + }; }; }; From patchwork Wed May 26 18:28:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 448218 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp5476342jac; Wed, 26 May 2021 11:28:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy4Ol7uXOGZRgtJyA2XWW0GpGqId+qokI08h8y1UTn6ONjXvCG2EQL3hIzX+vPWqCHHwEqJ X-Received: by 2002:a02:6d6c:: with SMTP id e44mr4457365jaf.81.1622053704036; Wed, 26 May 2021 11:28:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622053704; cv=none; d=google.com; s=arc-20160816; b=Uuhb1p42sE8S/sUIeIO7yyKYSsUWmdjDxsp9iYa1WLt0ysEDNePnrsZqQ9dlnEDkeg wpLE8wWa7Coqv+Ib6hgioikHVGq/JcJLTrA+Ckelj0Wmkda7MqPxHgi+YDCNLe+g88ra r0CZJMtrWH/9G+wXO2+UuhM289h+DMNyTXvh0ygNVWg3R3upUvTk+qAMmTRy5FoUnSW8 gpQoUX3BMmv2bQTa4QRjrIXx056ZeX4L/bzDKmzLIrCg/s6J4V6cfVSdJZV4ZWfPNH2i Gk1MoqcCjGapFApmzQ7OjoOX4zX02qLmQB8m58/hYGSVsYf3QEYQqimXPZrqAFSzMajX afDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ubVc8djZj9EfplbDRjgRePaW9aeIXSLeC7/pNj5AIfs=; b=YhlZgNhjebVh9XVKxnC2s4faDaASVml7FE6BcpIPSx7+GR6EyyC13OQ+ZA/NxydlIQ JxDYy0dFLHHpE1ZrtZNznzee2zcHHUVqYq6FXUz7ejh+H8g1eDbgysXdubqo0wjoztid 9OzpnXLOhCcWNwTtoHezxVWjSiNvLGFMbxrSn0I0wzkRr2Qeg95/SlXVRr6K+p6ll10a jXnhm0sfaO5UZSnanLe0Z4X1IQuDsnaAX1YYh/Cu/jEdg/z7A9LRuKg8ItYzuoRwX7PN BQ2Lg/ZMC1VxTNf9+f15dD0yMwGKdKYoYWe8trLWrDao7Ws/z21vJT44yzA7e9okjVz+ AP6A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n12si99222jat.1.2021.05.26.11.28.23; Wed, 26 May 2021 11:28:24 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235506AbhEZS3y (ORCPT + 7 others); Wed, 26 May 2021 14:29:54 -0400 Received: from foss.arm.com ([217.140.110.172]:48530 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232262AbhEZS3y (ORCPT ); Wed, 26 May 2021 14:29:54 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C4D9D13A1; Wed, 26 May 2021 11:28:22 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A59933F73B; Wed, 26 May 2021 11:28:21 -0700 (PDT) From: Sudeep Holla To: devicetree@vger.kernel.org Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, Rob Herring , Cristian Marussi , Kevin Hilman , Neil Armstrong , Jerome Brunet Subject: [PATCH 7/8] dt-bindings: firmware: amlogic, scpi: Convert to json schema Date: Wed, 26 May 2021 19:28:06 +0100 Message-Id: <20210526182807.548118-8-sudeep.holla@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526182807.548118-1-sudeep.holla@arm.com> References: <20210526182807.548118-1-sudeep.holla@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert/merge the existing text format SCPI binding additions for amlogic,scpi into the common arm,scpi json scheme. Couple of things to note: "amlogic,meson-gxbb-scpi" is always used with "arm,scpi-pre-1.0" hence no need for separate "arm,scpi-pre-1.0" standalone entry and "amlogic,meson-gxbb-scpi-sensors" is used always with "arm,scpi-sensors" Cc: Rob Herring Cc: Kevin Hilman Cc: Neil Armstrong Cc: Jerome Brunet Signed-off-by: Sudeep Holla --- .../devicetree/bindings/arm/amlogic,scpi.txt | 15 --------------- .../devicetree/bindings/firmware/arm,scpi.yaml | 4 ++++ 2 files changed, 4 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/amlogic,scpi.txt -- 2.25.1 diff --git a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt deleted file mode 100644 index ebfe302fb747..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt +++ /dev/null @@ -1,15 +0,0 @@ -System Control and Power Interface (SCPI) Message Protocol -(in addition to the standard binding in [0]) ----------------------------------------------------------- -Required properties - -- compatible : should be "amlogic,meson-gxbb-scpi" - -Sensor bindings for the sensors based on SCPI Message Protocol --------------------------------------------------------------- -SCPI provides an API to access the various sensors on the SoC. - -Required properties: -- compatible : should be "amlogic,meson-gxbb-scpi-sensors". - -[0] Documentation/devicetree/bindings/arm/arm,scpi.txt diff --git a/Documentation/devicetree/bindings/firmware/arm,scpi.yaml b/Documentation/devicetree/bindings/firmware/arm,scpi.yaml index 9c115e9c1536..d1179a4ea4e9 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scpi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scpi.yaml @@ -34,6 +34,7 @@ description: | to SCPI v1.0 items: - const: arm,scpi-pre-1.0 + - const: amlogic,meson-gxbb-scpi mboxes: description: | @@ -64,6 +65,9 @@ description: | oneOf: - const: arm,scpi-sensors - const: arm,scpi-power-domains + - items: + - const: amlogic,meson-gxbb-scpi-sensors + - const: arm,scpi-sensors "^clocks(-[0-9a-f]+)?$": type: object From patchwork Wed May 26 18:28:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 448219 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp5476392jac; Wed, 26 May 2021 11:28:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzZVVrJvEK99r23HOLyxFTPdIFx1vI3R73kypac0L5F2XAkNrUSp58Wao25e9smPzYOPLci X-Received: by 2002:a6b:3119:: with SMTP id j25mr23462023ioa.64.1622053708537; Wed, 26 May 2021 11:28:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622053708; cv=none; d=google.com; s=arc-20160816; b=jWsymkQ3bE2PUZ2WVoBlYDpEdSgTy3/ARG2whwVCrBlAFIFltshYNB6pgHu07ijukB brhiNYxh7jMomcG7P05Vn5z13P0PrGhG+u9wO17ppqcWbHpFFXV38VpLvQpyyWlvNcDs vjxVuYNirEz1lZ9avH/aoMFu8UBuD5WtuKhNGDpDrqt4Kg2WTl3lJSOQXoizrLW36wuP OzLg0hPL49+GGsXLKZuyWxS/3B3MnBJ5+6q8dDdfxDMvzrsExzSEb4UPPVzyxZlZram0 WSwe3QY9eQkOx+Wqt6XRYMSMb95nB90Yu3yiz+cT63kFKvzc6RniYItdDn9RmzE+8FuC hGZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=1pNdYVcm5unDKv3Iam6PyIBj5vXU1gzJSTv/ms8YRb0=; b=OzlqVuiRYL497fHd4093E0M8HcTUkK+sHEpoezUY2+o1+vW4tRIZV9YZ8udEM9PQDO s1quNP7a+BU6zUI6rIgnxIQ1pjDAEqvRcWgWEqjwRAHNTqLbWLQZUi83QZce5+bW1X/Z 45TdZ81e1JWbG2Iy7aKs+bEnjkCGegpk+sVJWRlYcT0pBOxjSG2M34I0dwpD4gmUuPfw pVAeHTwyX4DZJZ1zVO6sL0+eZtXf8fvN9pV0pJM0tt4j+Ym3rp5r88ZcUwzyWcFY+Ko0 uX985Ik8/9cy0D+l8WIvincSX6qr1LjuRwRKJHgQ9uzilarAZ53DEe6HaNzVORP/txU2 gV5A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n12si99222jat.1.2021.05.26.11.28.28; Wed, 26 May 2021 11:28:28 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235512AbhEZS34 (ORCPT + 7 others); Wed, 26 May 2021 14:29:56 -0400 Received: from foss.arm.com ([217.140.110.172]:48538 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232262AbhEZS34 (ORCPT ); Wed, 26 May 2021 14:29:56 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C9ED143B; Wed, 26 May 2021 11:28:24 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 054C03F73B; Wed, 26 May 2021 11:28:22 -0700 (PDT) From: Sudeep Holla To: devicetree@vger.kernel.org Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, Rob Herring , Cristian Marussi , Florian Fainelli , Jim Quinlan , Etienne Carriere , Peter Hilber Subject: [PATCH 8/8] dt-bindings: firmware: arm, scmi: Convert to json schema Date: Wed, 26 May 2021 19:28:07 +0100 Message-Id: <20210526182807.548118-9-sudeep.holla@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526182807.548118-1-sudeep.holla@arm.com> References: <20210526182807.548118-1-sudeep.holla@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the old text format binding for System Control and Management Interface (SCMI) Message Protocol into the new and shiny YAML format. Cc: Rob Herring Cc: Cristian Marussi Cc: Florian Fainelli Cc: Jim Quinlan Cc: Etienne Carriere Cc: Peter Hilber Signed-off-by: Sudeep Holla --- .../devicetree/bindings/arm/arm,scmi.txt | 224 --------------- .../bindings/firmware/arm,scmi.yaml | 270 ++++++++++++++++++ 2 files changed, 270 insertions(+), 224 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/arm,scmi.txt create mode 100644 Documentation/devicetree/bindings/firmware/arm,scmi.yaml Hi, I have converted all the bindings except the below regulator part of the binding. This needs to be addressed before merging ofcourse. Just posting the remaining changes to get feedback and also ask suggestion for the below: scmi_voltage: protocol@17 { reg = <0x17>; regulators { regulator_devX: regulator@0 { reg = <0x0>; regulator-max-microvolt = <3300000>; }; regulator_devY: regulator@9 { reg = <0x9>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <4200000>; }; }; }; I will reply with things I have tried separately to avoid confusion with this the patch here. -- 2.25.1 diff --git a/Documentation/devicetree/bindings/arm/arm,scmi.txt b/Documentation/devicetree/bindings/arm/arm,scmi.txt deleted file mode 100644 index b7be2000afcb..000000000000 --- a/Documentation/devicetree/bindings/arm/arm,scmi.txt +++ /dev/null @@ -1,224 +0,0 @@ -System Control and Management Interface (SCMI) Message Protocol ----------------------------------------------------------- - -The SCMI is intended to allow agents such as OSPM to manage various functions -that are provided by the hardware platform it is running on, including power -and performance functions. - -This binding is intended to define the interface the firmware implementing -the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control -and Management Interface Platform Design Document")[0] provide for OSPM in -the device tree. - -Required properties: - -The scmi node with the following properties shall be under the /firmware/ node. - -- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports -- mboxes: List of phandle and mailbox channel specifiers. It should contain - exactly one or two mailboxes, one for transmitting messages("tx") - and another optional for receiving the notifications("rx") if - supported. -- shmem : List of phandle pointing to the shared memory(SHM) area as per - generic mailbox client binding. -- #address-cells : should be '1' if the device has sub-nodes, maps to - protocol identifier for a given sub-node. -- #size-cells : should be '0' as 'reg' property doesn't have any size - associated with it. -- arm,smc-id : SMC id required when using smc or hvc transports - -Optional properties: - -- mbox-names: shall be "tx" or "rx" depending on mboxes entries. - -- interrupts : when using smc or hvc transports, this optional - property indicates that msg completion by the platform is indicated - by an interrupt rather than by the return of the smc call. This - should not be used except when the platform requires such behavior. - -- interrupt-names : if "interrupts" is present, interrupt-names must also - be present and have the value "a2p". - -See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details -about the generic mailbox controller and client driver bindings. - -The mailbox is the only permitted method of calling the SCMI firmware. -Mailbox doorbell is used as a mechanism to alert the presence of a -messages and/or notification. - -Each protocol supported shall have a sub-node with corresponding compatible -as described in the following sections. If the platform supports dedicated -communication channel for a particular protocol, the 3 properties namely: -mboxes, mbox-names and shmem shall be present in the sub-node corresponding -to that protocol. - -Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol ------------------------------------------------------------- - -This binding uses the common clock binding[1]. - -Required properties: -- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands. - -Power domain bindings for the power domains based on SCMI Message Protocol ------------------------------------------------------------- - -This binding for the SCMI power domain providers uses the generic power -domain binding[2]. - -Required properties: - - #power-domain-cells : Should be 1. Contains the device or the power - domain ID value used by SCMI commands. - -Regulator bindings for the SCMI Regulator based on SCMI Message Protocol ------------------------------------------------------------- -An SCMI Regulator is permanently bound to a well defined SCMI Voltage Domain, -and should be always positioned as a root regulator. -It does not support any current operation. - -SCMI Regulators are grouped under a 'regulators' node which in turn is a child -of the SCMI Voltage protocol node inside the desired SCMI instance node. - -This binding uses the common regulator binding[6]. - -Required properties: - - reg : shall identify an existent SCMI Voltage Domain. - -Sensor bindings for the sensors based on SCMI Message Protocol --------------------------------------------------------------- -SCMI provides an API to access the various sensors on the SoC. - -Required properties: -- #thermal-sensor-cells: should be set to 1. This property follows the - thermal device tree bindings[3]. - - Valid cell values are raw identifiers (Sensor ID) - as used by the firmware. Refer to platform details - for your implementation for the IDs to use. - -Reset signal bindings for the reset domains based on SCMI Message Protocol ------------------------------------------------------------- - -This binding for the SCMI reset domain providers uses the generic reset -signal binding[5]. - -Required properties: - - #reset-cells : Should be 1. Contains the reset domain ID value used - by SCMI commands. - -[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/power/power-domain.yaml -[3] Documentation/devicetree/bindings/thermal/thermal*.yaml -[4] Documentation/devicetree/bindings/sram/sram.yaml -[5] Documentation/devicetree/bindings/reset/reset.txt -[6] Documentation/devicetree/bindings/regulator/regulator.yaml - -Example: - -sram@50000000 { - compatible = "mmio-sram"; - reg = <0x0 0x50000000 0x0 0x10000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x50000000 0x10000>; - - cpu_scp_lpri: scp-shmem@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x200>; - }; - - cpu_scp_hpri: scp-shmem@200 { - compatible = "arm,scmi-shmem"; - reg = <0x200 0x200>; - }; -}; - -mailbox@40000000 { - .... - #mbox-cells = <1>; - reg = <0x0 0x40000000 0x0 0x10000>; -}; - -firmware { - - ... - - scmi { - compatible = "arm,scmi"; - mboxes = <&mailbox 0 &mailbox 1>; - mbox-names = "tx", "rx"; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_devpd: protocol@11 { - reg = <0x11>; - #power-domain-cells = <1>; - }; - - scmi_dvfs: protocol@13 { - reg = <0x13>; - #clock-cells = <1>; - }; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_sensors0: protocol@15 { - reg = <0x15>; - #thermal-sensor-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - - scmi_voltage: protocol@17 { - reg = <0x17>; - - regulators { - regulator_devX: regulator@0 { - reg = <0x0>; - regulator-max-microvolt = <3300000>; - }; - - regulator_devY: regulator@9 { - reg = <0x9>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <4200000>; - }; - - ... - }; - }; - }; -}; - -cpu@0 { - ... - reg = <0 0>; - clocks = <&scmi_dvfs 0>; -}; - -hdlcd@7ff60000 { - ... - reg = <0 0x7ff60000 0 0x1000>; - clocks = <&scmi_clk 4>; - power-domains = <&scmi_devpd 1>; - resets = <&scmi_reset 10>; -}; - -thermal-zones { - soc_thermal { - polling-delay-passive = <100>; - polling-delay = <1000>; - /* sensor ID */ - thermal-sensors = <&scmi_sensors0 3>; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml new file mode 100644 index 000000000000..36072585fc45 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -0,0 +1,270 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2021 ARM Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/arm,scmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: System Control and Management Interface (SCMI) Message Protocol bindings + +maintainers: + - Sudeep Holla + +description: | + The SCMI is intended to allow agents such as OSPM to manage various functions + that are provided by the hardware platform it is running on, including power + and performance functions. + + This binding is intended to define the interface the firmware implementing + the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control + and Management Interface Platform Design Document")[0] provide for OSPM in + the device tree. + + [0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html + +properties: + $nodename: + const: scmi + + compatible: + oneOf: + - description: SCMI compliant firmware with mailbox transport + items: + - const: arm,scmi + - description: SCMI compliant firmware with ARM SMC/HVC transport + items: + - const: arm,scmi-smc + + mbox-names: + description: | + Specifies the mailboxes used to communicate with SCMI compliant + firmware. + items: + - const: tx + - const: rx + + mboxes: + description: | + List of phandle and mailbox channel specifiers. It should contain + exactly one or two mailboxes, one for transmitting messages("tx") + and another optional for receiving the notifications("rx") if supported. + minItems: 1 + maxItems: 2 + + shmem: + description: | + List of phandle pointing to the shared memory(SHM) area, for each + transport channel specified. + minItems: 1 + maxItems: 2 + + '#address-cells': + description: | + The address cells maps to protocol identifier for a given sub-node. + const: 1 + + '#size-cells': + description: | + The size cells are not present as 'reg' property doesn't have any + size associated with it. + const: 0 + + arm,smc-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SMC id required when using smc or hvc transports + +additionalProperties: + type: object + +patternProperties: + '^protocol@[0-9a-f]+$': + type: object + description: | + Each sub-node represents a protocol supported. If the platform + supports dedicated communication channel for a particular protocol, + then corresponding transport properties must be present. + + properties: + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + '#thermal-sensor-cells': + const: 1 + +required: + - compatible + - shmem + +allOf: + - if: + properties: + compatible: + contains: + const: arm,scmi + then: + required: + - mboxes + - if: + properties: + compatible: + contains: + const: arm,scmi-smc + then: + properties: + interrupts: + description: | + The interrupt that indicates message completion by the platform + rather than by the return of the smc call. This should not be used + except when the platform requires such behavior. + + interrupt-names: + const: a2p + + required: + - arm,smc-id + +examples: + - | + firmware { + scmi { + compatible = "arm,scmi"; + mboxes = <&mhuB 0 0>, + <&mhuB 0 1>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensors: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + + scmi_voltage: protocol@17 { + reg = <0x17>; + }; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + + sram@50000000 { + compatible = "mmio-sram"; + reg = <0x0 0x50000000 0x0 0x10000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x10000>; + + cpu_scp_lpri: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_hpri: scp-sram-section@200 { + compatible = "arm,scmi-shmem"; + reg = <0x200 0x200>; + }; + }; + + mhuB: mailbox@2b2f0000 { + #mbox-cells = <2>; + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0 0x2b2f0000 0 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + gpu@ffe40000 { + compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; + reg = <0x0 0xffe40000 0x0 0x10000>; + interrupts = <0 160 4>, <0 161 4>, <0 162 4>; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&scmi_clk 1>; + power-domains = <&scmi_devpd 8>; + resets = <&scmi_reset 0>, <&scmi_reset 1>; + }; + + display@20930000 { + compatible = "intel,keembay-display"; + reg = <0x0 0x20930000 0x0 0x3000>; + reg-names = "lcd"; + interrupts = <0 33 4>; + clocks = <&scmi_clk 0x83>, + <&scmi_clk 0x0>; + clock-names = "clk_lcd", "clk_pll0"; + + port { + disp_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + + thermal-zones { + soc-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&scmi_sensors0 3>; + + trips { + mpu0_crit: mpu0_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + }; + }; + + cpus { + #size-cells = <0>; + #address-cells = <2>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + }; + }; + +...