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Thu, 27 May 2021 17:50:19 -0700 Envelope-to: mdf@kernel.org, robh@kernel.org, trix@redhat.com, devicetree@vger.kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.19.73.109] (port=34006 helo=xsj-xw9400.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lmQhf-0003WN-Gk; Thu, 27 May 2021 17:50:19 -0700 Received: by xsj-xw9400.xilinx.com (Postfix, from userid 21952) id E9A6F600217; Thu, 27 May 2021 17:50:05 -0700 (PDT) From: Lizhi Hou To: CC: Lizhi Hou , , , , , , , , , , , Max Zhen Subject: [PATCH V7 XRT Alveo 01/20] Documentation: fpga: Add a document describing XRT Alveo drivers Date: Thu, 27 May 2021 17:49:40 -0700 Message-ID: <20210528004959.61354-2-lizhi.hou@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210528004959.61354-1-lizhi.hou@xilinx.com> References: <20210528004959.61354-1-lizhi.hou@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4da8246b-dafd-4bd6-fa29-08d92172954b X-MS-TrafficTypeDiagnostic: CH0PR02MB8026: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou --- Documentation/fpga/index.rst | 1 + Documentation/fpga/xrt.rst | 870 +++++++++++++++++++++++++++++++++++ MAINTAINERS | 11 + 3 files changed, 882 insertions(+) create mode 100644 Documentation/fpga/xrt.rst diff --git a/Documentation/fpga/index.rst b/Documentation/fpga/index.rst index f80f95667ca2..30134357b70d 100644 --- a/Documentation/fpga/index.rst +++ b/Documentation/fpga/index.rst @@ -8,6 +8,7 @@ fpga :maxdepth: 1 dfl + xrt .. only:: subproject and html diff --git a/Documentation/fpga/xrt.rst b/Documentation/fpga/xrt.rst new file mode 100644 index 000000000000..5a5b4d5a3bc6 --- /dev/null +++ b/Documentation/fpga/xrt.rst @@ -0,0 +1,870 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================================== +XRTV2 Linux Kernel Driver Overview +================================== + +Authors: + +* Sonal Santan +* Max Zhen +* Lizhi Hou + +XRTV2 drivers are second generation `XRT `_ +drivers which support `Alveo `_ +PCIe platforms from Xilinx. + +XRTV2 drivers support *subsystem* style data driven platforms where driver's +configuration and behavior are determined by metadata provided by the platform +(in *device tree* format). Primary management physical function (MPF) driver +is called **xrt-mgmt**. Primary user physical function (UPF) driver is called +**xrt-user** and is under development. xrt_driver framework and HW subsystem +drivers are packaged into a library module called **xrt-lib**, which is shared +by **xrt-mgmt** and **xrt-user** (under development). The xrt_driver framework +implements a ``bus_type`` called **xrt_bus_type** which is used to discover HW +subsystems and facilitate inter HW subsystem interaction. + +Driver Modules +============== + +xrt-lib.ko +---------- + +xrt-lib is the repository of all subsystem drivers and pure software modules that +can potentially be shared between xrt-mgmt and xrt-user. All these drivers are +structured as **xrt_driver** and are instantiated by xrt-mgmt (or xrt-user under +development) based on the metadata associated with the hardware. The metadata is +in the form of a device tree as mentioned before. Each xrt_driver statically +defines a subsystem node array by using a node name or a string in its ``.endpoints`` +property. And this array is eventually translated to IOMEM resources in the +instantiated **xrt_device**. + +The xrt-lib infrastructure provides hooks to xrt_drivers for device node +management, user file operations and ioctl callbacks. The core infrastructure also +provides a bus functionality called **xrt_bus_type** for xrt_driver registration, +discovery and inter xrt_driver calls. xrt-lib does not have any dependency on PCIe +subsystem. + +.. note:: + See code in ``include/xleaf.h`` and ``include/xdevice.h`` + + +xrt-mgmt.ko +------------ + +The xrt-mgmt driver is a PCIe device driver driving MPF found on Xilinx's Alveo +PCIe device. It consists of one *root* driver, one or more *group* drivers +and one or more *xleaf* drivers. The group and xleaf drivers are instantiations +of the xrt_driver but are called group and xleaf to symbolize the logical operation +performed by them. + +The root driver manages the life cycle of multiple group drivers, which, in turn, +manages multiple xleaf drivers. This flexibility allows xrt-mgmt.ko and xrt-lib.ko +to support various HW subsystems exposed by different Alveo shells. The differences +among these Alveo shells is handled in xleaf drivers. The root and group +drivers are part of the infrastructure which provide common services to xleaf +drivers found on various Alveo shells. See :ref:`alveo_platform_overview`. + +The instantiation of specific group driver or xleaf drivers is completely data +driven based on metadata (mostly in device tree format) found through VSEC +capability and inside the firmware files, such as platform xsabin or user xclbin +file. + + +Driver Object Model +=================== + +The driver object model looks like the following:: + + +-----------+ + | xroot | + +-----+-----+ + | + +-----------+-----------+ + | | + v v + +-----------+ +-----------+ + | group | ... | group | + +-----+-----+ +------+----+ + | | + | | + +-----+----+ +-----+----+ + | | | | + v v v v + +-------+ +-------+ +-------+ +-------+ + | xleaf |..| xleaf | | xleaf |..| xleaf | + +-------+ +-------+ +-------+ +-------+ + +As an example, for Xilinx Alveo U50 before user xclbin download, the tree +looks like the following:: + + +-----------+ + | xrt-mgmt | + +-----+-----+ + | + +-------------------------+--------------------+ + | | | + v v v + +--------+ +--------+ +--------+ + | group0 | | group1 | | group2 | + +----+---+ +----+---+ +---+----+ + | | | + | | | + +-----+-----+ +----+-----+---+ +-----+-----+----+--------+ + | | | | | | | | | + v v | v v | v v | + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | + | xmgmt_main | | VSEC | | | GPIO | | QSPI | | | CMC | | AXI-GATE0 | | + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | + | +---------+ | +------+ +-----------+ | + +>| MAILBOX | +->| ICAP | | AXI-GATE1 |<+ + +---------+ | +------+ +-----------+ + | +-------+ + +->| CALIB | + +-------+ + +After a xclbin is downloaded, group3 will be added and the tree looks like the +following:: + + +-----------+ + | xrt-mgmt | + +-----+-----+ + | + +-------------------------+--------------------+-----------------+ + | | | | + v v v | + +--------+ +--------+ +--------+ | + | group0 | | group1 | | group2 | | + +----+---+ +----+---+ +---+----+ | + | | | | + | | | | + +-----+-----+ +-----+-----+---+ +-----+-----+----+--------+ | + | | | | | | | | | | + v v | v v | v v | | + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | | + | xmgmt_main | | VSEC | | | GPIO | | QSPI | | | CMC | | AXI-GATE0 | | | + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | | + | +---------+ | +------+ +-----------+ | | + +>| MAILBOX | +->| ICAP | | AXI-GATE1 |<+ | + +---------+ | +------+ +-----------+ | + | +-------+ | + +->| CALIB | | + +-------+ | + +---+----+ | + | group3 |<--------------------------------------------+ + +--------+ + | + | + +-------+--------+---+--+--------+------+-------+ + | | | | | | | + v | v | v | v + +--------+ | +--------+ | +--------+ | +-----+ + | CLOCK0 | | | CLOCK1 | | | CLOCK2 | | | UCS | + +--------+ v +--------+ v +--------+ v +-----+ + +-------------+ +-------------+ +-------------+ + | CLOCK-FREQ0 | | CLOCK-FREQ1 | | CLOCK-FREQ2 | + +-------------+ +-------------+ +-------------+ + + +root +---- + +The root driver is a PCIe device driver attached to MPF. It's part of the +infrastructure of the MPF driver and resides in xrt-mgmt.ko. This driver + +* manages one or more group drivers +* provides access to functionalities that requires pci_dev, such as PCIE config + space access, to other xleaf drivers through root calls +* facilities inter xleaf driver calls for other xleaf drivers +* facilities event callbacks for other xleaf drivers + +When the root driver starts, it will explicitly create an initial group instance, +which contains xleaf drivers that will trigger the creation of other group +instances. The root driver will wait for all group and xleaf drivers to be +created before it returns from its probe routine and claim success of the +initialization of the entire xrt-mgmt driver. If any xleaf fails to initialize +the xrt-mgmt driver will still come online but with limited functionality. + +.. note:: + See code in ``lib/xroot.c`` and ``mgmt/root.c`` + + +group +----- + +The group driver represents a pseudo device whose life cycle is managed by +root and does not have real IO mem or IRQ resources. It's part of the +infrastructure of the MPF driver and resides in xrt-lib.ko. This driver + +* manages one or more xleaf drivers +* provides access to root from xleaf drivers, so that root calls, event + notifications and inter xleaf calls can happen + +In xrt-mgmt, an initial group driver instance will be created by the root. This +instance contains xleaf drivers that will trigger group instances to be created +to manage groups of xleaf drivers found on different partitions of hardware, +such as VSEC, Shell, and User. + +Every *fpga_region* has a group driver associated with it. The group driver is +created when a xclbin image is loaded on the fpga_region. The existing group +is destroyed when a new xclbin image is loaded. The fpga_region persists +across xclbin downloads. + +.. note:: + See code in ``lib/group.c`` + + +xleaf +----- + +The xleaf driver is a xrt_driver whose life cycle is managed by +a group driver and may or may not have real IO mem or IRQ resources. They +manage HW subsystems they are attached to. + +A xleaf driver without real hardware resources manages in-memory states for +xrt-mgmt. These states are shareable by other xleaf drivers. + +Xleaf drivers assigned to specific hardware resources drive a specific subsystem +in the device. To manipulate the subsystem or carry out a task, a xleaf driver +may ask for help from the root via root calls and/or from other leaves via +inter xleaf calls. + +A xleaf can also broadcast events through infrastructure code for other leaves +to process. It can also receive event notification from infrastructure about +certain events, such as post-creation or pre-exit of a particular xleaf. + +.. note:: + See code in ``lib/xleaf/*.c`` + + +xrt_bus_type +------------ + +xrt_bus_type defines a virtual bus which handles xrt_driver probe, remove and match +operations. All xrt_drivers register with xrt_bus_type as part of xrt-lib driver +``module_init`` and un-register as part of xrt-lib driver ``module_exit``. + +.. note:: + See code in ``lib/lib-drv.c`` + +FPGA Manager Interaction +======================== + +fpga_manager +------------ + +An instance of fpga_manager is created by xmgmt_main and is used for xclbin +image download. fpga_manager requires the full xclbin image before it can +start programming the FPGA configuration engine via Internal Configuration +Access Port (ICAP) xrt_driver. + +fpga_region +----------- + +For every interface exposed by the currently loaded xclbin/xsabin in the +*parent* fpga_region a new instance of fpga_region is created like a *child* +fpga_region. The device tree of the *parent* fpga_region defines the +resources for a new instance of fpga_bridge which isolates the parent from +child fpga_region. This new instance of fpga_bridge will be used when a +xclbin image is loaded on the child fpga_region. After the xclbin image is +downloaded to the fpga_region, an instance of a group is created for the +fpga_region using the device tree obtained as part of the xclbin. If this +device tree defines any child interfaces, it can trigger the creation of +fpga_bridge and fpga_region for the next region in the chain. + +fpga_bridge +----------- + +Like the fpga_region, a fpga_bridge is created by walking the device tree +of the parent group. The bridge is used for isolation between a parent and +its child. + +Driver Interfaces +================= + +xrt-mgmt Driver Ioctls +---------------------- + +Ioctls exposed by the xrt-mgmt driver to user space are enumerated in the +following table: + +== ===================== ============================ ========================== +# Functionality ioctl request code data format +== ===================== ============================ ========================== +1 FPGA image download XMGMT_IOCICAPDOWNLOAD_AXLF xmgmt_ioc_bitstream_axlf +== ===================== ============================ ========================== + +A user xclbin can be downloaded by using the xbmgmt tool from the XRT open source +suite. See example usage below:: + + xbmgmt partition --program --path /lib/firmware/xilinx/862c7020a250293e32036f19956669e5/test/verify.xclbin --force + +xrt-mgmt Driver Sysfs +---------------------- + +The xrt-mgmt driver exposes a rich set of sysfs interfaces. Subsystem xrt +drivers export sysfs node for every platform instance. + +Every partition also exports its UUIDs. See below for examples:: + + /sys/bus/pci/devices/0000:06:00.0/xmgmt_main.0/interface_uuids + /sys/bus/pci/devices/0000:06:00.0/xmgmt_main.0/logic_uuids + + +hwmon +----- + +The xrt-mgmt driver exposes standard hwmon interface to report voltage, current, +temperature, power, etc. These can easily be viewed using *sensors* command line +utility. + +.. _alveo_platform_overview: + +Alveo Platform Overview +======================= + +Alveo platforms are architected as two physical FPGA partitions: *Shell* and +*User*. The Shell provides basic infrastructure for the Alveo platform like +PCIe connectivity, board management, Dynamic Function Exchange (DFX), sensors, +clocking, reset, and security. DFX, partial reconfiguration, is responsible for +loading the user compiled FPGA binary. + +For DFX to work properly, physical partitions require strict HW compatibility +with each other. Every physical partition has two interface UUIDs: the *parent* +UUID and the *child* UUID. For simple single stage platforms, Shell → User forms +the parent child relationship. + +.. note:: + Partition compatibility matching is a key design component of the Alveo platforms + and XRT. Partitions have child and parent relationship. A loaded partition + exposes child partition UUID to advertise its compatibility requirement. When + loading a child partition, the xrt-mgmt driver matches the parent + UUID of the child partition against the child UUID exported by the parent. + The parent and child partition UUIDs are stored in the *xclbin* (for the user) + and the *xsabin* (for the shell). Except for the root UUID exported by VSEC, + the hardware itself does not know about the UUIDs. The UUIDs are stored in + xsabin and xclbin. The image format has a special node called Partition UUIDs + which define the compatibility UUIDs. See :ref:`partition_uuids`. + + +The physical partitions and their loading are illustrated below:: + + SHELL USER + +-----------+ +-------------------+ + | | | | + | VSEC UUID | CHILD PARENT | LOGIC UUID | + | o------->|<--------o | + | | UUID UUID | | + +-----+-----+ +--------+----------+ + | | + . . + | | + +---+---+ +------+--------+ + | POR | | USER COMPILED | + | FLASH | | XCLBIN | + +-------+ +---------------+ + + +Loading Sequence +---------------- + +The Shell partition is loaded from flash at system boot time. It establishes the +PCIe link and exposes two physical functions to the BIOS. After the OS boots, +the xrt-mgmt driver attaches to the PCIe physical function 0 exposed by the Shell +and then looks for VSEC in the PCIe extended configuration space. Using VSEC, it +determines the logic UUID of the Shell and uses the UUID to load matching *xsabin* +file from Linux firmware directory. The xsabin file contains the metadata to +discover the peripherals that are part of the Shell and the firmware for any +embedded soft processors in the Shell. The xsabin file also contains Partition +UUIDs as described here :ref:`partition_uuids`. + +The Shell exports a child interface UUID which is used for the compatibility +check when loading the user compiled xclbin over the User partition as part of DFX. +When a user requests loading of a specific xclbin, the xrt-mgmt driver reads +the parent interface UUID specified in the xclbin and matches it with the child +interface UUID exported by the Shell to determine if the xclbin is compatible with +the Shell. If the match fails, loading of xclbin is denied. + +xclbin loading is requested using the ICAP_DOWNLOAD_AXLF ioctl command. When loading +a xclbin, the xrt-mgmt driver performs the following *logical* operations: + +1. Copy xclbin from user to kernel memory +2. Sanity check the xclbin contents +3. Isolate the User partition +4. Download the bitstream using the FPGA config engine (ICAP) +5. De-isolate the User partition +6. Program the clocks (ClockWiz) driving the User partition +7. Wait for the memory controller (MIG) calibration +8. Return the loading status back to the caller + +`Platform Loading Overview `_ +provides more detailed information on platform loading. + + +xsabin +------ + +Each Alveo platform comes packaged with its own xsabin. The xsabin is a trusted +component of the platform. For format details refer to :ref:`xsabin_xclbin_container_format` +below. xsabin contains basic information like UUIDs, platform name and metadata in the +form of device tree. See :ref:`device_tree_usage` below for details and example. + +xclbin +------ + +xclbin is compiled by end user using +`Vitis `_ +tool set from Xilinx. The xclbin contains sections describing user compiled +acceleration engines/kernels, memory subsystems, clocking information etc. It also +contains a FPGA bitstream for the user partition, UUIDs, platform name, etc. + + +.. _xsabin_xclbin_container_format: + +xsabin/xclbin Container Format +------------------------------ + +xclbin/xsabin is ELF-like binary container format. It is structured as series of +sections. There is a file header followed by several section headers which is +followed by sections. A section header points to an actual section. There is an +optional signature at the end. The format is defined by the header file ``xclbin.h``. +The following figure illustrates a typical xclbin:: + + + +---------------------+ + | | + | HEADER | + +---------------------+ + | SECTION HEADER | + | | + +---------------------+ + | ... | + | | + +---------------------+ + | SECTION HEADER | + | | + +---------------------+ + | SECTION | + | | + +---------------------+ + | ... | + | | + +---------------------+ + | SECTION | + | | + +---------------------+ + | SIGNATURE | + | (OPTIONAL) | + +---------------------+ + + +xclbin/xsabin files can be packaged, un-packaged and inspected using an XRT +utility called **xclbinutil**. xclbinutil is part of the XRT open source +software stack. The source code for xclbinutil can be found at +https://github.com/Xilinx/XRT/tree/master/src/runtime_src/tools/xclbinutil + +For example, to enumerate the contents of a xclbin/xsabin use the *--info* switch +as shown below:: + + + xclbinutil --info --input /opt/xilinx/firmware/u50/gen3x16-xdma/blp/test/bandwidth.xclbin + xclbinutil --info --input /lib/firmware/xilinx/862c7020a250293e32036f19956669e5/partition.xsabin + + +.. _device_tree_usage: + +Device Tree Usage +----------------- + +The xsabin file stores metadata which advertise HW subsystems present in a +partition. The metadata is stored in device tree format with a well defined +schema. XRT management driver uses this information to bind *xrt_drivers* to +the subsystem instantiations. The xrt_drivers are found in **xrt-lib.ko** kernel +module. + +Logic UUID +^^^^^^^^^^ +A partition is identified uniquely through ``logic_uuid`` property:: + + /dts-v1/; + / { + logic_uuid = "0123456789abcdef0123456789abcdef"; + ... + } + +Schema Version +^^^^^^^^^^^^^^ +Schema version is defined through the ``schema_version`` node. It contains +``major`` and ``minor`` properties as below:: + + /dts-v1/; + / { + schema_version { + major = <0x01>; + minor = <0x00>; + }; + ... + } + +.. _partition_uuids: + +Partition UUIDs +^^^^^^^^^^^^^^^ +Each partition may have parent and child UUIDs. These UUIDs are +defined by ``interfaces`` node and ``interface_uuid`` property:: + + /dts-v1/; + / { + interfaces { + @0 { + interface_uuid = "0123456789abcdef0123456789abcdef"; + }; + @1 { + interface_uuid = "fedcba9876543210fedcba9876543210"; + }; + ... + }; + ... + } + + +Subsystem Instantiations +^^^^^^^^^^^^^^^^^^^^^^^^ +Subsystem instantiations are captured as children of ``addressable_endpoints`` +node:: + + /dts-v1/; + / { + addressable_endpoints { + abc { + ... + }; + def { + ... + }; + ... + } + } + +Subnode 'abc' and 'def' are the name of subsystem nodes + +Subsystem Node +^^^^^^^^^^^^^^ +Each subsystem node and its properties define a hardware instance:: + + + addressable_endpoints { + abc { + reg = <0x00 0x1f05000 0x00 0x1000>> + pcie_physical_function = <0x0>; + pcie_bar_mapping = <0x2>; + compatible = "abc def"; + interrupts = <0x09 0x0c>; + firmware { + firmware_product_name = "abc" + firmware_branch_name = "def" + firmware_version_major = <1> + firmware_version_minor = <2> + }; + } + ... + } + +:reg: + Property defines an address range. `<0x00 0x1f05000 0x00 0x1000>` indicates + *0x00 0x1f05000* as BAR offset and *0x00 0x1000* as address length. +:pcie_physical_function: + Property specifies which PCIe physical function the subsystem node resides. + `<0x0>` implies physical function 0. +:pcie_bar_mapping: + Property specifies which PCIe BAR the subsystem node resides. `<0x2>` implies + BAR 2. A value of 0 means the property is not defined. +:compatible: + Property is a list of strings. The first string in the list specifies the exact + subsystem node. The following strings represent other devices that the device + is compatible with. +:interrupts: + Property specifies start and end interrupts for this subsystem node. + `<0x09 0x0c>` implies interrupts 9 to 13 are used by this subsystem. +:firmware: + Subnode defines the firmware required by this subsystem node. + +Alveo U50 Platform Example +^^^^^^^^^^^^^^^^^^^^^^^^^^ +:: + + /dts-v1/; + + /{ + logic_uuid = "f465b0a3ae8c64f619bc150384ace69b"; + + schema_version { + major = <0x01>; + minor = <0x00>; + }; + + interfaces { + + @0 { + interface_uuid = "862c7020a250293e32036f19956669e5"; + }; + }; + + addressable_endpoints { + + ep_blp_rom_00 { + reg = <0x00 0x1f04000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; + }; + + ep_card_flash_program_00 { + reg = <0x00 0x1f06000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_quad_spi-1.0\0axi_quad_spi"; + interrupts = <0x03 0x03>; + }; + + ep_cmc_firmware_mem_00 { + reg = <0x00 0x1e20000 0x00 0x20000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; + + firmware { + firmware_product_name = "cmc"; + firmware_branch_name = "u50"; + firmware_version_major = <0x01>; + firmware_version_minor = <0x00>; + }; + }; + + ep_cmc_intc_00 { + reg = <0x00 0x1e03000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_intc-1.0\0axi_intc"; + interrupts = <0x04 0x04>; + }; + + ep_cmc_mutex_00 { + reg = <0x00 0x1e02000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; + }; + + ep_cmc_regmap_00 { + reg = <0x00 0x1e08000 0x00 0x2000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; + + firmware { + firmware_product_name = "sc-fw"; + firmware_branch_name = "u50"; + firmware_version_major = <0x05>; + }; + }; + + ep_cmc_reset_00 { + reg = <0x00 0x1e01000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; + }; + + ep_ddr_mem_calib_00 { + reg = <0x00 0x63000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; + }; + + ep_debug_bscan_mgmt_00 { + reg = <0x00 0x1e90000 0x00 0x10000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-debug_bridge-1.0\0debug_bridge"; + }; + + ep_ert_base_address_00 { + reg = <0x00 0x21000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; + }; + + ep_ert_command_queue_mgmt_00 { + reg = <0x00 0x40000 0x00 0x10000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-ert_command_queue-1.0\0ert_command_queue"; + }; + + ep_ert_command_queue_user_00 { + reg = <0x00 0x40000 0x00 0x10000>; + pcie_physical_function = <0x01>; + compatible = "xilinx.com,reg_abs-ert_command_queue-1.0\0ert_command_queue"; + }; + + ep_ert_firmware_mem_00 { + reg = <0x00 0x30000 0x00 0x8000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; + + firmware { + firmware_product_name = "ert"; + firmware_branch_name = "v20"; + firmware_version_major = <0x01>; + }; + }; + + ep_ert_intc_00 { + reg = <0x00 0x23000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_intc-1.0\0axi_intc"; + interrupts = <0x05 0x05>; + }; + + ep_ert_reset_00 { + reg = <0x00 0x22000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; + }; + + ep_ert_sched_00 { + reg = <0x00 0x50000 0x00 0x1000>; + pcie_physical_function = <0x01>; + compatible = "xilinx.com,reg_abs-ert_sched-1.0\0ert_sched"; + interrupts = <0x09 0x0c>; + }; + + ep_fpga_configuration_00 { + reg = <0x00 0x1e88000 0x00 0x8000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_hwicap-1.0\0axi_hwicap"; + interrupts = <0x02 0x02>; + }; + + ep_icap_reset_00 { + reg = <0x00 0x1f07000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; + }; + + ep_msix_00 { + reg = <0x00 0x00 0x00 0x20000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-msix-1.0\0msix"; + pcie_bar_mapping = <0x02>; + }; + + ep_pcie_link_mon_00 { + reg = <0x00 0x1f05000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; + }; + + ep_pr_isolate_plp_00 { + reg = <0x00 0x1f01000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; + }; + + ep_pr_isolate_ulp_00 { + reg = <0x00 0x1000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; + }; + + ep_uuid_rom_00 { + reg = <0x00 0x64000 0x00 0x1000>; + pcie_physical_function = <0x00>; + compatible = "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; + }; + + ep_xdma_00 { + reg = <0x00 0x00 0x00 0x10000>; + pcie_physical_function = <0x01>; + compatible = "xilinx.com,reg_abs-xdma-1.0\0xdma"; + pcie_bar_mapping = <0x02>; + }; + }; + + } + + + +Deployment Models +================= + +Baremetal +--------- + +In bare-metal deployments, both MPF and UPF are visible and accessible. The +xrt-mgmt driver binds to MPF. The xrt-mgmt driver operations are privileged and +available to system administrator. The full stack is illustrated below:: + + HOST + + [XRT-MGMT] [XRT-USER] + | | + | | + +-----+ +-----+ + | MPF | | UPF | + | | | | + | PF0 | | PF1 | + +--+--+ +--+--+ + ......... ^................. ^.......... + | | + | PCIe DEVICE | + | | + +--+------------------+--+ + | SHELL | + | | + +------------------------+ + | USER | + | | + | | + | | + | | + +------------------------+ + + + +Virtualized +----------- + +In virtualized deployments, the privileged MPF is assigned to the host but the +unprivileged UPF is assigned to a guest VM via PCIe pass-through. The xrt-mgmt +driver in host binds to MPF. The xrt-mgmt driver operations are privileged and +only accessible to the MPF. The full stack is illustrated below:: + + + .............. + HOST . VM . + . . + [XRT-MGMT] . [XRT-USER] . + | . | . + | . | . + +-----+ . +-----+ . + | MPF | . | UPF | . + | | . | | . + | PF0 | . | PF1 | . + +--+--+ . +--+--+ . + ......... ^................. ^.......... + | | + | PCIe DEVICE | + | | + +--+------------------+--+ + | SHELL | + | | + +------------------------+ + | USER | + | | + | | + | | + | | + +------------------------+ + + + + + +Platform Security Considerations +================================ + +`Security of Alveo Platform `_ +discusses the deployment options and security implications in great detail. diff --git a/MAINTAINERS b/MAINTAINERS index 008fcad7ac00..dd90b91c574b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7136,6 +7136,17 @@ F: Documentation/fpga/ F: drivers/fpga/ F: include/linux/fpga/ +FPGA XRT DRIVERS +M: Lizhi Hou +R: Max Zhen +R: Sonal Santan +L: linux-fpga@vger.kernel.org +S: Supported +W: https://github.com/Xilinx/XRT +F: Documentation/fpga/xrt.rst +F: drivers/fpga/xrt/ +F: include/uapi/linux/xrt/ + FPU EMULATOR M: Bill Metzenthen S: Maintained From patchwork Fri May 28 00:49:43 2021 Content-Type: text/plain; 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Thu, 27 May 2021 17:50:55 -0700 Envelope-to: mdf@kernel.org, robh@kernel.org, trix@redhat.com, devicetree@vger.kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.19.73.109] (port=34012 helo=xsj-xw9400.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lmQiF-0007BL-LJ; Thu, 27 May 2021 17:50:55 -0700 Received: by xsj-xw9400.xilinx.com (Postfix, from userid 21952) id 2E2F6600347; Thu, 27 May 2021 17:50:06 -0700 (PDT) From: Lizhi Hou To: CC: Lizhi Hou , , , , , , , , , , , Max Zhen Subject: [PATCH V7 XRT Alveo 04/20] fpga: xrt: xrt-lib driver manager Date: Thu, 27 May 2021 17:49:43 -0700 Message-ID: <20210528004959.61354-5-lizhi.hou@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210528004959.61354-1-lizhi.hou@xilinx.com> References: <20210528004959.61354-1-lizhi.hou@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 28883780-19c5-41d7-7e3e-08d92172b7f6 X-MS-TrafficTypeDiagnostic: BL3PR02MB7987: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:215; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 00:51:24.4449 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28883780-19c5-41d7-7e3e-08d92172b7f6 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT055.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR02MB7987 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org xrt-lib kernel module infrastructure code to register and manage all leaf driver modules. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou --- drivers/fpga/xrt/include/subdev_id.h | 39 ++++ drivers/fpga/xrt/include/xdevice.h | 131 +++++++++++ drivers/fpga/xrt/include/xleaf.h | 205 +++++++++++++++++ drivers/fpga/xrt/lib/lib-drv.c | 328 +++++++++++++++++++++++++++ drivers/fpga/xrt/lib/lib-drv.h | 21 ++ 5 files changed, 724 insertions(+) create mode 100644 drivers/fpga/xrt/include/subdev_id.h create mode 100644 drivers/fpga/xrt/include/xdevice.h create mode 100644 drivers/fpga/xrt/include/xleaf.h create mode 100644 drivers/fpga/xrt/lib/lib-drv.c create mode 100644 drivers/fpga/xrt/lib/lib-drv.h diff --git a/drivers/fpga/xrt/include/subdev_id.h b/drivers/fpga/xrt/include/subdev_id.h new file mode 100644 index 000000000000..02df4b939a1b --- /dev/null +++ b/drivers/fpga/xrt/include/subdev_id.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + */ + +#ifndef _XRT_SUBDEV_ID_H_ +#define _XRT_SUBDEV_ID_H_ + +/* + * Every subdev driver has an ID for others to refer to it. There can be multiple number of + * instances of a subdev driver. A tuple is a unique identification + * of a specific instance of a subdev driver. + */ +enum xrt_subdev_id { + XRT_SUBDEV_INVALID = 0, + XRT_SUBDEV_GRP, + XRT_SUBDEV_VSEC, + XRT_SUBDEV_VSEC_GOLDEN, + XRT_SUBDEV_DEVCTL, + XRT_SUBDEV_AXIGATE, + XRT_SUBDEV_ICAP, + XRT_SUBDEV_TEST, + XRT_SUBDEV_MGMT_MAIN, + XRT_SUBDEV_QSPI, + XRT_SUBDEV_MAILBOX, + XRT_SUBDEV_CMC, + XRT_SUBDEV_CALIB, + XRT_SUBDEV_CLKFREQ, + XRT_SUBDEV_CLOCK, + XRT_SUBDEV_SRSR, + XRT_SUBDEV_UCS, + XRT_SUBDEV_NUM, /* Total number of subdevs. */ + XRT_ROOT = -1, /* Special ID for root driver. */ +}; + +#endif /* _XRT_SUBDEV_ID_H_ */ diff --git a/drivers/fpga/xrt/include/xdevice.h b/drivers/fpga/xrt/include/xdevice.h new file mode 100644 index 000000000000..3afd96989fc5 --- /dev/null +++ b/drivers/fpga/xrt/include/xdevice.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#ifndef _XRT_DEVICE_H_ +#define _XRT_DEVICE_H_ + +#include +#include + +#define XRT_MAX_DEVICE_NODES 128 +#define XRT_INVALID_DEVICE_INST (XRT_MAX_DEVICE_NODES + 1) + +enum { + XRT_DEVICE_STATE_NONE = 0, + XRT_DEVICE_STATE_ADDED +}; + +/* + * struct xrt_device - represent an xrt device on xrt bus + * + * dev: generic device interface. + * id: id of the xrt device. + */ +struct xrt_device { + struct device dev; + u32 subdev_id; + const char *name; + u32 instance; + u32 state; + u32 num_resources; + struct resource *resource; + void *sdev_data; +}; + +/* + * If populated by xrt device driver, infra will handle the mechanics of + * char device (un)registration. + */ +enum xrt_dev_file_mode { + /* Infra create cdev, default file name */ + XRT_DEV_FILE_DEFAULT = 0, + /* Infra create cdev, need to encode inst num in file name */ + XRT_DEV_FILE_MULTI_INST, + /* No auto creation of cdev by infra, leaf handles it by itself */ + XRT_DEV_FILE_NO_AUTO, +}; + +struct xrt_dev_file_ops { + const struct file_operations xsf_ops; + dev_t xsf_dev_t; + const char *xsf_dev_name; + enum xrt_dev_file_mode xsf_mode; +}; + +/* + * this struct define the endpoints belong to the same xrt device + */ +struct xrt_dev_ep_names { + const char *ep_name; + const char *compat; +}; + +struct xrt_dev_endpoints { + struct xrt_dev_ep_names *xse_names; + /* minimum number of endpoints to support the subdevice */ + u32 xse_min_ep; +}; + +/* + * struct xrt_driver - represent a xrt device driver + * + * drv: driver model structure. + * id_table: pointer to table of device IDs the driver is interested in. + * { } member terminated. + * probe: mandatory callback for device binding. + * remove: callback for device unbinding. + */ +struct xrt_driver { + struct device_driver driver; + u32 subdev_id; + struct xrt_dev_file_ops file_ops; + struct xrt_dev_endpoints *endpoints; + + /* + * Subdev driver callbacks populated by subdev driver. + */ + int (*probe)(struct xrt_device *xrt_dev); + void (*remove)(struct xrt_device *xrt_dev); + /* + * If leaf_call is defined, these are called by other leaf drivers. + * Note that root driver may call into leaf_call of a group driver. + */ + int (*leaf_call)(struct xrt_device *xrt_dev, u32 cmd, void *arg); +}; + +#define to_xrt_dev(d) container_of(d, struct xrt_device, dev) +#define to_xrt_drv(d) container_of(d, struct xrt_driver, driver) + +static inline void *xrt_get_drvdata(const struct xrt_device *xdev) +{ + return dev_get_drvdata(&xdev->dev); +} + +static inline void xrt_set_drvdata(struct xrt_device *xdev, void *data) +{ + dev_set_drvdata(&xdev->dev, data); +} + +static inline void *xrt_get_xdev_data(struct device *dev) +{ + struct xrt_device *xdev = to_xrt_dev(dev); + + return xdev->sdev_data; +} + +struct xrt_device * +xrt_device_register(struct device *parent, u32 id, + struct resource *res, u32 res_num, + void *pdata, size_t data_sz); +void xrt_device_unregister(struct xrt_device *xdev); +int xrt_register_driver(struct xrt_driver *drv); +void xrt_unregister_driver(struct xrt_driver *drv); +void *xrt_get_xdev_data(struct device *dev); +struct resource *xrt_get_resource(struct xrt_device *xdev, u32 type, u32 num); + +#endif /* _XRT_DEVICE_H_ */ diff --git a/drivers/fpga/xrt/include/xleaf.h b/drivers/fpga/xrt/include/xleaf.h new file mode 100644 index 000000000000..f065fc766e0f --- /dev/null +++ b/drivers/fpga/xrt/include/xleaf.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + * Sonal Santan + */ + +#ifndef _XRT_XLEAF_H_ +#define _XRT_XLEAF_H_ + +#include +#include "xdevice.h" +#include "subdev_id.h" +#include "xroot.h" +#include "events.h" + +/* All subdev drivers should use below common routines to print out msg. */ +#define DEV(xdev) (&(xdev)->dev) +#define DEV_PDATA(xdev) \ + ((struct xrt_subdev_platdata *)xrt_get_xdev_data(DEV(xdev))) +#define DEV_FILE_OPS(xdev) \ + (&(to_xrt_drv((xdev)->dev.driver))->file_ops) +#define FMT_PRT(prt_fn, xdev, fmt, args...) \ + ({typeof(xdev) (_xdev) = (xdev); \ + prt_fn(DEV(_xdev), "%s %s: " fmt, \ + DEV_PDATA(_xdev)->xsp_root_name, __func__, ##args); }) +#define xrt_err(xdev, fmt, args...) FMT_PRT(dev_err, xdev, fmt, ##args) +#define xrt_warn(xdev, fmt, args...) FMT_PRT(dev_warn, xdev, fmt, ##args) +#define xrt_info(xdev, fmt, args...) FMT_PRT(dev_info, xdev, fmt, ##args) +#define xrt_dbg(xdev, fmt, args...) FMT_PRT(dev_dbg, xdev, fmt, ##args) + +#define XRT_DEFINE_REGMAP_CONFIG(config_name) \ + static const struct regmap_config config_name = { \ + .reg_bits = 32, \ + .val_bits = 32, \ + .reg_stride = 4, \ + .max_register = 0x1000, \ + } + +enum { + /* Starting cmd for common leaf cmd implemented by all leaves. */ + XRT_XLEAF_COMMON_BASE = 0, + /* Starting cmd for leaves' specific leaf cmds. */ + XRT_XLEAF_CUSTOM_BASE = 64, +}; + +enum xrt_xleaf_common_leaf_cmd { + XRT_XLEAF_EVENT = XRT_XLEAF_COMMON_BASE, +}; + +/* + * Partially initialized by the parent driver, then, passed in as subdev driver's + * platform data when creating subdev driver instance by calling platform + * device register API (xrt_device_register_data() or the likes). + * + * Once device register API returns, platform driver framework makes a copy of + * this buffer and maintains its life cycle. The content of the buffer is + * completely owned by subdev driver. + * + * Thus, parent driver should be very careful when it touches this buffer + * again once it's handed over to subdev driver. And the data structure + * should not contain pointers pointing to buffers that is managed by + * other or parent drivers since it could have been freed before platform + * data buffer is freed by platform driver framework. + */ +struct xrt_subdev_platdata { + /* + * Per driver instance callback. The xdev points to the instance. + * Should always be defined for subdev driver to get service from root. + */ + xrt_subdev_root_cb_t xsp_root_cb; + void *xsp_root_cb_arg; + + /* Something to associate w/ root for msg printing. */ + const char *xsp_root_name; + + /* + * Char dev support for this subdev instance. + * Initialized by subdev driver. + */ + struct cdev xsp_cdev; + struct device *xsp_sysdev; + struct mutex xsp_devnode_lock; /* devnode lock */ + struct completion xsp_devnode_comp; + int xsp_devnode_ref; + bool xsp_devnode_online; + bool xsp_devnode_excl; + + /* + * Subdev driver specific init data. The buffer should be embedded + * in this data structure buffer after dtb, so that it can be freed + * together with platform data. + */ + loff_t xsp_priv_off; /* Offset into this platform data buffer. */ + size_t xsp_priv_len; + + /* + * Populated by parent driver to describe the device tree for + * the subdev driver to handle. Should always be last one since it's + * of variable length. + */ + bool xsp_dtb_valid; + char xsp_dtb[0]; +}; + +struct subdev_match_arg { + enum xrt_subdev_id id; + int instance; +}; + +bool xleaf_has_endpoint(struct xrt_device *xdev, const char *endpoint_name); +struct xrt_device *xleaf_get_leaf(struct xrt_device *xdev, + xrt_subdev_match_t cb, void *arg); + +static inline bool subdev_match(enum xrt_subdev_id id, struct xrt_device *xdev, void *arg) +{ + const struct subdev_match_arg *a = (struct subdev_match_arg *)arg; + int instance = a->instance; + + if (id != a->id) + return false; + if (instance != xdev->instance && instance != XRT_INVALID_DEVICE_INST) + return false; + return true; +} + +static inline bool xrt_subdev_match_epname(enum xrt_subdev_id id, + struct xrt_device *xdev, void *arg) +{ + return xleaf_has_endpoint(xdev, arg); +} + +static inline struct xrt_device * +xleaf_get_leaf_by_id(struct xrt_device *xdev, + enum xrt_subdev_id id, int instance) +{ + struct subdev_match_arg arg = { id, instance }; + + return xleaf_get_leaf(xdev, subdev_match, &arg); +} + +static inline struct xrt_device * +xleaf_get_leaf_by_epname(struct xrt_device *xdev, const char *name) +{ + return xleaf_get_leaf(xdev, xrt_subdev_match_epname, (void *)name); +} + +static inline int xleaf_call(struct xrt_device *tgt, u32 cmd, void *arg) +{ + return (to_xrt_drv(tgt->dev.driver)->leaf_call)(tgt, cmd, arg); +} + +int xleaf_broadcast_event(struct xrt_device *xdev, enum xrt_events evt, bool async); +int xleaf_create_group(struct xrt_device *xdev, char *dtb); +int xleaf_destroy_group(struct xrt_device *xdev, int instance); +void xleaf_get_root_res(struct xrt_device *xdev, u32 region_id, struct resource **res); +void xleaf_get_root_id(struct xrt_device *xdev, unsigned short *vendor, unsigned short *device, + unsigned short *subvendor, unsigned short *subdevice); +void xleaf_hot_reset(struct xrt_device *xdev); +int xleaf_put_leaf(struct xrt_device *xdev, struct xrt_device *leaf); +struct device *xleaf_register_hwmon(struct xrt_device *xdev, const char *name, void *drvdata, + const struct attribute_group **grps); +void xleaf_unregister_hwmon(struct xrt_device *xdev, struct device *hwmon); +int xleaf_wait_for_group_bringup(struct xrt_device *xdev); + +/* + * Character device helper APIs for use by leaf drivers + */ +static inline bool xleaf_devnode_enabled(struct xrt_device *xdev) +{ + return DEV_FILE_OPS(xdev)->xsf_ops.open; +} + +int xleaf_devnode_create(struct xrt_device *xdev, + const char *file_name, const char *inst_name); +void xleaf_devnode_destroy(struct xrt_device *xdev); + +struct xrt_device *xleaf_devnode_open_excl(struct inode *inode); +struct xrt_device *xleaf_devnode_open(struct inode *inode); +void xleaf_devnode_close(struct inode *inode); + +/* Module's init/fini routines for leaf driver in xrt-lib module */ +#define XRT_LEAF_INIT_FINI_FUNC(name) \ +void name##_leaf_init_fini(bool init) \ +{ \ + if (init) \ + xrt_register_driver(&xrt_##name##_driver); \ + else \ + xrt_unregister_driver(&xrt_##name##_driver); \ +} + +/* Module's init/fini routines for leaf driver in xrt-lib module */ +void group_leaf_init_fini(bool init); +void vsec_leaf_init_fini(bool init); +void devctl_leaf_init_fini(bool init); +void axigate_leaf_init_fini(bool init); +void icap_leaf_init_fini(bool init); +void calib_leaf_init_fini(bool init); +void clkfreq_leaf_init_fini(bool init); +void clock_leaf_init_fini(bool init); +void ucs_leaf_init_fini(bool init); + +#endif /* _XRT_LEAF_H_ */ diff --git a/drivers/fpga/xrt/lib/lib-drv.c b/drivers/fpga/xrt/lib/lib-drv.c new file mode 100644 index 000000000000..ba4ac4930823 --- /dev/null +++ b/drivers/fpga/xrt/lib/lib-drv.c @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + * Lizhi Hou + */ + +#include +#include +#include +#include "xleaf.h" +#include "xroot.h" +#include "lib-drv.h" + +#define XRT_IPLIB_MODULE_NAME "xrt-lib" +#define XRT_IPLIB_MODULE_VERSION "4.0.0" +#define XRT_DRVNAME(drv) ((drv)->driver.name) + +#define XRT_SUBDEV_ID_SHIFT 16 +#define XRT_SUBDEV_ID_MASK ((1 << XRT_SUBDEV_ID_SHIFT) - 1) + +struct xrt_find_drv_data { + enum xrt_subdev_id id; + struct xrt_driver *xdrv; +}; + +struct class *xrt_class; +static DEFINE_IDA(xrt_device_ida); + +static inline u32 xrt_instance_to_id(enum xrt_subdev_id id, u32 instance) +{ + return (id << XRT_SUBDEV_ID_SHIFT) | instance; +} + +static inline u32 xrt_id_to_instance(u32 id) +{ + return (id & XRT_SUBDEV_ID_MASK); +} + +static int xrt_bus_match(struct device *dev, struct device_driver *drv) +{ + struct xrt_device *xdev = to_xrt_dev(dev); + struct xrt_driver *xdrv = to_xrt_drv(drv); + + if (xdev->subdev_id == xdrv->subdev_id) + return 1; + + return 0; +} + +static int xrt_bus_probe(struct device *dev) +{ + struct xrt_driver *xdrv = to_xrt_drv(dev->driver); + struct xrt_device *xdev = to_xrt_dev(dev); + + return xdrv->probe(xdev); +} + +static int xrt_bus_remove(struct device *dev) +{ + struct xrt_driver *xdrv = to_xrt_drv(dev->driver); + struct xrt_device *xdev = to_xrt_dev(dev); + + if (xdrv->remove) + xdrv->remove(xdev); + + return 0; +} + +struct bus_type xrt_bus_type = { + .name = "xrt", + .match = xrt_bus_match, + .probe = xrt_bus_probe, + .remove = xrt_bus_remove, +}; + +int xrt_register_driver(struct xrt_driver *drv) +{ + const char *drvname = XRT_DRVNAME(drv); + int rc = 0; + + /* Initialize dev_t for char dev node. */ + if (drv->file_ops.xsf_ops.open) { + rc = alloc_chrdev_region(&drv->file_ops.xsf_dev_t, 0, + XRT_MAX_DEVICE_NODES, drvname); + if (rc) { + pr_err("failed to alloc dev minor for %s: %d\n", drvname, rc); + return rc; + } + } else { + drv->file_ops.xsf_dev_t = (dev_t)-1; + } + + drv->driver.owner = THIS_MODULE; + drv->driver.bus = &xrt_bus_type; + + rc = driver_register(&drv->driver); + if (rc) { + pr_err("register %s xrt driver failed\n", drvname); + if (drv->file_ops.xsf_dev_t != (dev_t)-1) { + unregister_chrdev_region(drv->file_ops.xsf_dev_t, + XRT_MAX_DEVICE_NODES); + } + return rc; + } + + pr_info("%s registered successfully\n", drvname); + + return 0; +} +EXPORT_SYMBOL_GPL(xrt_register_driver); + +void xrt_unregister_driver(struct xrt_driver *drv) +{ + driver_unregister(&drv->driver); + + if (drv->file_ops.xsf_dev_t != (dev_t)-1) + unregister_chrdev_region(drv->file_ops.xsf_dev_t, XRT_MAX_DEVICE_NODES); + + pr_info("%s unregistered successfully\n", XRT_DRVNAME(drv)); +} +EXPORT_SYMBOL_GPL(xrt_unregister_driver); + +static int __find_driver(struct device_driver *drv, void *_data) +{ + struct xrt_driver *xdrv = to_xrt_drv(drv); + struct xrt_find_drv_data *data = _data; + + if (xdrv->subdev_id == data->id) { + data->xdrv = xdrv; + return 1; + } + + return 0; +} + +const char *xrt_drv_name(enum xrt_subdev_id id) +{ + struct xrt_find_drv_data data = { 0 }; + + data.id = id; + bus_for_each_drv(&xrt_bus_type, NULL, &data, __find_driver); + + if (data.xdrv) + return XRT_DRVNAME(data.xdrv); + + return NULL; +} + +static int xrt_drv_get_instance(enum xrt_subdev_id id) +{ + int ret; + + ret = ida_alloc_range(&xrt_device_ida, xrt_instance_to_id(id, 0), + xrt_instance_to_id(id, XRT_MAX_DEVICE_NODES), + GFP_KERNEL); + if (ret < 0) + return ret; + + return xrt_id_to_instance((u32)ret); +} + +static void xrt_drv_put_instance(enum xrt_subdev_id id, int instance) +{ + ida_free(&xrt_device_ida, xrt_instance_to_id(id, instance)); +} + +struct xrt_dev_endpoints *xrt_drv_get_endpoints(enum xrt_subdev_id id) +{ + struct xrt_find_drv_data data = { 0 }; + + data.id = id; + bus_for_each_drv(&xrt_bus_type, NULL, &data, __find_driver); + + if (data.xdrv) + return data.xdrv->endpoints; + + return NULL; +} + +static void xrt_device_release(struct device *dev) +{ + struct xrt_device *xdev = container_of(dev, struct xrt_device, dev); + + kfree(xdev); +} + +void xrt_device_unregister(struct xrt_device *xdev) +{ + if (xdev->state == XRT_DEVICE_STATE_ADDED) + device_del(&xdev->dev); + + vfree(xdev->sdev_data); + kfree(xdev->resource); + + if (xdev->instance != XRT_INVALID_DEVICE_INST) + xrt_drv_put_instance(xdev->subdev_id, xdev->instance); + + if (xdev->dev.release == xrt_device_release) + put_device(&xdev->dev); +} + +struct xrt_device * +xrt_device_register(struct device *parent, u32 id, + struct resource *res, u32 res_num, + void *pdata, size_t data_sz) +{ + struct xrt_device *xdev = NULL; + int ret; + + xdev = kzalloc(sizeof(*xdev), GFP_KERNEL); + if (!xdev) + return NULL; + xdev->instance = XRT_INVALID_DEVICE_INST; + + /* Obtain dev instance number. */ + ret = xrt_drv_get_instance(id); + if (ret < 0) { + dev_err(parent, "failed get instance, ret %d", ret); + goto fail; + } + + xdev->instance = ret; + xdev->name = xrt_drv_name(id); + xdev->subdev_id = id; + device_initialize(&xdev->dev); + xdev->dev.release = xrt_device_release; + xdev->dev.parent = parent; + + xdev->dev.bus = &xrt_bus_type; + dev_set_name(&xdev->dev, "%s.%d", xdev->name, xdev->instance); + + xdev->num_resources = res_num; + xdev->resource = kmemdup(res, sizeof(*res) * res_num, GFP_KERNEL); + if (!xdev->resource) + goto fail; + + xdev->sdev_data = vzalloc(data_sz); + if (!xdev->sdev_data) + goto fail; + + memcpy(xdev->sdev_data, pdata, data_sz); + + ret = device_add(&xdev->dev); + if (ret) { + dev_err(parent, "failed add device, ret %d", ret); + goto fail; + } + xdev->state = XRT_DEVICE_STATE_ADDED; + + return xdev; + +fail: + xrt_device_unregister(xdev); + kfree(xdev); + + return NULL; +} + +struct resource *xrt_get_resource(struct xrt_device *xdev, u32 type, u32 num) +{ + u32 i; + + for (i = 0; i < xdev->num_resources; i++) { + struct resource *r = &xdev->resource[i]; + + if (type == resource_type(r) && num-- == 0) + return r; + } + return NULL; +} + +/* + * Leaf driver's module init/fini callbacks. This is not a open infrastructure for dynamic + * plugging in drivers. All drivers should be statically added. + */ +static void (*leaf_init_fini_cbs[])(bool) = { + group_leaf_init_fini, + vsec_leaf_init_fini, + devctl_leaf_init_fini, + axigate_leaf_init_fini, + icap_leaf_init_fini, + calib_leaf_init_fini, + clkfreq_leaf_init_fini, + clock_leaf_init_fini, + ucs_leaf_init_fini, +}; + +static __init int xrt_lib_init(void) +{ + int ret; + int i; + + ret = bus_register(&xrt_bus_type); + if (ret) + return ret; + + xrt_class = class_create(THIS_MODULE, XRT_IPLIB_MODULE_NAME); + if (IS_ERR(xrt_class)) { + bus_unregister(&xrt_bus_type); + return PTR_ERR(xrt_class); + } + + for (i = 0; i < ARRAY_SIZE(leaf_init_fini_cbs); i++) + leaf_init_fini_cbs[i](true); + return 0; +} + +static __exit void xrt_lib_fini(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(leaf_init_fini_cbs); i++) + leaf_init_fini_cbs[i](false); + + class_destroy(xrt_class); + bus_unregister(&xrt_bus_type); +} + +module_init(xrt_lib_init); +module_exit(xrt_lib_fini); + +MODULE_VERSION(XRT_IPLIB_MODULE_VERSION); +MODULE_AUTHOR("XRT Team "); +MODULE_DESCRIPTION("Xilinx Alveo IP Lib driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/fpga/xrt/lib/lib-drv.h b/drivers/fpga/xrt/lib/lib-drv.h new file mode 100644 index 000000000000..0276c28e009f --- /dev/null +++ b/drivers/fpga/xrt/lib/lib-drv.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + */ + +#ifndef _LIB_DRV_H_ +#define _LIB_DRV_H_ + +#include +#include + +extern struct class *xrt_class; +extern struct bus_type xrt_bus_type; + +const char *xrt_drv_name(enum xrt_subdev_id id); +struct xrt_dev_endpoints *xrt_drv_get_endpoints(enum xrt_subdev_id id); + +#endif /* _LIB_DRV_H_ */ From patchwork Fri May 28 00:49:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 449622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 662EFC4707F for ; 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This is part of xrt driver infrastructure. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reviewed-by: Tom Rix --- drivers/fpga/xrt/lib/cdev.c | 209 ++++++++++++++++++++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 drivers/fpga/xrt/lib/cdev.c diff --git a/drivers/fpga/xrt/lib/cdev.c b/drivers/fpga/xrt/lib/cdev.c new file mode 100644 index 000000000000..3c20adac8c03 --- /dev/null +++ b/drivers/fpga/xrt/lib/cdev.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo FPGA device node helper functions. + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + */ + +#include "xleaf.h" +#include "lib-drv.h" + +#define XRT_CDEV_DIR "xrt" +#define INODE2PDATA(inode) \ + container_of((inode)->i_cdev, struct xrt_subdev_platdata, xsp_cdev) +#define INODE2PDEV(inode) \ + to_xrt_dev(kobj_to_dev((inode)->i_cdev->kobj.parent)) +#define CDEV_NAME(sysdev) (strchr((sysdev)->kobj.name, '!') + 1) + +/* Allow it to be accessed from cdev. */ +static void xleaf_devnode_allowed(struct xrt_device *xdev) +{ + struct xrt_subdev_platdata *pdata = DEV_PDATA(xdev); + + /* Allow new opens. */ + mutex_lock(&pdata->xsp_devnode_lock); + pdata->xsp_devnode_online = true; + mutex_unlock(&pdata->xsp_devnode_lock); +} + +/* Turn off access from cdev and wait for all existing user to go away. */ +static void xleaf_devnode_disallowed(struct xrt_device *xdev) +{ + struct xrt_subdev_platdata *pdata = DEV_PDATA(xdev); + + mutex_lock(&pdata->xsp_devnode_lock); + + /* Prevent new opens. */ + pdata->xsp_devnode_online = false; + /* Wait for existing user to close. */ + while (pdata->xsp_devnode_ref) { + mutex_unlock(&pdata->xsp_devnode_lock); + wait_for_completion(&pdata->xsp_devnode_comp); + mutex_lock(&pdata->xsp_devnode_lock); + } + + mutex_unlock(&pdata->xsp_devnode_lock); +} + +static struct xrt_device * +__xleaf_devnode_open(struct inode *inode, bool excl) +{ + struct xrt_subdev_platdata *pdata = INODE2PDATA(inode); + struct xrt_device *xdev = INODE2PDEV(inode); + bool opened = false; + + mutex_lock(&pdata->xsp_devnode_lock); + + if (pdata->xsp_devnode_online) { + if (excl && pdata->xsp_devnode_ref) { + xrt_err(xdev, "%s has already been opened exclusively", + CDEV_NAME(pdata->xsp_sysdev)); + } else if (!excl && pdata->xsp_devnode_excl) { + xrt_err(xdev, "%s has been opened exclusively", + CDEV_NAME(pdata->xsp_sysdev)); + } else { + pdata->xsp_devnode_ref++; + pdata->xsp_devnode_excl = excl; + opened = true; + xrt_info(xdev, "opened %s, ref=%d", + CDEV_NAME(pdata->xsp_sysdev), + pdata->xsp_devnode_ref); + } + } else { + xrt_err(xdev, "%s is offline", CDEV_NAME(pdata->xsp_sysdev)); + } + + mutex_unlock(&pdata->xsp_devnode_lock); + + xdev = opened ? xdev : NULL; + return xdev; +} + +struct xrt_device * +xleaf_devnode_open_excl(struct inode *inode) +{ + return __xleaf_devnode_open(inode, true); +} + +struct xrt_device * +xleaf_devnode_open(struct inode *inode) +{ + return __xleaf_devnode_open(inode, false); +} +EXPORT_SYMBOL_GPL(xleaf_devnode_open); + +void xleaf_devnode_close(struct inode *inode) +{ + struct xrt_subdev_platdata *pdata = INODE2PDATA(inode); + struct xrt_device *xdev = INODE2PDEV(inode); + bool notify = false; + + mutex_lock(&pdata->xsp_devnode_lock); + + WARN_ON(pdata->xsp_devnode_ref == 0); + pdata->xsp_devnode_ref--; + if (pdata->xsp_devnode_ref == 0) { + pdata->xsp_devnode_excl = false; + notify = true; + } + if (notify) + xrt_info(xdev, "closed %s", CDEV_NAME(pdata->xsp_sysdev)); + else + xrt_info(xdev, "closed %s, notifying waiter", CDEV_NAME(pdata->xsp_sysdev)); + + mutex_unlock(&pdata->xsp_devnode_lock); + + if (notify) + complete(&pdata->xsp_devnode_comp); +} +EXPORT_SYMBOL_GPL(xleaf_devnode_close); + +static inline enum xrt_dev_file_mode +devnode_mode(struct xrt_device *xdev) +{ + return DEV_FILE_OPS(xdev)->xsf_mode; +} + +int xleaf_devnode_create(struct xrt_device *xdev, const char *file_name, + const char *inst_name) +{ + struct xrt_subdev_platdata *pdata = DEV_PDATA(xdev); + struct xrt_dev_file_ops *fops = DEV_FILE_OPS(xdev); + struct cdev *cdevp; + struct device *sysdev; + int ret = 0; + char fname[256]; + + mutex_init(&pdata->xsp_devnode_lock); + init_completion(&pdata->xsp_devnode_comp); + + cdevp = &DEV_PDATA(xdev)->xsp_cdev; + cdev_init(cdevp, &fops->xsf_ops); + cdevp->owner = fops->xsf_ops.owner; + cdevp->dev = MKDEV(MAJOR(fops->xsf_dev_t), xdev->instance); + + /* + * Set xdev as parent of cdev so that when xdev (and its platform + * data) will not be freed when cdev is not freed. + */ + cdev_set_parent(cdevp, &DEV(xdev)->kobj); + + ret = cdev_add(cdevp, cdevp->dev, 1); + if (ret) { + xrt_err(xdev, "failed to add cdev: %d", ret); + goto failed; + } + if (!file_name) + file_name = xdev->name; + if (!inst_name) { + if (devnode_mode(xdev) == XRT_DEV_FILE_MULTI_INST) { + snprintf(fname, sizeof(fname), "%s/%s/%s.%u", + XRT_CDEV_DIR, DEV_PDATA(xdev)->xsp_root_name, + file_name, xdev->instance); + } else { + snprintf(fname, sizeof(fname), "%s/%s/%s", + XRT_CDEV_DIR, DEV_PDATA(xdev)->xsp_root_name, + file_name); + } + } else { + snprintf(fname, sizeof(fname), "%s/%s/%s.%s", XRT_CDEV_DIR, + DEV_PDATA(xdev)->xsp_root_name, file_name, inst_name); + } + sysdev = device_create(xrt_class, NULL, cdevp->dev, NULL, "%s", fname); + if (IS_ERR(sysdev)) { + ret = PTR_ERR(sysdev); + xrt_err(xdev, "failed to create device node: %d", ret); + goto failed_cdev_add; + } + pdata->xsp_sysdev = sysdev; + + xleaf_devnode_allowed(xdev); + + xrt_info(xdev, "created (%d, %d): /dev/%s", + MAJOR(cdevp->dev), xdev->instance, fname); + return 0; + +failed_cdev_add: + cdev_del(cdevp); +failed: + cdevp->owner = NULL; + return ret; +} + +void xleaf_devnode_destroy(struct xrt_device *xdev) +{ + struct xrt_subdev_platdata *pdata = DEV_PDATA(xdev); + struct cdev *cdevp = &pdata->xsp_cdev; + dev_t dev = cdevp->dev; + + xleaf_devnode_disallowed(xdev); + + xrt_info(xdev, "removed (%d, %d): /dev/%s/%s", MAJOR(dev), MINOR(dev), + XRT_CDEV_DIR, CDEV_NAME(pdata->xsp_sysdev)); + device_destroy(xrt_class, cdevp->dev); + pdata->xsp_sysdev = NULL; + cdev_del(cdevp); +} From patchwork Fri May 28 00:49:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 449620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F794C4707F for ; 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This is part of root driver infrastructure. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reviewed-by: Tom Rix --- drivers/fpga/xrt/include/events.h | 45 +++ drivers/fpga/xrt/include/xroot.h | 117 +++++++ drivers/fpga/xrt/lib/subdev_pool.h | 53 +++ drivers/fpga/xrt/lib/xroot.c | 536 +++++++++++++++++++++++++++++ 4 files changed, 751 insertions(+) create mode 100644 drivers/fpga/xrt/include/events.h create mode 100644 drivers/fpga/xrt/include/xroot.h create mode 100644 drivers/fpga/xrt/lib/subdev_pool.h create mode 100644 drivers/fpga/xrt/lib/xroot.c diff --git a/drivers/fpga/xrt/include/events.h b/drivers/fpga/xrt/include/events.h new file mode 100644 index 000000000000..775171a47c8e --- /dev/null +++ b/drivers/fpga/xrt/include/events.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + */ + +#ifndef _XRT_EVENTS_H_ +#define _XRT_EVENTS_H_ + +#include "subdev_id.h" + +/* + * Event notification. + */ +enum xrt_events { + XRT_EVENT_TEST = 0, /* for testing */ + /* + * Events related to specific subdev + * Callback arg: struct xrt_event_arg_subdev + */ + XRT_EVENT_POST_CREATION, + XRT_EVENT_PRE_REMOVAL, + /* + * Events related to change of the whole board + * Callback arg: + */ + XRT_EVENT_PRE_HOT_RESET, + XRT_EVENT_POST_HOT_RESET, + XRT_EVENT_PRE_GATE_CLOSE, + XRT_EVENT_POST_GATE_OPEN, +}; + +struct xrt_event_arg_subdev { + enum xrt_subdev_id xevt_subdev_id; + int xevt_subdev_instance; +}; + +struct xrt_event { + enum xrt_events xe_evt; + struct xrt_event_arg_subdev xe_subdev; +}; + +#endif /* _XRT_EVENTS_H_ */ diff --git a/drivers/fpga/xrt/include/xroot.h b/drivers/fpga/xrt/include/xroot.h new file mode 100644 index 000000000000..56461bcb07a9 --- /dev/null +++ b/drivers/fpga/xrt/include/xroot.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + */ + +#ifndef _XRT_ROOT_H_ +#define _XRT_ROOT_H_ + +#include "xdevice.h" +#include "subdev_id.h" +#include "events.h" + +typedef bool (*xrt_subdev_match_t)(enum xrt_subdev_id, struct xrt_device *, void *); +#define XRT_SUBDEV_MATCH_PREV ((xrt_subdev_match_t)-1) +#define XRT_SUBDEV_MATCH_NEXT ((xrt_subdev_match_t)-2) + +/* + * Root calls. + */ +enum xrt_root_cmd { + /* Leaf actions. */ + XRT_ROOT_GET_LEAF = 0, + XRT_ROOT_PUT_LEAF, + XRT_ROOT_GET_LEAF_HOLDERS, + + /* Group actions. */ + XRT_ROOT_CREATE_GROUP, + XRT_ROOT_REMOVE_GROUP, + XRT_ROOT_LOOKUP_GROUP, + XRT_ROOT_WAIT_GROUP_BRINGUP, + + /* Event actions. */ + XRT_ROOT_EVENT_SYNC, + XRT_ROOT_EVENT_ASYNC, + + /* Device info. */ + XRT_ROOT_GET_RESOURCE, + XRT_ROOT_GET_ID, + + /* Misc. */ + XRT_ROOT_HOT_RESET, + XRT_ROOT_HWMON, +}; + +struct xrt_root_get_leaf { + struct xrt_device *xpigl_caller_xdev; + xrt_subdev_match_t xpigl_match_cb; + void *xpigl_match_arg; + struct xrt_device *xpigl_tgt_xdev; +}; + +struct xrt_root_put_leaf { + struct xrt_device *xpipl_caller_xdev; + struct xrt_device *xpipl_tgt_xdev; +}; + +struct xrt_root_lookup_group { + struct xrt_device *xpilp_xdev; /* caller's xdev */ + xrt_subdev_match_t xpilp_match_cb; + void *xpilp_match_arg; + int xpilp_grp_inst; +}; + +struct xrt_root_get_holders { + struct xrt_device *xpigh_xdev; /* caller's xdev */ + char *xpigh_holder_buf; + size_t xpigh_holder_buf_len; +}; + +struct xrt_root_get_res { + u32 xpigr_region_id; + struct resource *xpigr_res; +}; + +struct xrt_root_get_id { + unsigned short xpigi_vendor_id; + unsigned short xpigi_device_id; + unsigned short xpigi_sub_vendor_id; + unsigned short xpigi_sub_device_id; +}; + +struct xrt_root_hwmon { + bool xpih_register; + const char *xpih_name; + void *xpih_drvdata; + const struct attribute_group **xpih_groups; + struct device *xpih_hwmon_dev; +}; + +/* + * Callback for leaf to make a root request. Arguments are: parent device, parent cookie, req, + * and arg. + */ +typedef int (*xrt_subdev_root_cb_t)(struct device *, void *, u32, void *); +int xrt_subdev_root_request(struct xrt_device *self, u32 cmd, void *arg); + +/* + * Defines physical function (MPF / UPF) specific operations + * needed in common root driver. + */ +struct xroot_physical_function_callback { + void (*xpc_get_id)(struct device *dev, struct xrt_root_get_id *rid); + int (*xpc_get_resource)(struct device *dev, struct xrt_root_get_res *res); + void (*xpc_hot_reset)(struct device *dev); +}; + +int xroot_probe(struct device *dev, struct xroot_physical_function_callback *cb, void **root); +void xroot_remove(void *root); +bool xroot_wait_for_bringup(void *root); +int xroot_create_group(void *xr, char *dtb); +int xroot_add_simple_node(void *root, char *dtb, const char *endpoint); +void xroot_broadcast(void *root, enum xrt_events evt); + +#endif /* _XRT_ROOT_H_ */ diff --git a/drivers/fpga/xrt/lib/subdev_pool.h b/drivers/fpga/xrt/lib/subdev_pool.h new file mode 100644 index 000000000000..03f617d7ffd7 --- /dev/null +++ b/drivers/fpga/xrt/lib/subdev_pool.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + */ + +#ifndef _XRT_SUBDEV_POOL_H_ +#define _XRT_SUBDEV_POOL_H_ + +#include +#include +#include "xroot.h" + +/* + * The struct xrt_subdev_pool manages a list of xrt_subdevs for root and group drivers. + */ +struct xrt_subdev_pool { + struct list_head xsp_dev_list; + struct device *xsp_owner; + struct mutex xsp_lock; /* pool lock */ + bool xsp_closing; +}; + +/* + * Subdev pool helper functions for root and group drivers only. + */ +void xrt_subdev_pool_init(struct device *dev, + struct xrt_subdev_pool *spool); +void xrt_subdev_pool_fini(struct xrt_subdev_pool *spool); +int xrt_subdev_pool_get(struct xrt_subdev_pool *spool, + xrt_subdev_match_t match, + void *arg, struct device *holder_dev, + struct xrt_device **xdevp); +int xrt_subdev_pool_put(struct xrt_subdev_pool *spool, + struct xrt_device *xdev, + struct device *holder_dev); +int xrt_subdev_pool_add(struct xrt_subdev_pool *spool, + enum xrt_subdev_id id, xrt_subdev_root_cb_t pcb, + void *pcb_arg, char *dtb); +int xrt_subdev_pool_del(struct xrt_subdev_pool *spool, + enum xrt_subdev_id id, int instance); +ssize_t xrt_subdev_pool_get_holders(struct xrt_subdev_pool *spool, + struct xrt_device *xdev, + char *buf, size_t len); + +void xrt_subdev_pool_trigger_event(struct xrt_subdev_pool *spool, + enum xrt_events evt); +void xrt_subdev_pool_handle_event(struct xrt_subdev_pool *spool, + struct xrt_event *evt); + +#endif /* _XRT_SUBDEV_POOL_H_ */ diff --git a/drivers/fpga/xrt/lib/xroot.c b/drivers/fpga/xrt/lib/xroot.c new file mode 100644 index 000000000000..7b3e540dd6c0 --- /dev/null +++ b/drivers/fpga/xrt/lib/xroot.c @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo FPGA Root Functions + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + */ + +#include +#include +#include "xroot.h" +#include "subdev_pool.h" +#include "group.h" +#include "metadata.h" + +#define xroot_err(xr, fmt, args...) dev_err((xr)->dev, "%s: " fmt, __func__, ##args) +#define xroot_warn(xr, fmt, args...) dev_warn((xr)->dev, "%s: " fmt, __func__, ##args) +#define xroot_info(xr, fmt, args...) dev_info((xr)->dev, "%s: " fmt, __func__, ##args) +#define xroot_dbg(xr, fmt, args...) dev_dbg((xr)->dev, "%s: " fmt, __func__, ##args) + +#define XROOT_GROUP_FIRST (-1) +#define XROOT_GROUP_LAST (-2) + +static int xroot_root_cb(struct device *, void *, u32, void *); + +struct xroot_evt { + struct list_head list; + struct xrt_event evt; + struct completion comp; + bool async; +}; + +struct xroot_events { + struct mutex evt_lock; /* event lock */ + struct list_head evt_list; + struct work_struct evt_work; +}; + +struct xroot_groups { + struct xrt_subdev_pool pool; + struct work_struct bringup_work; + atomic_t bringup_pending_cnt; + atomic_t bringup_failed_cnt; + struct completion bringup_comp; +}; + +struct xroot { + struct device *dev; + struct xroot_events events; + struct xroot_groups groups; + struct xroot_physical_function_callback pf_cb; +}; + +struct xroot_group_match_arg { + enum xrt_subdev_id id; + int instance; +}; + +static bool xroot_group_match(enum xrt_subdev_id id, struct xrt_device *xdev, void *arg) +{ + struct xroot_group_match_arg *a = (struct xroot_group_match_arg *)arg; + + /* xdev->instance is the instance of the subdev. */ + return id == a->id && xdev->instance == a->instance; +} + +static int xroot_get_group(struct xroot *xr, int instance, struct xrt_device **grpp) +{ + int rc = 0; + struct xrt_subdev_pool *grps = &xr->groups.pool; + struct device *dev = xr->dev; + struct xroot_group_match_arg arg = { XRT_SUBDEV_GRP, instance }; + + if (instance == XROOT_GROUP_LAST) { + rc = xrt_subdev_pool_get(grps, XRT_SUBDEV_MATCH_NEXT, + *grpp, dev, grpp); + } else if (instance == XROOT_GROUP_FIRST) { + rc = xrt_subdev_pool_get(grps, XRT_SUBDEV_MATCH_PREV, + *grpp, dev, grpp); + } else { + rc = xrt_subdev_pool_get(grps, xroot_group_match, + &arg, dev, grpp); + } + + if (rc && rc != -ENOENT) + xroot_err(xr, "failed to hold group %d: %d", instance, rc); + return rc; +} + +static void xroot_put_group(struct xroot *xr, struct xrt_device *grp) +{ + int inst = grp->instance; + int rc = xrt_subdev_pool_put(&xr->groups.pool, grp, xr->dev); + + if (rc) + xroot_err(xr, "failed to release group %d: %d", inst, rc); +} + +static int xroot_trigger_event(struct xroot *xr, struct xrt_event *e, bool async) +{ + struct xroot_evt *enew = vzalloc(sizeof(*enew)); + + if (!enew) + return -ENOMEM; + + enew->evt = *e; + enew->async = async; + init_completion(&enew->comp); + + mutex_lock(&xr->events.evt_lock); + list_add(&enew->list, &xr->events.evt_list); + mutex_unlock(&xr->events.evt_lock); + + schedule_work(&xr->events.evt_work); + + if (async) + return 0; + + wait_for_completion(&enew->comp); + vfree(enew); + return 0; +} + +static void +xroot_group_trigger_event(struct xroot *xr, int inst, enum xrt_events e) +{ + int ret; + struct xrt_device *xdev = NULL; + struct xrt_event evt = { 0 }; + + WARN_ON(inst < 0); + /* Only triggers subdev specific events. */ + if (e != XRT_EVENT_POST_CREATION && e != XRT_EVENT_PRE_REMOVAL) { + xroot_err(xr, "invalid event %d", e); + return; + } + + ret = xroot_get_group(xr, inst, &xdev); + if (ret) + return; + + /* Triggers event for children, first. */ + xleaf_call(xdev, XRT_GROUP_TRIGGER_EVENT, (void *)(uintptr_t)e); + + /* Triggers event for itself. */ + evt.xe_evt = e; + evt.xe_subdev.xevt_subdev_id = XRT_SUBDEV_GRP; + evt.xe_subdev.xevt_subdev_instance = inst; + xroot_trigger_event(xr, &evt, false); + + xroot_put_group(xr, xdev); +} + +int xroot_create_group(void *root, char *dtb) +{ + struct xroot *xr = (struct xroot *)root; + int ret; + + atomic_inc(&xr->groups.bringup_pending_cnt); + ret = xrt_subdev_pool_add(&xr->groups.pool, XRT_SUBDEV_GRP, xroot_root_cb, xr, dtb); + if (ret >= 0) { + schedule_work(&xr->groups.bringup_work); + } else { + atomic_dec(&xr->groups.bringup_pending_cnt); + atomic_inc(&xr->groups.bringup_failed_cnt); + xroot_err(xr, "failed to create group: %d", ret); + } + return ret; +} +EXPORT_SYMBOL_GPL(xroot_create_group); + +static int xroot_destroy_single_group(struct xroot *xr, int instance) +{ + struct xrt_device *xdev = NULL; + int ret; + + WARN_ON(instance < 0); + ret = xroot_get_group(xr, instance, &xdev); + if (ret) + return ret; + + xroot_group_trigger_event(xr, instance, XRT_EVENT_PRE_REMOVAL); + + /* Now tear down all children in this group. */ + ret = xleaf_call(xdev, XRT_GROUP_FINI_CHILDREN, NULL); + xroot_put_group(xr, xdev); + if (!ret) + ret = xrt_subdev_pool_del(&xr->groups.pool, XRT_SUBDEV_GRP, instance); + + return ret; +} + +static int xroot_destroy_group(struct xroot *xr, int instance) +{ + struct xrt_device *target = NULL; + struct xrt_device *deps = NULL; + int ret; + + WARN_ON(instance < 0); + /* + * Make sure target group exists and can't go away before + * we remove it's dependents + */ + ret = xroot_get_group(xr, instance, &target); + if (ret) + return ret; + + /* + * Remove all groups depend on target one. + * Assuming subdevs in higher group ID can depend on ones in + * lower ID groups, we remove them in the reservse order. + */ + while (xroot_get_group(xr, XROOT_GROUP_LAST, &deps) != -ENOENT) { + int inst = deps->instance; + + xroot_put_group(xr, deps); + /* Reached the target group instance, stop here. */ + if (instance == inst) + break; + xroot_destroy_single_group(xr, inst); + deps = NULL; + } + + /* Now we can remove the target group. */ + xroot_put_group(xr, target); + return xroot_destroy_single_group(xr, instance); +} + +static int xroot_lookup_group(struct xroot *xr, + struct xrt_root_lookup_group *arg) +{ + int rc = -ENOENT; + struct xrt_device *grp = NULL; + + while (rc < 0 && xroot_get_group(xr, XROOT_GROUP_LAST, &grp) != -ENOENT) { + if (arg->xpilp_match_cb(XRT_SUBDEV_GRP, grp, arg->xpilp_match_arg)) + rc = grp->instance; + xroot_put_group(xr, grp); + } + return rc; +} + +static void xroot_event_work(struct work_struct *work) +{ + struct xroot_evt *tmp; + struct xroot *xr = container_of(work, struct xroot, events.evt_work); + + mutex_lock(&xr->events.evt_lock); + while (!list_empty(&xr->events.evt_list)) { + tmp = list_first_entry(&xr->events.evt_list, struct xroot_evt, list); + list_del(&tmp->list); + mutex_unlock(&xr->events.evt_lock); + + xrt_subdev_pool_handle_event(&xr->groups.pool, &tmp->evt); + + if (tmp->async) + vfree(tmp); + else + complete(&tmp->comp); + + mutex_lock(&xr->events.evt_lock); + } + mutex_unlock(&xr->events.evt_lock); +} + +static void xroot_event_init(struct xroot *xr) +{ + INIT_LIST_HEAD(&xr->events.evt_list); + mutex_init(&xr->events.evt_lock); + INIT_WORK(&xr->events.evt_work, xroot_event_work); +} + +static void xroot_event_fini(struct xroot *xr) +{ + flush_scheduled_work(); + WARN_ON(!list_empty(&xr->events.evt_list)); +} + +static int xroot_get_leaf(struct xroot *xr, struct xrt_root_get_leaf *arg) +{ + int rc = -ENOENT; + struct xrt_device *grp = NULL; + + while (rc && xroot_get_group(xr, XROOT_GROUP_LAST, &grp) != -ENOENT) { + rc = xleaf_call(grp, XRT_GROUP_GET_LEAF, arg); + xroot_put_group(xr, grp); + } + return rc; +} + +static int xroot_put_leaf(struct xroot *xr, struct xrt_root_put_leaf *arg) +{ + int rc = -ENOENT; + struct xrt_device *grp = NULL; + + while (rc && xroot_get_group(xr, XROOT_GROUP_LAST, &grp) != -ENOENT) { + rc = xleaf_call(grp, XRT_GROUP_PUT_LEAF, arg); + xroot_put_group(xr, grp); + } + return rc; +} + +static int xroot_root_cb(struct device *dev, void *parg, enum xrt_root_cmd cmd, void *arg) +{ + struct xroot *xr = (struct xroot *)parg; + int rc = 0; + + switch (cmd) { + /* Leaf actions. */ + case XRT_ROOT_GET_LEAF: { + struct xrt_root_get_leaf *getleaf = (struct xrt_root_get_leaf *)arg; + + rc = xroot_get_leaf(xr, getleaf); + break; + } + case XRT_ROOT_PUT_LEAF: { + struct xrt_root_put_leaf *putleaf = (struct xrt_root_put_leaf *)arg; + + rc = xroot_put_leaf(xr, putleaf); + break; + } + case XRT_ROOT_GET_LEAF_HOLDERS: { + struct xrt_root_get_holders *holders = (struct xrt_root_get_holders *)arg; + + rc = xrt_subdev_pool_get_holders(&xr->groups.pool, + holders->xpigh_xdev, + holders->xpigh_holder_buf, + holders->xpigh_holder_buf_len); + break; + } + + /* Group actions. */ + case XRT_ROOT_CREATE_GROUP: + rc = xroot_create_group(xr, (char *)arg); + break; + case XRT_ROOT_REMOVE_GROUP: + rc = xroot_destroy_group(xr, (int)(uintptr_t)arg); + break; + case XRT_ROOT_LOOKUP_GROUP: { + struct xrt_root_lookup_group *getgrp = (struct xrt_root_lookup_group *)arg; + + rc = xroot_lookup_group(xr, getgrp); + break; + } + case XRT_ROOT_WAIT_GROUP_BRINGUP: + rc = xroot_wait_for_bringup(xr) ? 0 : -EINVAL; + break; + + /* Event actions. */ + case XRT_ROOT_EVENT_SYNC: + case XRT_ROOT_EVENT_ASYNC: { + bool async = (cmd == XRT_ROOT_EVENT_ASYNC); + struct xrt_event *evt = (struct xrt_event *)arg; + + rc = xroot_trigger_event(xr, evt, async); + break; + } + + /* Device info. */ + case XRT_ROOT_GET_RESOURCE: { + struct xrt_root_get_res *res = (struct xrt_root_get_res *)arg; + + if (xr->pf_cb.xpc_get_resource) { + rc = xr->pf_cb.xpc_get_resource(xr->dev, res); + } else { + xroot_err(xr, "get resource is not supported"); + rc = -EOPNOTSUPP; + } + break; + } + case XRT_ROOT_GET_ID: { + struct xrt_root_get_id *id = (struct xrt_root_get_id *)arg; + + if (xr->pf_cb.xpc_get_id) + xr->pf_cb.xpc_get_id(xr->dev, id); + else + memset(id, 0, sizeof(*id)); + break; + } + + /* MISC generic root driver functions. */ + case XRT_ROOT_HOT_RESET: { + if (xr->pf_cb.xpc_hot_reset) { + xr->pf_cb.xpc_hot_reset(xr->dev); + } else { + xroot_err(xr, "hot reset is not supported"); + rc = -EOPNOTSUPP; + } + break; + } + case XRT_ROOT_HWMON: { + struct xrt_root_hwmon *hwmon = (struct xrt_root_hwmon *)arg; + + if (hwmon->xpih_register) { + hwmon->xpih_hwmon_dev = + hwmon_device_register_with_info(xr->dev, + hwmon->xpih_name, + hwmon->xpih_drvdata, + NULL, + hwmon->xpih_groups); + } else { + hwmon_device_unregister(hwmon->xpih_hwmon_dev); + } + break; + } + + default: + xroot_err(xr, "unknown IOCTL cmd %d", cmd); + rc = -EINVAL; + break; + } + + return rc; +} + +static void xroot_bringup_group_work(struct work_struct *work) +{ + struct xrt_device *xdev = NULL; + struct xroot *xr = container_of(work, struct xroot, groups.bringup_work); + + while (xroot_get_group(xr, XROOT_GROUP_FIRST, &xdev) != -ENOENT) { + int r, i; + + i = xdev->instance; + r = xleaf_call(xdev, XRT_GROUP_INIT_CHILDREN, NULL); + xroot_put_group(xr, xdev); + if (r == -EEXIST) + continue; /* Already brough up, nothing to do. */ + if (r) + atomic_inc(&xr->groups.bringup_failed_cnt); + + xroot_group_trigger_event(xr, i, XRT_EVENT_POST_CREATION); + + if (atomic_dec_and_test(&xr->groups.bringup_pending_cnt)) + complete(&xr->groups.bringup_comp); + } +} + +static void xroot_groups_init(struct xroot *xr) +{ + xrt_subdev_pool_init(xr->dev, &xr->groups.pool); + INIT_WORK(&xr->groups.bringup_work, xroot_bringup_group_work); + atomic_set(&xr->groups.bringup_pending_cnt, 0); + atomic_set(&xr->groups.bringup_failed_cnt, 0); + init_completion(&xr->groups.bringup_comp); +} + +static void xroot_groups_fini(struct xroot *xr) +{ + flush_scheduled_work(); + xrt_subdev_pool_fini(&xr->groups.pool); +} + +int xroot_add_simple_node(void *root, char *dtb, const char *endpoint) +{ + struct xroot *xr = (struct xroot *)root; + struct device *dev = xr->dev; + struct xrt_md_endpoint ep = { 0 }; + int ret = 0; + + ep.ep_name = endpoint; + ret = xrt_md_add_endpoint(dev, dtb, &ep); + if (ret) + xroot_err(xr, "add %s failed, ret %d", endpoint, ret); + + return ret; +} +EXPORT_SYMBOL_GPL(xroot_add_simple_node); + +bool xroot_wait_for_bringup(void *root) +{ + struct xroot *xr = (struct xroot *)root; + + wait_for_completion(&xr->groups.bringup_comp); + return atomic_read(&xr->groups.bringup_failed_cnt) == 0; +} +EXPORT_SYMBOL_GPL(xroot_wait_for_bringup); + +int xroot_probe(struct device *dev, struct xroot_physical_function_callback *cb, void **root) +{ + struct xroot *xr = NULL; + + dev_info(dev, "%s: probing...", __func__); + + xr = devm_kzalloc(dev, sizeof(*xr), GFP_KERNEL); + if (!xr) + return -ENOMEM; + + xr->dev = dev; + xr->pf_cb = *cb; + xroot_groups_init(xr); + xroot_event_init(xr); + + *root = xr; + return 0; +} +EXPORT_SYMBOL_GPL(xroot_probe); + +void xroot_remove(void *root) +{ + struct xroot *xr = (struct xroot *)root; + struct xrt_device *grp = NULL; + + xroot_info(xr, "leaving..."); + + if (xroot_get_group(xr, XROOT_GROUP_FIRST, &grp) == 0) { + int instance = grp->instance; + + xroot_put_group(xr, grp); + xroot_destroy_group(xr, instance); + } + + xroot_event_fini(xr); + xroot_groups_fini(xr); +} +EXPORT_SYMBOL_GPL(xroot_remove); + +void xroot_broadcast(void *root, enum xrt_events evt) +{ + struct xroot *xr = (struct xroot *)root; + struct xrt_event e = { 0 }; + + /* Root pf driver only broadcasts below two events. */ + if (evt != XRT_EVENT_POST_CREATION && evt != XRT_EVENT_PRE_REMOVAL) { + xroot_info(xr, "invalid event %d", evt); + return; + } + + e.xe_evt = evt; + e.xe_subdev.xevt_subdev_id = XRT_ROOT; + e.xe_subdev.xevt_subdev_instance = 0; + xroot_trigger_event(xr, &e, false); +} +EXPORT_SYMBOL_GPL(xroot_broadcast); From patchwork Fri May 28 00:49:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 449619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA4E4C4707F for ; Fri, 28 May 2021 00:52:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 91626613AF for ; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 00:52:15.5039 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9dc6c546-abd9-4c53-4154-08d92172d664 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT020.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR02MB8233 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PCIE device driver which attaches to management function on Alveo devices. It instantiates one or more group drivers which, in turn, instantiate xrt drivers. The instantiation of group and xrt drivers is completely dtb driven. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reviewed-by: Tom Rix --- drivers/fpga/xrt/mgmt/root.c | 420 +++++++++++++++++++++++++++++++++++ 1 file changed, 420 insertions(+) create mode 100644 drivers/fpga/xrt/mgmt/root.c diff --git a/drivers/fpga/xrt/mgmt/root.c b/drivers/fpga/xrt/mgmt/root.c new file mode 100644 index 000000000000..9f3c806a9eaa --- /dev/null +++ b/drivers/fpga/xrt/mgmt/root.c @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo Management Function Driver + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + */ + +#include +#include +#include +#include +#include + +#include "xroot.h" +#include "xmgmt.h" +#include "metadata.h" + +#define XMGMT_MODULE_NAME "xrt-mgmt" +#define XMGMT_DRIVER_VERSION "4.0.0" + +#define XMGMT_PDEV(xm) ((xm)->pdev) +#define XMGMT_DEV(xm) (&(XMGMT_PDEV(xm)->dev)) +#define xmgmt_err(xm, fmt, args...) \ + dev_err(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define xmgmt_warn(xm, fmt, args...) \ + dev_warn(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define xmgmt_info(xm, fmt, args...) \ + dev_info(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define xmgmt_dbg(xm, fmt, args...) \ + dev_dbg(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define XMGMT_DEV_ID(_pcidev) \ + ({ typeof(_pcidev) (pcidev) = (_pcidev); \ + ((pci_domain_nr((pcidev)->bus) << 16) | \ + PCI_DEVID((pcidev)->bus->number, 0)); }) +#define XRT_VSEC_ID 0x20 +#define XRT_MAX_READRQ 512 + +static struct class *xmgmt_class; + +/* PCI Device IDs */ +/* + * Golden image is preloaded on the device when it is shipped to customer. + * Then, customer can load other shells (from Xilinx or some other vendor). + * If something goes wrong with the shell, customer can always go back to + * golden and start over again. + */ +#define PCI_DEVICE_ID_U50_GOLDEN 0xD020 +#define PCI_DEVICE_ID_U50 0x5020 +static const struct pci_device_id xmgmt_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_U50_GOLDEN), }, /* Alveo U50 (golden) */ + { PCI_DEVICE(PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_U50), }, /* Alveo U50 */ + { 0, } +}; + +struct xmgmt { + struct pci_dev *pdev; + void *root; + + bool ready; +}; + +static int xmgmt_config_pci(struct xmgmt *xm) +{ + struct pci_dev *pdev = XMGMT_PDEV(xm); + int rc; + + rc = pcim_enable_device(pdev); + if (rc < 0) { + xmgmt_err(xm, "failed to enable device: %d", rc); + return rc; + } + + rc = pci_enable_pcie_error_reporting(pdev); + if (rc) + xmgmt_warn(xm, "failed to enable AER: %d", rc); + + pci_set_master(pdev); + + rc = pcie_get_readrq(pdev); + if (rc > XRT_MAX_READRQ) + pcie_set_readrq(pdev, XRT_MAX_READRQ); + return 0; +} + +static int xmgmt_match_slot_and_save(struct device *dev, void *data) +{ + struct xmgmt *xm = data; + struct pci_dev *pdev = to_pci_dev(dev); + + if (XMGMT_DEV_ID(pdev) == XMGMT_DEV_ID(xm->pdev)) { + pci_cfg_access_lock(pdev); + pci_save_state(pdev); + } + + return 0; +} + +static void xmgmt_pci_save_config_all(struct xmgmt *xm) +{ + bus_for_each_dev(&pci_bus_type, NULL, xm, xmgmt_match_slot_and_save); +} + +static int xmgmt_match_slot_and_restore(struct device *dev, void *data) +{ + struct xmgmt *xm = data; + struct pci_dev *pdev = to_pci_dev(dev); + + if (XMGMT_DEV_ID(pdev) == XMGMT_DEV_ID(xm->pdev)) { + pci_restore_state(pdev); + pci_cfg_access_unlock(pdev); + } + + return 0; +} + +static void xmgmt_pci_restore_config_all(struct xmgmt *xm) +{ + bus_for_each_dev(&pci_bus_type, NULL, xm, xmgmt_match_slot_and_restore); +} + +static void xmgmt_root_hot_reset(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct pci_bus *bus; + u16 pci_cmd, devctl; + struct xmgmt *xm; + u8 pci_bctl; + int i, ret; + + xm = pci_get_drvdata(pdev); + xmgmt_info(xm, "hot reset start"); + xmgmt_pci_save_config_all(xm); + pci_disable_device(pdev); + bus = pdev->bus; + + /* + * When flipping the SBR bit, device can fall off the bus. This is + * usually no problem at all so long as drivers are working properly + * after SBR. However, some systems complain bitterly when the device + * falls off the bus. + * The quick solution is to temporarily disable the SERR reporting of + * switch port during SBR. + */ + + pci_read_config_word(bus->self, PCI_COMMAND, &pci_cmd); + pci_write_config_word(bus->self, PCI_COMMAND, (pci_cmd & ~PCI_COMMAND_SERR)); + pcie_capability_read_word(bus->self, PCI_EXP_DEVCTL, &devctl); + pcie_capability_write_word(bus->self, PCI_EXP_DEVCTL, (devctl & ~PCI_EXP_DEVCTL_FERE)); + pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); + pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl | PCI_BRIDGE_CTL_BUS_RESET); + msleep(100); + pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); + ssleep(1); + + pcie_capability_write_word(bus->self, PCI_EXP_DEVCTL, devctl); + pci_write_config_word(bus->self, PCI_COMMAND, pci_cmd); + + ret = pci_enable_device(pdev); + if (ret) + xmgmt_err(xm, "failed to enable device, ret %d", ret); + + for (i = 0; i < 300; i++) { + pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); + if (pci_cmd != 0xffff) + break; + msleep(20); + } + if (i == 300) + xmgmt_err(xm, "timed out waiting for device to be online after reset"); + + xmgmt_info(xm, "waiting for %d ms", i * 20); + xmgmt_pci_restore_config_all(xm); + xmgmt_config_pci(xm); +} + +static int xmgmt_add_vsec_node(struct xmgmt *xm, char *dtb) +{ + struct pci_dev *pdev = XMGMT_PDEV(xm); + struct xrt_md_endpoint ep = { 0 }; + struct device *dev = DEV(pdev); + u32 off_low, off_high, header; + int cap = 0, ret = 0; + __be32 vsec_bar; + __be64 vsec_off; + + while ((cap = pci_find_next_ext_capability(pdev, cap, PCI_EXT_CAP_ID_VNDR))) { + pci_read_config_dword(pdev, cap + PCI_VNDR_HEADER, &header); + if (PCI_VNDR_HEADER_ID(header) == XRT_VSEC_ID) + break; + } + if (!cap) { + xmgmt_info(xm, "No Vendor Specific Capability."); + return -ENOENT; + } + + if (pci_read_config_dword(pdev, cap + 8, &off_low) || + pci_read_config_dword(pdev, cap + 12, &off_high)) { + xmgmt_err(xm, "pci_read vendor specific failed."); + return -EINVAL; + } + + ep.ep_name = XRT_MD_NODE_VSEC; + ret = xrt_md_add_endpoint(dev, dtb, &ep); + if (ret) { + xmgmt_err(xm, "add vsec metadata failed, ret %d", ret); + goto failed; + } + + vsec_bar = cpu_to_be32(off_low & 0xf); + ret = xrt_md_set_prop(dev, dtb, XRT_MD_NODE_VSEC, NULL, + XRT_MD_PROP_BAR_IDX, &vsec_bar, sizeof(vsec_bar)); + if (ret) { + xmgmt_err(xm, "add vsec bar idx failed, ret %d", ret); + goto failed; + } + + vsec_off = cpu_to_be64(((u64)off_high << 32) | (off_low & ~0xfU)); + ret = xrt_md_set_prop(dev, dtb, XRT_MD_NODE_VSEC, NULL, + XRT_MD_PROP_OFFSET, &vsec_off, sizeof(vsec_off)); + if (ret) { + xmgmt_err(xm, "add vsec offset failed, ret %d", ret); + goto failed; + } + +failed: + return ret; +} + +static int xmgmt_create_root_metadata(struct xmgmt *xm, char **root_dtb) +{ + char *dtb = NULL; + int ret; + + ret = xrt_md_create(XMGMT_DEV(xm), &dtb); + if (ret) { + xmgmt_err(xm, "create metadata failed, ret %d", ret); + goto failed; + } + + ret = xmgmt_add_vsec_node(xm, dtb); + if (ret == -ENOENT) { + /* + * We may be dealing with a MFG board. + * Try vsec-golden which will bring up all hard-coded leaves + * at hard-coded offsets. + */ + ret = xroot_add_simple_node(xm->root, dtb, XRT_MD_NODE_VSEC_GOLDEN); + } else if (ret == 0) { + ret = xroot_add_simple_node(xm->root, dtb, XRT_MD_NODE_MGMT_MAIN); + } + if (ret) + goto failed; + + *root_dtb = dtb; + return 0; + +failed: + vfree(dtb); + return ret; +} + +static ssize_t ready_show(struct device *dev, + struct device_attribute *da, + char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct xmgmt *xm = pci_get_drvdata(pdev); + + return sprintf(buf, "%d\n", xm->ready); +} +static DEVICE_ATTR_RO(ready); + +static struct attribute *xmgmt_root_attrs[] = { + &dev_attr_ready.attr, + NULL +}; + +static struct attribute_group xmgmt_root_attr_group = { + .attrs = xmgmt_root_attrs, +}; + +static void xmgmt_root_get_id(struct device *dev, struct xrt_root_get_id *rid) +{ + struct pci_dev *pdev = to_pci_dev(dev); + + rid->xpigi_vendor_id = pdev->vendor; + rid->xpigi_device_id = pdev->device; + rid->xpigi_sub_vendor_id = pdev->subsystem_vendor; + rid->xpigi_sub_device_id = pdev->subsystem_device; +} + +static int xmgmt_root_get_resource(struct device *dev, struct xrt_root_get_res *res) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct xmgmt *xm; + + xm = pci_get_drvdata(pdev); + if (res->xpigr_region_id > PCI_STD_RESOURCE_END) { + xmgmt_err(xm, "Invalid bar idx %d", res->xpigr_region_id); + return -EINVAL; + } + + res->xpigr_res = &pdev->resource[res->xpigr_region_id]; + return 0; +} + +static struct xroot_physical_function_callback xmgmt_xroot_pf_cb = { + .xpc_get_id = xmgmt_root_get_id, + .xpc_get_resource = xmgmt_root_get_resource, + .xpc_hot_reset = xmgmt_root_hot_reset, +}; + +static int xmgmt_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + int ret; + struct device *dev = &pdev->dev; + struct xmgmt *xm = devm_kzalloc(dev, sizeof(*xm), GFP_KERNEL); + char *dtb = NULL; + + if (!xm) + return -ENOMEM; + xm->pdev = pdev; + pci_set_drvdata(pdev, xm); + + ret = xmgmt_config_pci(xm); + if (ret) + goto failed; + + ret = xroot_probe(&pdev->dev, &xmgmt_xroot_pf_cb, &xm->root); + if (ret) + goto failed; + + ret = xmgmt_create_root_metadata(xm, &dtb); + if (ret) + goto failed_metadata; + + ret = xroot_create_group(xm->root, dtb); + vfree(dtb); + if (ret) + xmgmt_err(xm, "failed to create root group: %d", ret); + + if (!xroot_wait_for_bringup(xm->root)) + xmgmt_err(xm, "failed to bringup all groups"); + else + xm->ready = true; + + ret = sysfs_create_group(&pdev->dev.kobj, &xmgmt_root_attr_group); + if (ret) { + /* Warning instead of failing the probe. */ + xmgmt_warn(xm, "create xmgmt root attrs failed: %d", ret); + } + + xroot_broadcast(xm->root, XRT_EVENT_POST_CREATION); + xmgmt_info(xm, "%s started successfully", XMGMT_MODULE_NAME); + return 0; + +failed_metadata: + xroot_remove(xm->root); +failed: + pci_set_drvdata(pdev, NULL); + return ret; +} + +static void xmgmt_remove(struct pci_dev *pdev) +{ + struct xmgmt *xm = pci_get_drvdata(pdev); + + xroot_broadcast(xm->root, XRT_EVENT_PRE_REMOVAL); + sysfs_remove_group(&pdev->dev.kobj, &xmgmt_root_attr_group); + xroot_remove(xm->root); + pci_disable_pcie_error_reporting(xm->pdev); + xmgmt_info(xm, "%s cleaned up successfully", XMGMT_MODULE_NAME); +} + +static struct pci_driver xmgmt_driver = { + .name = XMGMT_MODULE_NAME, + .id_table = xmgmt_pci_ids, + .probe = xmgmt_probe, + .remove = xmgmt_remove, +}; + +static int __init xmgmt_init(void) +{ + int res = 0; + + res = xmgmt_register_leaf(); + if (res) + return res; + + xmgmt_class = class_create(THIS_MODULE, XMGMT_MODULE_NAME); + if (IS_ERR(xmgmt_class)) + return PTR_ERR(xmgmt_class); + + res = pci_register_driver(&xmgmt_driver); + if (res) { + class_destroy(xmgmt_class); + return res; + } + + return 0; +} + +static __exit void xmgmt_exit(void) +{ + pci_unregister_driver(&xmgmt_driver); + class_destroy(xmgmt_class); + xmgmt_unregister_leaf(); +} + +module_init(xmgmt_init); +module_exit(xmgmt_exit); + +MODULE_DEVICE_TABLE(pci, xmgmt_pci_ids); +MODULE_VERSION(XMGMT_DRIVER_VERSION); +MODULE_AUTHOR("XRT Team "); +MODULE_DESCRIPTION("Xilinx Alveo management function driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri May 28 00:49:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 449618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D597C4708B for ; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(376002)(136003)(39850400004)(396003)(346002)(46966006)(36840700001)(107886003)(2616005)(70206006)(26005)(6266002)(42186006)(1076003)(356005)(6666004)(82740400003)(44832011)(70586007)(83380400001)(316002)(8936002)(54906003)(4326008)(8676002)(36860700001)(5660300002)(478600001)(2906002)(30864003)(82310400003)(7636003)(336012)(186003)(36756003)(6916009)(47076005)(426003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 00:52:36.7642 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb8d3392-a9e9-46a7-18c7-08d92172e306 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0014.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2721 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org fpga-mgr and region implementation for xclbin download which will be called from main xrt driver Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reviewed-by: Tom Rix --- drivers/fpga/xrt/mgmt/xmgmt-main-region.c | 483 ++++++++++++++++++++++ drivers/fpga/xrt/mgmt/xrt-mgr.c | 190 +++++++++ drivers/fpga/xrt/mgmt/xrt-mgr.h | 16 + 3 files changed, 689 insertions(+) create mode 100644 drivers/fpga/xrt/mgmt/xmgmt-main-region.c create mode 100644 drivers/fpga/xrt/mgmt/xrt-mgr.c create mode 100644 drivers/fpga/xrt/mgmt/xrt-mgr.h diff --git a/drivers/fpga/xrt/mgmt/xmgmt-main-region.c b/drivers/fpga/xrt/mgmt/xmgmt-main-region.c new file mode 100644 index 000000000000..6e6a16b13258 --- /dev/null +++ b/drivers/fpga/xrt/mgmt/xmgmt-main-region.c @@ -0,0 +1,483 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * FPGA Region Support for Xilinx Alveo + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: Lizhi.Hou@xilinx.com + */ + +#include +#include +#include +#include +#include "metadata.h" +#include "xleaf.h" +#include "xleaf/axigate.h" +#include "xclbin-helper.h" +#include "xmgmt.h" + +struct xmgmt_bridge { + struct xrt_device *xdev; + const char *bridge_name; +}; + +struct xmgmt_region { + struct xrt_device *xdev; + struct fpga_region *region; + struct fpga_compat_id compat_id; + uuid_t interface_uuid; + struct fpga_bridge *bridge; + int group_instance; + uuid_t depend_uuid; + struct list_head list; +}; + +struct xmgmt_region_match_arg { + struct xrt_device *xdev; + uuid_t *uuids; + u32 uuid_num; +}; + +static int xmgmt_br_enable_set(struct fpga_bridge *bridge, bool enable) +{ + struct xmgmt_bridge *br_data = (struct xmgmt_bridge *)bridge->priv; + struct xrt_device *axigate_leaf; + int rc; + + axigate_leaf = xleaf_get_leaf_by_epname(br_data->xdev, br_data->bridge_name); + if (!axigate_leaf) { + xrt_err(br_data->xdev, "failed to get leaf %s", + br_data->bridge_name); + return -ENOENT; + } + + if (enable) + rc = xleaf_call(axigate_leaf, XRT_AXIGATE_OPEN, NULL); + else + rc = xleaf_call(axigate_leaf, XRT_AXIGATE_CLOSE, NULL); + + if (rc) { + xrt_err(br_data->xdev, "failed to %s gate %s, rc %d", + (enable ? "free" : "freeze"), br_data->bridge_name, + rc); + } + + xleaf_put_leaf(br_data->xdev, axigate_leaf); + + return rc; +} + +static const struct fpga_bridge_ops xmgmt_bridge_ops = { + .enable_set = xmgmt_br_enable_set +}; + +static void xmgmt_destroy_bridge(struct fpga_bridge *br) +{ + struct xmgmt_bridge *br_data = br->priv; + + if (!br_data) + return; + + xrt_info(br_data->xdev, "destroy fpga bridge %s", br_data->bridge_name); + fpga_bridge_unregister(br); + + devm_kfree(DEV(br_data->xdev), br_data); + + fpga_bridge_free(br); +} + +static struct fpga_bridge *xmgmt_create_bridge(struct xrt_device *xdev, + char *dtb) +{ + struct fpga_bridge *br = NULL; + struct xmgmt_bridge *br_data; + const char *gate; + int rc; + + br_data = devm_kzalloc(DEV(xdev), sizeof(*br_data), GFP_KERNEL); + if (!br_data) + return NULL; + br_data->xdev = xdev; + + br_data->bridge_name = XRT_MD_NODE_GATE_ULP; + rc = xrt_md_find_endpoint(&xdev->dev, dtb, XRT_MD_NODE_GATE_ULP, + NULL, &gate); + if (rc) { + br_data->bridge_name = XRT_MD_NODE_GATE_PLP; + rc = xrt_md_find_endpoint(&xdev->dev, dtb, XRT_MD_NODE_GATE_PLP, + NULL, &gate); + } + if (rc) { + xrt_err(xdev, "failed to get axigate, rc %d", rc); + goto failed; + } + + br = fpga_bridge_create(DEV(xdev), br_data->bridge_name, + &xmgmt_bridge_ops, br_data); + if (!br) { + xrt_err(xdev, "failed to create bridge"); + goto failed; + } + + rc = fpga_bridge_register(br); + if (rc) { + xrt_err(xdev, "failed to register bridge, rc %d", rc); + goto failed; + } + + xrt_info(xdev, "created fpga bridge %s", br_data->bridge_name); + + return br; + +failed: + if (br) + fpga_bridge_free(br); + if (br_data) + devm_kfree(DEV(xdev), br_data); + + return NULL; +} + +static void xmgmt_destroy_region(struct fpga_region *region) +{ + struct xmgmt_region *r_data = region->priv; + + xrt_info(r_data->xdev, "destroy fpga region %llx.%llx", + region->compat_id->id_h, region->compat_id->id_l); + + fpga_region_unregister(region); + + if (r_data->group_instance > 0) + xleaf_destroy_group(r_data->xdev, r_data->group_instance); + + if (r_data->bridge) + xmgmt_destroy_bridge(r_data->bridge); + + if (r_data->region->info) { + fpga_image_info_free(r_data->region->info); + r_data->region->info = NULL; + } + + fpga_region_free(region); + + devm_kfree(DEV(r_data->xdev), r_data); +} + +static int xmgmt_region_match(struct device *dev, const void *data) +{ + const struct xmgmt_region_match_arg *arg = data; + const struct fpga_region *match_region; + uuid_t compat_uuid; + int i; + + if (dev->parent != &arg->xdev->dev) + return false; + + match_region = to_fpga_region(dev); + /* + * The device tree provides both parent and child uuids for an + * xclbin in one array. Here we try both uuids to see if it matches + * with target region's compat_id. Strictly speaking we should + * only match xclbin's parent uuid with target region's compat_id + * but given the uuids by design are unique comparing with both + * does not hurt. + */ + import_uuid(&compat_uuid, (const char *)match_region->compat_id); + for (i = 0; i < arg->uuid_num; i++) { + if (uuid_equal(&compat_uuid, &arg->uuids[i])) + return true; + } + + return false; +} + +static int xmgmt_region_match_base(struct device *dev, const void *data) +{ + const struct xmgmt_region_match_arg *arg = data; + const struct fpga_region *match_region; + const struct xmgmt_region *r_data; + + if (dev->parent != &arg->xdev->dev) + return false; + + match_region = to_fpga_region(dev); + r_data = match_region->priv; + if (uuid_is_null(&r_data->depend_uuid)) + return true; + + return false; +} + +static int xmgmt_region_match_by_uuid(struct device *dev, const void *data) +{ + const struct xmgmt_region_match_arg *arg = data; + const struct fpga_region *match_region; + const struct xmgmt_region *r_data; + + if (dev->parent != &arg->xdev->dev) + return false; + + if (arg->uuid_num != 1) + return false; + + match_region = to_fpga_region(dev); + r_data = match_region->priv; + if (uuid_equal(&r_data->depend_uuid, arg->uuids)) + return true; + + return false; +} + +static void xmgmt_region_cleanup(struct fpga_region *region) +{ + struct xmgmt_region *r_data = region->priv, *pdata, *temp; + struct xrt_device *xdev = r_data->xdev; + struct xmgmt_region_match_arg arg = { 0 }; + struct fpga_region *match_region = NULL; + struct device *start_dev = NULL; + LIST_HEAD(free_list); + uuid_t compat_uuid; + + list_add_tail(&r_data->list, &free_list); + arg.xdev = xdev; + arg.uuid_num = 1; + arg.uuids = &compat_uuid; + + /* find all regions depending on this region */ + list_for_each_entry_safe(pdata, temp, &free_list, list) { + import_uuid(arg.uuids, (const char *)pdata->region->compat_id); + start_dev = NULL; + while ((match_region = fpga_region_class_find(start_dev, &arg, + xmgmt_region_match_by_uuid))) { + pdata = match_region->priv; + list_add_tail(&pdata->list, &free_list); + start_dev = &match_region->dev; + put_device(&match_region->dev); + } + } + + list_del(&r_data->list); + + list_for_each_entry_safe_reverse(pdata, temp, &free_list, list) + xmgmt_destroy_region(pdata->region); + + if (r_data->group_instance > 0) { + xleaf_destroy_group(xdev, r_data->group_instance); + r_data->group_instance = -1; + } + if (r_data->region->info) { + fpga_image_info_free(r_data->region->info); + r_data->region->info = NULL; + } +} + +void xmgmt_region_cleanup_all(struct xrt_device *xdev) +{ + struct xmgmt_region_match_arg arg = { 0 }; + struct fpga_region *base_region; + + arg.xdev = xdev; + + while ((base_region = fpga_region_class_find(NULL, &arg, xmgmt_region_match_base))) { + put_device(&base_region->dev); + + xmgmt_region_cleanup(base_region); + xmgmt_destroy_region(base_region); + } +} + +/* + * Program a region with a xclbin image. Bring up the subdevs and the + * group object to contain the subdevs. + */ +static int xmgmt_region_program(struct fpga_region *region, const void *xclbin, char *dtb) +{ + const struct axlf *xclbin_obj = xclbin; + struct fpga_image_info *info; + struct xrt_device *xdev; + struct xmgmt_region *r_data; + int rc; + + r_data = region->priv; + xdev = r_data->xdev; + + info = fpga_image_info_alloc(&xdev->dev); + if (!info) + return -ENOMEM; + + info->buf = xclbin; + info->count = xclbin_obj->header.length; + info->flags |= FPGA_MGR_PARTIAL_RECONFIG; + region->info = info; + rc = fpga_region_program_fpga(region); + if (rc) { + xrt_err(xdev, "programming xclbin failed, rc %d", rc); + return rc; + } + + /* free bridges to allow reprogram */ + if (region->get_bridges) + fpga_bridges_put(®ion->bridge_list); + + /* + * Next bringup the subdevs for this region which will be managed by + * its own group object. + */ + r_data->group_instance = xleaf_create_group(xdev, dtb); + if (r_data->group_instance < 0) { + xrt_err(xdev, "failed to create group, rc %d", + r_data->group_instance); + rc = r_data->group_instance; + return rc; + } + + rc = xleaf_wait_for_group_bringup(xdev); + if (rc) + xrt_err(xdev, "group bringup failed, rc %d", rc); + return rc; +} + +static int xmgmt_get_bridges(struct fpga_region *region) +{ + struct xmgmt_region *r_data = region->priv; + struct device *dev = &r_data->xdev->dev; + + return fpga_bridge_get_to_list(dev, region->info, ®ion->bridge_list); +} + +/* + * Program/create FPGA regions based on input xclbin file. + * 1. Identify a matching existing region for this xclbin + * 2. Tear down any previous objects for the found region + * 3. Program this region with input xclbin + * 4. Iterate over this region's interface uuids to determine if it defines any + * child region. Create fpga_region for the child region. + */ +int xmgmt_process_xclbin(struct xrt_device *xdev, + struct fpga_manager *fmgr, + const struct axlf *xclbin, + enum provider_kind kind) +{ + struct fpga_region *region, *compat_region = NULL; + struct xmgmt_region_match_arg arg = { 0 }; + struct xmgmt_region *r_data; + uuid_t compat_uuid; + char *dtb = NULL; + int rc, i; + + rc = xrt_xclbin_get_metadata(DEV(xdev), xclbin, &dtb); + if (rc) { + xrt_err(xdev, "failed to get dtb: %d", rc); + goto failed; + } + + rc = xrt_md_get_interface_uuids(DEV(xdev), dtb, 0, NULL); + if (rc < 0) { + xrt_err(xdev, "failed to get intf uuid"); + rc = -EINVAL; + goto failed; + } + arg.uuid_num = rc; + arg.uuids = kcalloc(arg.uuid_num, sizeof(uuid_t), GFP_KERNEL); + if (!arg.uuids) { + rc = -ENOMEM; + goto failed; + } + arg.xdev = xdev; + + rc = xrt_md_get_interface_uuids(DEV(xdev), dtb, arg.uuid_num, arg.uuids); + if (rc != arg.uuid_num) { + xrt_err(xdev, "only get %d uuids, expect %d", rc, arg.uuid_num); + rc = -EINVAL; + goto failed; + } + + /* if this is not base firmware, search for a compatible region */ + if (kind != XMGMT_BLP) { + compat_region = fpga_region_class_find(NULL, &arg, xmgmt_region_match); + if (!compat_region) { + xrt_err(xdev, "failed to get compatible region"); + rc = -ENOENT; + goto failed; + } + + xmgmt_region_cleanup(compat_region); + + rc = xmgmt_region_program(compat_region, xclbin, dtb); + if (rc) { + xrt_err(xdev, "failed to program region"); + goto failed; + } + } + + if (compat_region) + import_uuid(&compat_uuid, (const char *)compat_region->compat_id); + + /* create all the new regions contained in this xclbin */ + for (i = 0; i < arg.uuid_num; i++) { + if (compat_region && uuid_equal(&compat_uuid, &arg.uuids[i])) { + /* region for this interface already exists */ + continue; + } + + region = fpga_region_create(DEV(xdev), fmgr, xmgmt_get_bridges); + if (!region) { + xrt_err(xdev, "failed to create fpga region"); + rc = -EFAULT; + goto failed; + } + r_data = devm_kzalloc(DEV(xdev), sizeof(*r_data), GFP_KERNEL); + if (!r_data) { + rc = -ENOMEM; + fpga_region_free(region); + goto failed; + } + r_data->xdev = xdev; + r_data->region = region; + r_data->group_instance = -1; + uuid_copy(&r_data->interface_uuid, &arg.uuids[i]); + if (compat_region) + import_uuid(&r_data->depend_uuid, (const char *)compat_region->compat_id); + r_data->bridge = xmgmt_create_bridge(xdev, dtb); + if (!r_data->bridge) { + xrt_err(xdev, "failed to create fpga bridge"); + rc = -EFAULT; + devm_kfree(DEV(xdev), r_data); + fpga_region_free(region); + goto failed; + } + + region->compat_id = &r_data->compat_id; + export_uuid((char *)region->compat_id, &r_data->interface_uuid); + region->priv = r_data; + + rc = fpga_region_register(region); + if (rc) { + xrt_err(xdev, "failed to register fpga region"); + xmgmt_destroy_bridge(r_data->bridge); + fpga_region_free(region); + devm_kfree(DEV(xdev), r_data); + goto failed; + } + + xrt_info(xdev, "created fpga region %llx.%llx", + region->compat_id->id_h, region->compat_id->id_l); + } + + if (compat_region) + put_device(&compat_region->dev); + vfree(dtb); + kfree(arg.uuids); + return 0; + +failed: + if (compat_region) { + put_device(&compat_region->dev); + xmgmt_region_cleanup(compat_region); + } + + vfree(dtb); + kfree(arg.uuids); + return rc; +} diff --git a/drivers/fpga/xrt/mgmt/xrt-mgr.c b/drivers/fpga/xrt/mgmt/xrt-mgr.c new file mode 100644 index 000000000000..41263a033d9d --- /dev/null +++ b/drivers/fpga/xrt/mgmt/xrt-mgr.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * FPGA Manager Support for Xilinx Alveo + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: Sonal.Santan@xilinx.com + */ + +#include +#include +#include +#include +#include + +#include "xclbin-helper.h" +#include "xleaf.h" +#include "xrt-mgr.h" +#include "xleaf/axigate.h" +#include "xleaf/icap.h" +#include "xmgmt.h" + +struct xfpga_class { + struct xrt_device *xdev; + char name[64]; +}; + +/* + * xclbin download plumbing -- find the download subsystem, ICAP and + * pass the xclbin for heavy lifting + */ +static int xmgmt_download_bitstream(struct xrt_device *xdev, + const struct axlf *xclbin) + +{ + struct xclbin_bit_head_info bit_header = { 0 }; + struct xrt_device *icap_leaf = NULL; + struct xrt_icap_wr arg; + char *bitstream = NULL; + u64 bit_len; + int ret; + + ret = xrt_xclbin_get_section(DEV(xdev), xclbin, BITSTREAM, (void **)&bitstream, &bit_len); + if (ret) { + xrt_err(xdev, "bitstream not found"); + return -ENOENT; + } + ret = xrt_xclbin_parse_bitstream_header(DEV(xdev), bitstream, + XCLBIN_HWICAP_BITFILE_BUF_SZ, + &bit_header); + if (ret) { + ret = -EINVAL; + xrt_err(xdev, "invalid bitstream header"); + goto fail; + } + if (bit_header.header_length + bit_header.bitstream_length > bit_len) { + ret = -EINVAL; + xrt_err(xdev, "invalid bitstream length. header %d, bitstream %d, section len %lld", + bit_header.header_length, bit_header.bitstream_length, bit_len); + goto fail; + } + + icap_leaf = xleaf_get_leaf_by_id(xdev, XRT_SUBDEV_ICAP, XRT_INVALID_DEVICE_INST); + if (!icap_leaf) { + ret = -ENODEV; + xrt_err(xdev, "icap does not exist"); + goto fail; + } + arg.xiiw_bit_data = bitstream + bit_header.header_length; + arg.xiiw_data_len = bit_header.bitstream_length; + ret = xleaf_call(icap_leaf, XRT_ICAP_WRITE, &arg); + if (ret) { + xrt_err(xdev, "write bitstream failed, ret = %d", ret); + xleaf_put_leaf(xdev, icap_leaf); + goto fail; + } + + xleaf_put_leaf(xdev, icap_leaf); + vfree(bitstream); + + return 0; + +fail: + vfree(bitstream); + + return ret; +} + +/* + * There is no HW prep work we do here since we need the full + * xclbin for its sanity check. + */ +static int xmgmt_pr_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + const struct axlf *bin = (const struct axlf *)buf; + struct xfpga_class *obj = mgr->priv; + + if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { + xrt_info(obj->xdev, "%s only supports partial reconfiguration\n", obj->name); + return -EINVAL; + } + + if (count < sizeof(struct axlf)) + return -EINVAL; + + if (count > bin->header.length) + return -EINVAL; + + xrt_info(obj->xdev, "Prepare download of xclbin %pUb of length %lld B", + &bin->header.uuid, bin->header.length); + + return 0; +} + +/* + * The implementation requries full xclbin image before we can start + * programming the hardware via ICAP subsystem. The full image is required + * for checking the validity of xclbin and walking the sections to + * discover the bitstream. + */ +static int xmgmt_pr_write(struct fpga_manager *mgr, + const char *buf, size_t count) +{ + const struct axlf *bin = (const struct axlf *)buf; + struct xfpga_class *obj = mgr->priv; + + if (bin->header.length != count) + return -EINVAL; + + return xmgmt_download_bitstream((void *)obj->xdev, bin); +} + +static int xmgmt_pr_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + const struct axlf *bin = (const struct axlf *)info->buf; + struct xfpga_class *obj = mgr->priv; + + xrt_info(obj->xdev, "Finished download of xclbin %pUb", + &bin->header.uuid); + return 0; +} + +static enum fpga_mgr_states xmgmt_pr_state(struct fpga_manager *mgr) +{ + return FPGA_MGR_STATE_UNKNOWN; +} + +static const struct fpga_manager_ops xmgmt_pr_ops = { + .initial_header_size = sizeof(struct axlf), + .write_init = xmgmt_pr_write_init, + .write = xmgmt_pr_write, + .write_complete = xmgmt_pr_write_complete, + .state = xmgmt_pr_state, +}; + +struct fpga_manager *xmgmt_fmgr_probe(struct xrt_device *xdev) +{ + struct xfpga_class *obj = devm_kzalloc(DEV(xdev), sizeof(struct xfpga_class), + GFP_KERNEL); + struct fpga_manager *fmgr = NULL; + int ret = 0; + + if (!obj) + return ERR_PTR(-ENOMEM); + + snprintf(obj->name, sizeof(obj->name), "Xilinx Alveo FPGA Manager"); + obj->xdev = xdev; + fmgr = fpga_mgr_create(&xdev->dev, + obj->name, + &xmgmt_pr_ops, + obj); + if (!fmgr) + return ERR_PTR(-ENOMEM); + + ret = fpga_mgr_register(fmgr); + if (ret) { + fpga_mgr_free(fmgr); + return ERR_PTR(ret); + } + return fmgr; +} + +int xmgmt_fmgr_remove(struct fpga_manager *fmgr) +{ + fpga_mgr_unregister(fmgr); + return 0; +} diff --git a/drivers/fpga/xrt/mgmt/xrt-mgr.h b/drivers/fpga/xrt/mgmt/xrt-mgr.h new file mode 100644 index 000000000000..a3d1ab1c34f0 --- /dev/null +++ b/drivers/fpga/xrt/mgmt/xrt-mgr.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: Sonal.Santan@xilinx.com + */ + +#ifndef _XRT_MGR_H_ +#define _XRT_MGR_H_ + +#include + +struct fpga_manager *xmgmt_fmgr_probe(struct xrt_device *xdev); +int xmgmt_fmgr_remove(struct fpga_manager *fmgr); + +#endif /* _XRT_MGR_H_ */ From patchwork Fri May 28 00:49:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 449617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74A21C47089 for ; Fri, 28 May 2021 00:53:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 55ABE613AF for ; Fri, 28 May 2021 00:53:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235841AbhE1Ayf (ORCPT ); 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Thu, 27 May 2021 17:52:44 -0700 Envelope-to: mdf@kernel.org, robh@kernel.org, trix@redhat.com, devicetree@vger.kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.19.73.109] (port=34032 helo=xsj-xw9400.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lmQk0-0007Ia-2p; Thu, 27 May 2021 17:52:44 -0700 Received: by xsj-xw9400.xilinx.com (Postfix, from userid 21952) id E9EF66032AF; Thu, 27 May 2021 17:50:06 -0700 (PDT) From: Lizhi Hou To: CC: Lizhi Hou , , , , , , , , , , , Max Zhen Subject: [PATCH V7 XRT Alveo 13/20] fpga: xrt: User Clock Subsystem driver Date: Thu, 27 May 2021 17:49:52 -0700 Message-ID: <20210528004959.61354-14-lizhi.hou@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210528004959.61354-1-lizhi.hou@xilinx.com> References: <20210528004959.61354-1-lizhi.hou@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1e6fb282-7c51-4c26-3302-08d92172ef13 X-MS-TrafficTypeDiagnostic: DM6PR02MB6396: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2399; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 00:52:56.9827 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e6fb282-7c51-4c26-3302-08d92172ef13 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0056.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6396 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add User Clock Subsystem (UCS) driver. UCS is a hardware function discovered by walking xclbin metadata. A xrt device node will be created for it. UCS enables/disables the dynamic region clocks. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reviewed-by: Tom Rix --- drivers/fpga/xrt/lib/xleaf/ucs.c | 152 +++++++++++++++++++++++++++++++ 1 file changed, 152 insertions(+) create mode 100644 drivers/fpga/xrt/lib/xleaf/ucs.c diff --git a/drivers/fpga/xrt/lib/xleaf/ucs.c b/drivers/fpga/xrt/lib/xleaf/ucs.c new file mode 100644 index 000000000000..a7a96ddde44f --- /dev/null +++ b/drivers/fpga/xrt/lib/xleaf/ucs.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo FPGA UCS Driver + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#include +#include +#include +#include +#include +#include "metadata.h" +#include "xleaf.h" +#include "xleaf/clock.h" + +#define UCS_ERR(ucs, fmt, arg...) \ + xrt_err((ucs)->xdev, fmt "\n", ##arg) +#define UCS_WARN(ucs, fmt, arg...) \ + xrt_warn((ucs)->xdev, fmt "\n", ##arg) +#define UCS_INFO(ucs, fmt, arg...) \ + xrt_info((ucs)->xdev, fmt "\n", ##arg) +#define UCS_DBG(ucs, fmt, arg...) \ + xrt_dbg((ucs)->xdev, fmt "\n", ##arg) + +#define XRT_UCS "xrt_ucs" + +#define XRT_UCS_CHANNEL1_REG 0 +#define XRT_UCS_CHANNEL2_REG 8 + +#define CLK_MAX_VALUE 6400 + +XRT_DEFINE_REGMAP_CONFIG(ucs_regmap_config); + +struct xrt_ucs { + struct xrt_device *xdev; + struct regmap *regmap; + struct mutex ucs_lock; /* ucs dev lock */ +}; + +static void xrt_ucs_event_cb(struct xrt_device *xdev, void *arg) +{ + struct xrt_event *evt = (struct xrt_event *)arg; + enum xrt_events e = evt->xe_evt; + struct xrt_device *leaf; + enum xrt_subdev_id id; + int instance; + + id = evt->xe_subdev.xevt_subdev_id; + instance = evt->xe_subdev.xevt_subdev_instance; + + if (e != XRT_EVENT_POST_CREATION) { + xrt_dbg(xdev, "ignored event %d", e); + return; + } + + if (id != XRT_SUBDEV_CLOCK) + return; + + leaf = xleaf_get_leaf_by_id(xdev, XRT_SUBDEV_CLOCK, instance); + if (!leaf) { + xrt_err(xdev, "does not get clock subdev"); + return; + } + + xleaf_call(leaf, XRT_CLOCK_VERIFY, NULL); + xleaf_put_leaf(xdev, leaf); +} + +static int ucs_enable(struct xrt_ucs *ucs) +{ + int ret; + + mutex_lock(&ucs->ucs_lock); + ret = regmap_write(ucs->regmap, XRT_UCS_CHANNEL2_REG, 1); + mutex_unlock(&ucs->ucs_lock); + + return ret; +} + +static int +xrt_ucs_leaf_call(struct xrt_device *xdev, u32 cmd, void *arg) +{ + switch (cmd) { + case XRT_XLEAF_EVENT: + xrt_ucs_event_cb(xdev, arg); + break; + default: + xrt_err(xdev, "unsupported cmd %d", cmd); + return -EINVAL; + } + + return 0; +} + +static int ucs_probe(struct xrt_device *xdev) +{ + struct xrt_ucs *ucs = NULL; + void __iomem *base = NULL; + struct resource *res; + + ucs = devm_kzalloc(&xdev->dev, sizeof(*ucs), GFP_KERNEL); + if (!ucs) + return -ENOMEM; + + xrt_set_drvdata(xdev, ucs); + ucs->xdev = xdev; + mutex_init(&ucs->ucs_lock); + + res = xrt_get_resource(xdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + base = devm_ioremap_resource(&xdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + ucs->regmap = devm_regmap_init_mmio(&xdev->dev, base, &ucs_regmap_config); + if (IS_ERR(ucs->regmap)) { + UCS_ERR(ucs, "map base %pR failed", res); + return PTR_ERR(ucs->regmap); + } + ucs_enable(ucs); + + return 0; +} + +static struct xrt_dev_endpoints xrt_ucs_endpoints[] = { + { + .xse_names = (struct xrt_dev_ep_names[]) { + { .ep_name = XRT_MD_NODE_UCS_CONTROL_STATUS }, + { NULL }, + }, + .xse_min_ep = 1, + }, + { 0 }, +}; + +static struct xrt_driver xrt_ucs_driver = { + .driver = { + .name = XRT_UCS, + }, + .subdev_id = XRT_SUBDEV_UCS, + .endpoints = xrt_ucs_endpoints, + .probe = ucs_probe, + .leaf_call = xrt_ucs_leaf_call, +}; + +XRT_LEAF_INIT_FINI_FUNC(ucs); From patchwork Fri May 28 00:49:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 449616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6FE0C47089 for ; Fri, 28 May 2021 00:53:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9EFE613AF for ; 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PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(346002)(136003)(396003)(376002)(39850400004)(36840700001)(46966006)(2906002)(2616005)(6266002)(107886003)(186003)(316002)(54906003)(478600001)(5660300002)(26005)(426003)(47076005)(966005)(83380400001)(6666004)(82740400003)(36756003)(8936002)(42186006)(6916009)(82310400003)(4326008)(356005)(70586007)(7636003)(70206006)(1076003)(336012)(8676002)(36860700001)(44832011); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 00:53:21.1886 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d1fd9af-ff3c-4ac9-91d9-08d92172fd80 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0062.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5033 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ICAP stands for Hardware Internal Configuration Access Port. ICAP is discovered by walking the firmware metadata. A xrt device node will be created for it. FPGA bitstream is written to hardware through ICAP. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reviewed-by: Tom Rix --- drivers/fpga/xrt/include/xleaf/icap.h | 27 +++ drivers/fpga/xrt/lib/xleaf/icap.c | 328 ++++++++++++++++++++++++++ 2 files changed, 355 insertions(+) create mode 100644 drivers/fpga/xrt/include/xleaf/icap.h create mode 100644 drivers/fpga/xrt/lib/xleaf/icap.c diff --git a/drivers/fpga/xrt/include/xleaf/icap.h b/drivers/fpga/xrt/include/xleaf/icap.h new file mode 100644 index 000000000000..96d39a8934fa --- /dev/null +++ b/drivers/fpga/xrt/include/xleaf/icap.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#ifndef _XRT_ICAP_H_ +#define _XRT_ICAP_H_ + +#include "xleaf.h" + +/* + * ICAP driver leaf calls. + */ +enum xrt_icap_leaf_cmd { + XRT_ICAP_WRITE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ + XRT_ICAP_GET_IDCODE, +}; + +struct xrt_icap_wr { + void *xiiw_bit_data; + u32 xiiw_data_len; +}; + +#endif /* _XRT_ICAP_H_ */ diff --git a/drivers/fpga/xrt/lib/xleaf/icap.c b/drivers/fpga/xrt/lib/xleaf/icap.c new file mode 100644 index 000000000000..071923f61537 --- /dev/null +++ b/drivers/fpga/xrt/lib/xleaf/icap.c @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo FPGA ICAP Driver + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + * Sonal Santan + * Max Zhen + */ + +#include +#include +#include +#include +#include +#include "metadata.h" +#include "xleaf.h" +#include "xleaf/icap.h" +#include "xclbin-helper.h" + +#define XRT_ICAP "xrt_icap" + +#define ICAP_ERR(icap, fmt, arg...) \ + xrt_err((icap)->xdev, fmt "\n", ##arg) +#define ICAP_WARN(icap, fmt, arg...) \ + xrt_warn((icap)->xdev, fmt "\n", ##arg) +#define ICAP_INFO(icap, fmt, arg...) \ + xrt_info((icap)->xdev, fmt "\n", ##arg) +#define ICAP_DBG(icap, fmt, arg...) \ + xrt_dbg((icap)->xdev, fmt "\n", ##arg) + +/* + * AXI-HWICAP IP register layout. Please see + * https://www.xilinx.com/support/documentation/ip_documentation/axi_hwicap/v3_0/pg134-axi-hwicap.pdf + */ +#define ICAP_REG_GIER 0x1C +#define ICAP_REG_ISR 0x20 +#define ICAP_REG_IER 0x28 +#define ICAP_REG_WF 0x100 +#define ICAP_REG_RF 0x104 +#define ICAP_REG_SZ 0x108 +#define ICAP_REG_CR 0x10C +#define ICAP_REG_SR 0x110 +#define ICAP_REG_WFV 0x114 +#define ICAP_REG_RFO 0x118 +#define ICAP_REG_ASR 0x11C + +#define ICAP_STATUS_EOS 0x4 +#define ICAP_STATUS_DONE 0x1 + +/* + * Canned command sequence to obtain IDCODE of the FPGA + */ +static const __be32 idcode_stream[] = { + /* dummy word */ + cpu_to_be32(0xffffffff), + /* sync word */ + cpu_to_be32(0xaa995566), + /* NOP word */ + cpu_to_be32(0x20000000), + /* NOP word */ + cpu_to_be32(0x20000000), + /* ID code */ + cpu_to_be32(0x28018001), + /* NOP word */ + cpu_to_be32(0x20000000), + /* NOP word */ + cpu_to_be32(0x20000000), +}; + +XRT_DEFINE_REGMAP_CONFIG(icap_regmap_config); + +struct icap { + struct xrt_device *xdev; + struct regmap *regmap; + struct mutex icap_lock; /* icap dev lock */ + u32 idcode; +}; + +static int wait_for_done(const struct icap *icap) +{ + int i = 0; + int ret; + u32 w; + + for (i = 0; i < 10; i++) { + /* + * it requires few micro seconds for ICAP to process incoming data. + * Polling every 5us for 10 times would be good enough. + */ + udelay(5); + ret = regmap_read(icap->regmap, ICAP_REG_SR, &w); + if (ret) + return ret; + ICAP_INFO(icap, "XHWICAP_SR: %x", w); + if (w & (ICAP_STATUS_EOS | ICAP_STATUS_DONE)) + return 0; + } + + ICAP_ERR(icap, "bitstream download timeout"); + return -ETIMEDOUT; +} + +static int icap_write(const struct icap *icap, const __be32 *word_buf, int size) +{ + u32 value = 0; + int ret; + int i; + + for (i = 0; i < size; i++) { + value = be32_to_cpu(word_buf[i]); + ret = regmap_write(icap->regmap, ICAP_REG_WF, value); + if (ret) + return ret; + } + + ret = regmap_write(icap->regmap, ICAP_REG_CR, 0x1); + if (ret) + return ret; + + for (i = 0; i < 20; i++) { + ret = regmap_read(icap->regmap, ICAP_REG_CR, &value); + if (ret) + return ret; + + if ((value & 0x1) == 0) + return 0; + ndelay(50); + } + + ICAP_ERR(icap, "writing %d dwords timeout", size); + return -EIO; +} + +static int bitstream_helper(struct icap *icap, const __be32 *word_buffer, + u32 word_count) +{ + int wr_fifo_vacancy = 0; + u32 word_written = 0; + u32 remain_word; + int err = 0; + + WARN_ON(!mutex_is_locked(&icap->icap_lock)); + for (remain_word = word_count; remain_word > 0; + remain_word -= word_written, word_buffer += word_written) { + err = regmap_read(icap->regmap, ICAP_REG_WFV, &wr_fifo_vacancy); + if (err) { + ICAP_ERR(icap, "read wr_fifo_vacancy failed %d", err); + break; + } + if (wr_fifo_vacancy <= 0) { + ICAP_ERR(icap, "no vacancy: %d", wr_fifo_vacancy); + err = -EIO; + break; + } + word_written = (wr_fifo_vacancy < remain_word) ? + wr_fifo_vacancy : remain_word; + if (icap_write(icap, word_buffer, word_written) != 0) { + ICAP_ERR(icap, "write failed remain %d, written %d", + remain_word, word_written); + err = -EIO; + break; + } + } + + return err; +} + +static int icap_download(struct icap *icap, const char *buffer, + unsigned long length) +{ + u32 num_chars_read = XCLBIN_HWICAP_BITFILE_BUF_SZ; + u32 byte_read; + int err = 0; + + if (length % sizeof(u32)) { + ICAP_ERR(icap, "invalid bitstream length %ld", length); + return -EINVAL; + } + + mutex_lock(&icap->icap_lock); + for (byte_read = 0; byte_read < length; byte_read += num_chars_read) { + num_chars_read = length - byte_read; + if (num_chars_read > XCLBIN_HWICAP_BITFILE_BUF_SZ) + num_chars_read = XCLBIN_HWICAP_BITFILE_BUF_SZ; + + err = bitstream_helper(icap, (__be32 *)buffer, num_chars_read / sizeof(u32)); + if (err) + goto failed; + buffer += num_chars_read; + } + + /* there is not any cleanup needs to be done if writing ICAP timeout. */ + err = wait_for_done(icap); + +failed: + mutex_unlock(&icap->icap_lock); + + return err; +} + +/* + * Discover the FPGA IDCODE using special sequence of canned commands + */ +static int icap_probe_chip(struct icap *icap) +{ + int err; + u32 val = 0; + + regmap_read(icap->regmap, ICAP_REG_SR, &val); + if (val != ICAP_STATUS_DONE) + return -ENODEV; + /* Read ICAP FIFO vacancy */ + regmap_read(icap->regmap, ICAP_REG_WFV, &val); + if (val < 8) + return -ENODEV; + err = icap_write(icap, idcode_stream, ARRAY_SIZE(idcode_stream)); + if (err) + return err; + err = wait_for_done(icap); + if (err) + return err; + + /* Tell config engine how many words to transfer to read FIFO */ + regmap_write(icap->regmap, ICAP_REG_SZ, 0x1); + /* Switch the ICAP to read mode */ + regmap_write(icap->regmap, ICAP_REG_CR, 0x2); + err = wait_for_done(icap); + if (err) + return err; + + /* Read IDCODE from Read FIFO */ + regmap_read(icap->regmap, ICAP_REG_RF, &icap->idcode); + return 0; +} + +static int +xrt_icap_leaf_call(struct xrt_device *xdev, u32 cmd, void *arg) +{ + struct xrt_icap_wr *wr_arg = arg; + struct icap *icap; + int ret = 0; + + icap = xrt_get_drvdata(xdev); + + switch (cmd) { + case XRT_XLEAF_EVENT: + /* Does not handle any event. */ + break; + case XRT_ICAP_WRITE: + ret = icap_download(icap, wr_arg->xiiw_bit_data, + wr_arg->xiiw_data_len); + break; + case XRT_ICAP_GET_IDCODE: + *(u32 *)arg = icap->idcode; + break; + default: + ICAP_ERR(icap, "unknown command %d", cmd); + return -EINVAL; + } + + return ret; +} + +static int xrt_icap_probe(struct xrt_device *xdev) +{ + void __iomem *base = NULL; + struct resource *res; + struct icap *icap; + int result = 0; + + icap = devm_kzalloc(&xdev->dev, sizeof(*icap), GFP_KERNEL); + if (!icap) + return -ENOMEM; + + icap->xdev = xdev; + xrt_set_drvdata(xdev, icap); + mutex_init(&icap->icap_lock); + + xrt_info(xdev, "probing"); + res = xrt_get_resource(xdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + base = devm_ioremap_resource(&xdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + icap->regmap = devm_regmap_init_mmio(&xdev->dev, base, &icap_regmap_config); + if (IS_ERR(icap->regmap)) { + ICAP_ERR(icap, "init mmio failed"); + return PTR_ERR(icap->regmap); + } + /* Disable ICAP interrupts */ + regmap_write(icap->regmap, ICAP_REG_GIER, 0); + + result = icap_probe_chip(icap); + if (result) + xrt_err(xdev, "Failed to probe FPGA"); + else + xrt_info(xdev, "Discovered FPGA IDCODE %x", icap->idcode); + return result; +} + +static struct xrt_dev_endpoints xrt_icap_endpoints[] = { + { + .xse_names = (struct xrt_dev_ep_names[]) { + { .ep_name = XRT_MD_NODE_FPGA_CONFIG }, + { NULL }, + }, + .xse_min_ep = 1, + }, + { 0 }, +}; + +static struct xrt_driver xrt_icap_driver = { + .driver = { + .name = XRT_ICAP, + }, + .subdev_id = XRT_SUBDEV_ICAP, + .endpoints = xrt_icap_endpoints, + .probe = xrt_icap_probe, + .leaf_call = xrt_icap_leaf_call, +}; + +XRT_LEAF_INIT_FINI_FUNC(icap); From patchwork Fri May 28 00:49:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 449614 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C4A4C47089 for ; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(396003)(39840400004)(136003)(346002)(376002)(36840700001)(46966006)(5660300002)(4326008)(8676002)(186003)(47076005)(70586007)(107886003)(2616005)(6916009)(316002)(82310400003)(70206006)(42186006)(7636003)(356005)(36756003)(6266002)(1076003)(36860700001)(478600001)(26005)(44832011)(54906003)(83380400001)(8936002)(2906002)(426003)(336012)(6666004); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 00:54:27.8385 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1e30e1d-9e81-4884-faaa-08d921732545 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT052.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB5411 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DDR calibration driver. DDR calibration is a hardware function discovered by walking firmware metadata. A xrt device node will be created for it. Hardware provides DDR calibration status through this function. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reviewed-by: Tom Rix --- .../fpga/xrt/include/xleaf/ddr_calibration.h | 28 +++ drivers/fpga/xrt/lib/xleaf/ddr_calibration.c | 210 ++++++++++++++++++ 2 files changed, 238 insertions(+) create mode 100644 drivers/fpga/xrt/include/xleaf/ddr_calibration.h create mode 100644 drivers/fpga/xrt/lib/xleaf/ddr_calibration.c diff --git a/drivers/fpga/xrt/include/xleaf/ddr_calibration.h b/drivers/fpga/xrt/include/xleaf/ddr_calibration.h new file mode 100644 index 000000000000..878740c26ca2 --- /dev/null +++ b/drivers/fpga/xrt/include/xleaf/ddr_calibration.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + */ + +#ifndef _XRT_DDR_CALIBRATION_H_ +#define _XRT_DDR_CALIBRATION_H_ + +#include "xleaf.h" +#include + +/* + * Memory calibration driver leaf calls. + */ +enum xrt_calib_results { + XRT_CALIB_UNKNOWN = 0, + XRT_CALIB_SUCCEEDED, + XRT_CALIB_FAILED, +}; + +enum xrt_calib_leaf_cmd { + XRT_CALIB_RESULT = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ +}; + +#endif /* _XRT_DDR_CALIBRATION_H_ */ diff --git a/drivers/fpga/xrt/lib/xleaf/ddr_calibration.c b/drivers/fpga/xrt/lib/xleaf/ddr_calibration.c new file mode 100644 index 000000000000..36a0937c9195 --- /dev/null +++ b/drivers/fpga/xrt/lib/xleaf/ddr_calibration.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo FPGA memory calibration driver + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * memory calibration + * + * Authors: + * Lizhi Hou + */ +#include +#include +#include "xclbin-helper.h" +#include "metadata.h" +#include "xleaf/ddr_calibration.h" + +#define XRT_CALIB "xrt_calib" + +#define XRT_CALIB_STATUS_REG 0 +#define XRT_CALIB_READ_RETRIES 20 +#define XRT_CALIB_READ_INTERVAL 500 /* ms */ + +XRT_DEFINE_REGMAP_CONFIG(calib_regmap_config); + +struct calib_cache { + struct list_head link; + const char *ep_name; + char *data; + u32 data_size; +}; + +struct calib { + struct xrt_device *xdev; + struct regmap *regmap; + struct mutex lock; /* calibration dev lock */ + struct list_head cache_list; + u32 cache_num; + enum xrt_calib_results result; +}; + +static void __calib_cache_clean_nolock(struct calib *calib) +{ + struct calib_cache *cache, *temp; + + list_for_each_entry_safe(cache, temp, &calib->cache_list, link) { + vfree(cache->data); + list_del(&cache->link); + vfree(cache); + } + calib->cache_num = 0; +} + +static void calib_cache_clean(struct calib *calib) +{ + mutex_lock(&calib->lock); + __calib_cache_clean_nolock(calib); + mutex_unlock(&calib->lock); +} + +static int calib_calibration(struct calib *calib) +{ + u32 times = XRT_CALIB_READ_RETRIES; + u32 status; + int ret; + + while (times != 0) { + ret = regmap_read(calib->regmap, XRT_CALIB_STATUS_REG, &status); + if (ret) { + xrt_err(calib->xdev, "failed to read status reg %d", ret); + return ret; + } + + if (status & BIT(0)) + break; + msleep(XRT_CALIB_READ_INTERVAL); + times--; + } + + if (!times) { + xrt_err(calib->xdev, + "MIG calibration timeout after bitstream download"); + return -ETIMEDOUT; + } + + xrt_info(calib->xdev, "took %dms", (XRT_CALIB_READ_RETRIES - times) * + XRT_CALIB_READ_INTERVAL); + return 0; +} + +static void xrt_calib_event_cb(struct xrt_device *xdev, void *arg) +{ + struct calib *calib = xrt_get_drvdata(xdev); + struct xrt_event *evt = (struct xrt_event *)arg; + enum xrt_events e = evt->xe_evt; + enum xrt_subdev_id id; + int ret; + + id = evt->xe_subdev.xevt_subdev_id; + + switch (e) { + case XRT_EVENT_POST_CREATION: + if (id == XRT_SUBDEV_UCS) { + ret = calib_calibration(calib); + if (ret) + calib->result = XRT_CALIB_FAILED; + else + calib->result = XRT_CALIB_SUCCEEDED; + } + break; + default: + xrt_dbg(xdev, "ignored event %d", e); + break; + } +} + +static void xrt_calib_remove(struct xrt_device *xdev) +{ + struct calib *calib = xrt_get_drvdata(xdev); + + calib_cache_clean(calib); +} + +static int xrt_calib_probe(struct xrt_device *xdev) +{ + void __iomem *base = NULL; + struct resource *res; + struct calib *calib; + int err = 0; + + calib = devm_kzalloc(&xdev->dev, sizeof(*calib), GFP_KERNEL); + if (!calib) + return -ENOMEM; + + calib->xdev = xdev; + xrt_set_drvdata(xdev, calib); + + res = xrt_get_resource(xdev, IORESOURCE_MEM, 0); + if (!res) { + err = -EINVAL; + goto failed; + } + + base = devm_ioremap_resource(&xdev->dev, res); + if (IS_ERR(base)) { + err = PTR_ERR(base); + goto failed; + } + + calib->regmap = devm_regmap_init_mmio(&xdev->dev, base, &calib_regmap_config); + if (IS_ERR(calib->regmap)) { + xrt_err(xdev, "Map iomem failed"); + err = PTR_ERR(calib->regmap); + goto failed; + } + + mutex_init(&calib->lock); + INIT_LIST_HEAD(&calib->cache_list); + + return 0; + +failed: + return err; +} + +static int +xrt_calib_leaf_call(struct xrt_device *xdev, u32 cmd, void *arg) +{ + struct calib *calib = xrt_get_drvdata(xdev); + int ret = 0; + + switch (cmd) { + case XRT_XLEAF_EVENT: + xrt_calib_event_cb(xdev, arg); + break; + case XRT_CALIB_RESULT: { + enum xrt_calib_results *r = (enum xrt_calib_results *)arg; + *r = calib->result; + break; + } + default: + xrt_err(xdev, "unsupported cmd %d", cmd); + ret = -EINVAL; + } + return ret; +} + +static struct xrt_dev_endpoints xrt_calib_endpoints[] = { + { + .xse_names = (struct xrt_dev_ep_names[]) { + { .ep_name = XRT_MD_NODE_DDR_CALIB }, + { NULL }, + }, + .xse_min_ep = 1, + }, + { 0 }, +}; + +static struct xrt_driver xrt_calib_driver = { + .driver = { + .name = XRT_CALIB, + }, + .subdev_id = XRT_SUBDEV_CALIB, + .endpoints = xrt_calib_endpoints, + .probe = xrt_calib_probe, + .remove = xrt_calib_remove, + .leaf_call = xrt_calib_leaf_call, +}; + +XRT_LEAF_INIT_FINI_FUNC(calib); From patchwork Fri May 28 00:49:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 449615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACD9FC47089 for ; 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A xrt device node will be created for it. Partition isolation function isolate the different fpga regions Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reviewed-by: Tom Rix --- drivers/fpga/xrt/include/xleaf/axigate.h | 23 ++ drivers/fpga/xrt/lib/xleaf/axigate.c | 325 +++++++++++++++++++++++ 2 files changed, 348 insertions(+) create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c diff --git a/drivers/fpga/xrt/include/xleaf/axigate.h b/drivers/fpga/xrt/include/xleaf/axigate.h new file mode 100644 index 000000000000..58f32c76dca1 --- /dev/null +++ b/drivers/fpga/xrt/include/xleaf/axigate.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#ifndef _XRT_AXIGATE_H_ +#define _XRT_AXIGATE_H_ + +#include "xleaf.h" +#include "metadata.h" + +/* + * AXIGATE driver leaf calls. + */ +enum xrt_axigate_leaf_cmd { + XRT_AXIGATE_CLOSE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ + XRT_AXIGATE_OPEN, +}; + +#endif /* _XRT_AXIGATE_H_ */ diff --git a/drivers/fpga/xrt/lib/xleaf/axigate.c b/drivers/fpga/xrt/lib/xleaf/axigate.c new file mode 100644 index 000000000000..493707b782e4 --- /dev/null +++ b/drivers/fpga/xrt/lib/xleaf/axigate.c @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo FPGA AXI Gate Driver + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#include +#include +#include +#include +#include +#include "metadata.h" +#include "xleaf.h" +#include "xleaf/axigate.h" + +#define XRT_AXIGATE "xrt_axigate" + +#define XRT_AXIGATE_WRITE_REG 0 +#define XRT_AXIGATE_READ_REG 8 + +#define XRT_AXIGATE_CTRL_CLOSE 0 +#define XRT_AXIGATE_CTRL_OPEN_BIT0 1 +#define XRT_AXIGATE_CTRL_OPEN_BIT1 2 + +#define XRT_AXIGATE_INTERVAL 500 /* ns */ + +struct xrt_axigate { + struct xrt_device *xdev; + struct regmap *regmap; + struct mutex gate_lock; /* gate dev lock */ + void *evt_hdl; + const char *ep_name; + bool gate_closed; +}; + +XRT_DEFINE_REGMAP_CONFIG(axigate_regmap_config); + +/* the ep names are in the order of hardware layers */ +static const char * const xrt_axigate_epnames[] = { + XRT_MD_NODE_GATE_PLP, /* PLP: Provider Logic Partition */ + XRT_MD_NODE_GATE_ULP /* ULP: User Logic Partition */ +}; + +static inline int close_gate(struct xrt_axigate *gate) +{ + u32 val; + int ret; + + ret = regmap_write(gate->regmap, XRT_AXIGATE_WRITE_REG, XRT_AXIGATE_CTRL_CLOSE); + if (ret) { + xrt_err(gate->xdev, "write gate failed %d", ret); + return ret; + } + ndelay(XRT_AXIGATE_INTERVAL); + /* + * Legacy hardware requires extra read work properly. + * This is not on critical path, thus the extra read should not impact performance much. + */ + ret = regmap_read(gate->regmap, XRT_AXIGATE_READ_REG, &val); + if (ret) { + xrt_err(gate->xdev, "read gate failed %d", ret); + return ret; + } + + return 0; +} + +static inline int open_gate(struct xrt_axigate *gate) +{ + u32 val; + int ret; + + ret = regmap_write(gate->regmap, XRT_AXIGATE_WRITE_REG, XRT_AXIGATE_CTRL_OPEN_BIT1); + if (ret) { + xrt_err(gate->xdev, "write 2 failed %d", ret); + return ret; + } + ndelay(XRT_AXIGATE_INTERVAL); + /* + * Legacy hardware requires extra read work properly. + * This is not on critical path, thus the extra read should not impact performance much. + */ + ret = regmap_read(gate->regmap, XRT_AXIGATE_READ_REG, &val); + if (ret) { + xrt_err(gate->xdev, "read 2 failed %d", ret); + return ret; + } + ret = regmap_write(gate->regmap, XRT_AXIGATE_WRITE_REG, + XRT_AXIGATE_CTRL_OPEN_BIT0 | XRT_AXIGATE_CTRL_OPEN_BIT1); + if (ret) { + xrt_err(gate->xdev, "write 3 failed %d", ret); + return ret; + } + ndelay(XRT_AXIGATE_INTERVAL); + ret = regmap_read(gate->regmap, XRT_AXIGATE_READ_REG, &val); + if (ret) { + xrt_err(gate->xdev, "read 3 failed %d", ret); + return ret; + } + + return 0; +} + +static int xrt_axigate_epname_idx(struct xrt_device *xdev) +{ + struct resource *res; + int ret, i; + + res = xrt_get_resource(xdev, IORESOURCE_MEM, 0); + if (!res) { + xrt_err(xdev, "Empty Resource!"); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(xrt_axigate_epnames); i++) { + ret = strncmp(xrt_axigate_epnames[i], res->name, + strlen(xrt_axigate_epnames[i]) + 1); + if (!ret) + return i; + } + + return -EINVAL; +} + +static int xrt_axigate_close(struct xrt_device *xdev) +{ + struct xrt_axigate *gate; + u32 status = 0; + int ret; + + gate = xrt_get_drvdata(xdev); + + mutex_lock(&gate->gate_lock); + ret = regmap_read(gate->regmap, XRT_AXIGATE_READ_REG, &status); + if (ret) { + xrt_err(xdev, "read gate failed %d", ret); + goto failed; + } + if (status) { /* gate is opened */ + xleaf_broadcast_event(xdev, XRT_EVENT_PRE_GATE_CLOSE, false); + ret = close_gate(gate); + if (ret) + goto failed; + } + + gate->gate_closed = true; + +failed: + mutex_unlock(&gate->gate_lock); + + xrt_info(xdev, "close gate %s", gate->ep_name); + return ret; +} + +static int xrt_axigate_open(struct xrt_device *xdev) +{ + struct xrt_axigate *gate; + u32 status; + int ret; + + gate = xrt_get_drvdata(xdev); + + mutex_lock(&gate->gate_lock); + ret = regmap_read(gate->regmap, XRT_AXIGATE_READ_REG, &status); + if (ret) { + xrt_err(xdev, "read gate failed %d", ret); + goto failed; + } + if (!status) { /* gate is closed */ + ret = open_gate(gate); + if (ret) + goto failed; + xleaf_broadcast_event(xdev, XRT_EVENT_POST_GATE_OPEN, true); + /* xrt_axigate_open() could be called in event cb, thus + * we can not wait for the completes + */ + } + + gate->gate_closed = false; + +failed: + mutex_unlock(&gate->gate_lock); + + xrt_info(xdev, "open gate %s", gate->ep_name); + return ret; +} + +static void xrt_axigate_event_cb(struct xrt_device *xdev, void *arg) +{ + struct xrt_axigate *gate = xrt_get_drvdata(xdev); + struct xrt_event *evt = (struct xrt_event *)arg; + enum xrt_events e = evt->xe_evt; + struct xrt_device *leaf; + enum xrt_subdev_id id; + struct resource *res; + int instance; + + if (e != XRT_EVENT_POST_CREATION) + return; + + instance = evt->xe_subdev.xevt_subdev_instance; + id = evt->xe_subdev.xevt_subdev_id; + if (id != XRT_SUBDEV_AXIGATE) + return; + + leaf = xleaf_get_leaf_by_id(xdev, id, instance); + if (!leaf) + return; + + res = xrt_get_resource(leaf, IORESOURCE_MEM, 0); + if (!res || !strncmp(res->name, gate->ep_name, strlen(res->name) + 1)) { + xleaf_put_leaf(xdev, leaf); + return; + } + + /* higher level axigate instance created, make sure the gate is opened. */ + if (xrt_axigate_epname_idx(leaf) > xrt_axigate_epname_idx(xdev)) + xrt_axigate_open(xdev); + else + xleaf_call(leaf, XRT_AXIGATE_OPEN, NULL); + + xleaf_put_leaf(xdev, leaf); +} + +static int +xrt_axigate_leaf_call(struct xrt_device *xdev, u32 cmd, void *arg) +{ + int ret = 0; + + switch (cmd) { + case XRT_XLEAF_EVENT: + xrt_axigate_event_cb(xdev, arg); + break; + case XRT_AXIGATE_CLOSE: + ret = xrt_axigate_close(xdev); + break; + case XRT_AXIGATE_OPEN: + ret = xrt_axigate_open(xdev); + break; + default: + xrt_err(xdev, "unsupported cmd %d", cmd); + return -EINVAL; + } + + return ret; +} + +static int xrt_axigate_probe(struct xrt_device *xdev) +{ + struct xrt_axigate *gate = NULL; + void __iomem *base = NULL; + struct resource *res; + int ret; + + gate = devm_kzalloc(&xdev->dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return -ENOMEM; + + gate->xdev = xdev; + xrt_set_drvdata(xdev, gate); + + xrt_info(xdev, "probing..."); + res = xrt_get_resource(xdev, IORESOURCE_MEM, 0); + if (!res) { + xrt_err(xdev, "Empty resource 0"); + ret = -EINVAL; + goto failed; + } + + base = devm_ioremap_resource(&xdev->dev, res); + if (IS_ERR(base)) { + xrt_err(xdev, "map base iomem failed"); + ret = PTR_ERR(base); + goto failed; + } + + gate->regmap = devm_regmap_init_mmio(&xdev->dev, base, &axigate_regmap_config); + if (IS_ERR(gate->regmap)) { + xrt_err(xdev, "regmap %pR failed", res); + ret = PTR_ERR(gate->regmap); + goto failed; + } + gate->ep_name = res->name; + + mutex_init(&gate->gate_lock); + + return 0; + +failed: + return ret; +} + +static struct xrt_dev_endpoints xrt_axigate_endpoints[] = { + { + .xse_names = (struct xrt_dev_ep_names[]) { + { .ep_name = XRT_MD_NODE_GATE_ULP }, + { NULL }, + }, + .xse_min_ep = 1, + }, + { + .xse_names = (struct xrt_dev_ep_names[]) { + { .ep_name = XRT_MD_NODE_GATE_PLP }, + { NULL }, + }, + .xse_min_ep = 1, + }, + { 0 }, +}; + +static struct xrt_driver xrt_axigate_driver = { + .driver = { + .name = XRT_AXIGATE, + }, + .subdev_id = XRT_SUBDEV_AXIGATE, + .endpoints = xrt_axigate_endpoints, + .probe = xrt_axigate_probe, + .leaf_call = xrt_axigate_leaf_call, +}; + +XRT_LEAF_INIT_FINI_FUNC(axigate);