From patchwork Sat Jun 5 14:40:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasad Malisetty X-Patchwork-Id: 455197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 370E4C4743E for ; Sat, 5 Jun 2021 14:41:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1AEDB611CA for ; Sat, 5 Jun 2021 14:41:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230108AbhFEOnX (ORCPT ); Sat, 5 Jun 2021 10:43:23 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:54875 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230105AbhFEOnX (ORCPT ); Sat, 5 Jun 2021 10:43:23 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1622904095; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=Jc5T8IWPGCtGM16740kwduRZ74s9DKe1zWNKlO+B9MM=; b=trcI2vsJeLdaJ/zhGQvnEVXYrPyp5At1hU0CenZYgv2NR0TKoDgYFBZXtmoYwfUpPAG0qThC gSv/L6iXi5G9NpmKq4eemqg86K6ZMgyjXYYgQTqrfomJDa/wzEB/RadSKZfw92yepcet2csv fHLh/FHmcC6J1vt0f7E5mL4fw0M= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyIxZTE2YSIsICJsaW51eC11c2JAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-west-2.postgun.com with SMTP id 60bb8d10ea2aacd729ec2892 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Sat, 05 Jun 2021 14:41:20 GMT Sender: pmaliset=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 791A5C4323A; Sat, 5 Jun 2021 14:41:20 +0000 (UTC) Received: from pmaliset-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pmaliset) by smtp.codeaurora.org (Postfix) with ESMTPSA id 29BF9C43145; Sat, 5 Jun 2021 14:41:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 29BF9C43145 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=pmaliset@codeaurora.org From: Prasad Malisetty To: agross@kernel.org, bjorn.andersson@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, swboyd@chromium.org, lorenzo.pieralisi@arm.com, svarbanov@mm-sol.com Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, dianders@chromium.org, mka@chromium.org, sanm@codeaurora.org, Prasad Malisetty Subject: [PATCH v2 1/4] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board Date: Sat, 5 Jun 2021 20:10:56 +0530 Message-Id: <1622904059-21244-2-git-send-email-pmaliset@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622904059-21244-1-git-send-email-pmaliset@codeaurora.org> References: <1622904059-21244-1-git-send-email-pmaliset@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add PCIe nodes for sc7280 IDP board. Signed-off-by: Prasad Malisetty --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 3900cfc..a58552b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -268,6 +268,34 @@ }; }; +&pcie1 { + status = "okay"; + + vdda-supply = <&vreg_l10c_0p8>; +}; + +&pcie1_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l10c_0p8>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + +&pcie1_default_state { + clkreq { + bias-pull-up; + }; + + wake-n { + drive-strength = <2>; + bias-pull-up; + }; + + nvme-n { + bias-pull-up; + }; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Sat Jun 5 14:40:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasad Malisetty X-Patchwork-Id: 454918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D43BAC4743D for ; Sat, 5 Jun 2021 14:41:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BD3DE613DF for ; Sat, 5 Jun 2021 14:41:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230030AbhFEOnR (ORCPT ); Sat, 5 Jun 2021 10:43:17 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:21071 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230050AbhFEOnR (ORCPT ); Sat, 5 Jun 2021 10:43:17 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1622904089; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=/8Dj0ibMqld9V83qHQThUqkGWUoqu6b8YmszZIbe/IU=; b=MrVAdKkr9bIMCjHOGalQ0RRr31rm4bE4YOEQbMVUUxWTvbdUVnaMzcgAMyr+V4iTKbzx3MnY h+UrEilHHQLfEk2A4ZblwNCvVhHzJORMkSXldDoqoBWDzMbBjq64utI5Tx+N5lXI9HO9MKA8 aLT98Q/AM5ys37lrP6lfqTp4/KU= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyIxZTE2YSIsICJsaW51eC11c2JAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-west-2.postgun.com with SMTP id 60bb8d14ed59bf69cc3d7805 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Sat, 05 Jun 2021 14:41:24 GMT Sender: pmaliset=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9D30CC43143; Sat, 5 Jun 2021 14:41:24 +0000 (UTC) Received: from pmaliset-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pmaliset) by smtp.codeaurora.org (Postfix) with ESMTPSA id 840E3C433F1; Sat, 5 Jun 2021 14:41:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 840E3C433F1 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=pmaliset@codeaurora.org From: Prasad Malisetty To: agross@kernel.org, bjorn.andersson@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, swboyd@chromium.org, lorenzo.pieralisi@arm.com, svarbanov@mm-sol.com Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, dianders@chromium.org, mka@chromium.org, sanm@codeaurora.org, Prasad Malisetty Subject: [PATCH v2 2/4] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes Date: Sat, 5 Jun 2021 20:10:57 +0530 Message-Id: <1622904059-21244-3-git-send-email-pmaliset@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622904059-21244-1-git-send-email-pmaliset@codeaurora.org> References: <1622904059-21244-1-git-send-email-pmaliset@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add PCIe controller and PHY nodes for sc7280 SOC. Signed-off-by: Prasad Malisetty --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 138 +++++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0b6f119..9e8414d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -484,6 +485,117 @@ #power-domain-cells = <1>; }; + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sc7280", "qcom,pcie-sm8250", "snps,dw-pcie"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie1_lane 0>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>; + + clock-names = "pipe", + "pipe_src", + "pipe_ext", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc GCC_PCIE_1_GDSC>; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + iommus = <&apps_smmu 0x1c80 0x1>; + + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; + status = "disabled"; + reg = <0 0x01c0e000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + pcie1_lane: lanes@1c0e200 { + reg = <0 0x01c0e200 0 0x170>, + <0 0x01c0e400 0 0x200>, + <0 0x01c0ea00 0 0x1f0>, + <0 0x01c0e600 0 0x170>, + <0 0x01c0e800 0 0x200>, + <0 0x01c0ee00 0 0xf4>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + #clock-cells = <1>; + clock-output-names = "pcie_1_pipe_clk"; + }; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, @@ -1102,6 +1214,32 @@ pins = "gpio46", "gpio47"; function = "qup13"; }; + + pcie1_default_state: pcie1-default { + clkreq { + pins = "gpio79"; + function = "pcie1_clkreqn"; + }; + + reset-n { + pins = "gpio2"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-disable; + }; + + wake-n { + pins = "gpio3"; + function = "gpio"; + }; + + nvme-n { + pins = "gpio19"; + function = "gpio"; + }; + }; }; apps_smmu: iommu@15000000 { From patchwork Sat Jun 5 14:40:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasad Malisetty X-Patchwork-Id: 454917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEA26C4743F for ; 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Sat, 05 Jun 2021 14:41:30 GMT Sender: pmaliset=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 24EA0C4338A; Sat, 5 Jun 2021 14:41:30 +0000 (UTC) Received: from pmaliset-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pmaliset) by smtp.codeaurora.org (Postfix) with ESMTPSA id 15D3AC4360C; Sat, 5 Jun 2021 14:41:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 15D3AC4360C Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=pmaliset@codeaurora.org From: Prasad Malisetty To: agross@kernel.org, bjorn.andersson@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, swboyd@chromium.org, lorenzo.pieralisi@arm.com, svarbanov@mm-sol.com Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, dianders@chromium.org, mka@chromium.org, sanm@codeaurora.org, Prasad Malisetty Subject: [PATCH v2 3/4] PCIe: qcom: Add support to control pipe clk mux Date: Sat, 5 Jun 2021 20:10:58 +0530 Message-Id: <1622904059-21244-4-git-send-email-pmaliset@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622904059-21244-1-git-send-email-pmaliset@codeaurora.org> References: <1622904059-21244-1-git-send-email-pmaliset@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org In PCIe driver pipe-clk mux needs to switch between pipe_clk and XO for GDSC enable. This is done by setting pipe_clk mux as parent of pipe_clk after phy init. Signed-off-by: Prasad Malisetty --- drivers/pci/controller/dwc/pcie-qcom.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8a7a300..5cbbea4 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -166,6 +166,9 @@ struct qcom_pcie_resources_2_7_0 { struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; struct clk *pipe_clk; + struct clk *pipe_clk_mux; + struct clk *pipe_ext_src; + struct clk *ref_clk_src; }; union qcom_pcie_resources { @@ -1167,6 +1170,20 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret < 0) return ret; + if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280")) { + res->pipe_clk_mux = devm_clk_get(dev, "pipe_src"); + if (IS_ERR(res->pipe_clk_mux)) + return PTR_ERR(res->pipe_clk_mux); + + res->pipe_ext_src = devm_clk_get(dev, "pipe_ext"); + if (IS_ERR(res->pipe_ext_src)) + return PTR_ERR(res->pipe_ext_src); + + res->ref_clk_src = devm_clk_get(dev, "ref"); + if (IS_ERR(res->ref_clk_src)) + return PTR_ERR(res->ref_clk_src); + } + res->pipe_clk = devm_clk_get(dev, "pipe"); return PTR_ERR_OR_ZERO(res->pipe_clk); } @@ -1255,6 +1272,11 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; + + if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280")) + clk_set_parent(res->pipe_clk_mux, res->pipe_ext_src); return clk_prepare_enable(res->pipe_clk); } From patchwork Sat Jun 5 14:40:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasad Malisetty X-Patchwork-Id: 455196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB2FAC4743E for ; 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Sat, 05 Jun 2021 14:41:40 GMT Sender: pmaliset=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9B641C43145; Sat, 5 Jun 2021 14:41:40 +0000 (UTC) Received: from pmaliset-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pmaliset) by smtp.codeaurora.org (Postfix) with ESMTPSA id 02E13C43143; Sat, 5 Jun 2021 14:41:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 02E13C43143 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=pmaliset@codeaurora.org From: Prasad Malisetty To: agross@kernel.org, bjorn.andersson@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, swboyd@chromium.org, lorenzo.pieralisi@arm.com, svarbanov@mm-sol.com Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, dianders@chromium.org, mka@chromium.org, sanm@codeaurora.org, Prasad Malisetty Subject: [PATCH v2 4/4] dt-bindings: pci: qcom: Document PCIe bindings for SC720 Date: Sat, 5 Jun 2021 20:10:59 +0530 Message-Id: <1622904059-21244-5-git-send-email-pmaliset@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622904059-21244-1-git-send-email-pmaliset@codeaurora.org> References: <1622904059-21244-1-git-send-email-pmaliset@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Document the PCIe DT bindings for SC7280 SoC.The PCIe IP is similar to the one used on SM8250. Add the compatible for SC7280. Signed-off-by: Prasad Malisetty Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 25f4def..9c0908f 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -12,6 +12,7 @@ - "qcom,pcie-ipq4019" for ipq4019 - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 + - "qcom,pcie-sc7280" for sc7280 - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 - "qcom,pcie-ipq6018" for ipq6018 @@ -144,6 +145,22 @@ - "slave_bus" AXI Slave clock - clock-names: + Usage: required for sc7280 + Value type: + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock + - "pipe" PIPE clock + - "pipe_src" PIPE MUX + - "pipe_ext" PIPE output clock + - "ref" REFERENCE clock + +- clock-names: Usage: required for sdm845 Value type: Definition: Should contain the following entries