From patchwork Wed Jul 25 05:30:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongbo Zhang X-Patchwork-Id: 142844 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp388252ljj; Tue, 24 Jul 2018 22:33:15 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfMEaQfvYIrkMDDvtwKUKq5mcFZgG1puXjpVv9oycSYUHNBLTpljMvdRnlMhkz/mMyOUbcx X-Received: by 2002:a37:ab17:: with SMTP id u23-v6mr18134617qke.279.1532496795096; Tue, 24 Jul 2018 22:33:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532496795; cv=none; d=google.com; s=arc-20160816; b=T0lFiPPdCe+2SCDRpIqhq8jVz8vC24MjRgxDE3LO1MGSYIQnEEWEuBWv7ezobDjVmu ge4ixmqz0m3T01oLWHy8Xm4D41VayFoMadejTkmxb2ZgXPwN915PMqS/1TUVRnB4GCjW fSavi5gJtQHvrypejyswYQyyBMZWAy/10WDj39or1EhB3gIA5Hw4lO3GiGEd1cuXmlAo MPv0W0x7J7cptIpsW2SE4ULvE0yycfb8tpySeTZiqS1wRi4ZALpj7sVb0DrlOmddEtr7 u5UIhyeVWbGh00tOk8kYB8QlPyOnqKqixoMkX6Q0EYZ7/UOIYNhyCGv4p0K63gC7VEbm etmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=NNN8mjnF2Vz3g5GOst/CbeIh72InaXfGbwD4IxSBb8c=; b=fU0Nl5C5nqizRgXsBWcSq+54dgXbiSclZKihcdVR497FFuC9w5Md4M1cv6wM4uEPQT 4aMe5URU1UIhdpxCpzb2E3XDSA9DAmynKAG1Qw7uUYCWsxgk6fCFoYwAokk8R3WPQgc9 CsQJP5sksFV5r+PKU3FjHO49u2czByP6ZXA9PqCtGnhAVKtTn92yd5cjkhqGcqSnF7P6 gyueKpeHc3qCWZhfkB+EvKUvbj5d09CuRsvGZFalEGWblY9G0Q8Od9J4vrdjvom1QYp5 JdyhllLt7mjvxz+c3ZBR0M/tMDYgVde3EwozoQpipmJ4NmR2OKfuwPoR5u9ca2To2nTg IOjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NnjQ4Evw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p9-v6si6114664qtf.102.2018.07.24.22.33.14 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 24 Jul 2018 22:33:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NnjQ4Evw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44761 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fiCQE-00046T-Jo for patch@linaro.org; Wed, 25 Jul 2018 01:33:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42608) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fiCOC-0003RH-Dj for qemu-devel@nongnu.org; Wed, 25 Jul 2018 01:31:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fiCO9-0007vf-Ek for qemu-devel@nongnu.org; Wed, 25 Jul 2018 01:31:08 -0400 Received: from mail-qk0-x242.google.com ([2607:f8b0:400d:c09::242]:43099) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fiCO9-0007vS-1G for qemu-devel@nongnu.org; Wed, 25 Jul 2018 01:31:05 -0400 Received: by mail-qk0-x242.google.com with SMTP id z74-v6so4160708qkb.10 for ; Tue, 24 Jul 2018 22:31:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=NNN8mjnF2Vz3g5GOst/CbeIh72InaXfGbwD4IxSBb8c=; b=NnjQ4Evww3G4v0Cmoaas5Yuir56afZ9ackVe8ydvdzTH3BeXxR7sSPTYvwRLKy77AP nW+PnFSulOhna0E3FLK92xoRGwfmKpXSqR7Qr6+mIi7YUP1NXf2GXTD2XRnkuU/bPU1x pwh0sBbbUP1NVPTh630rUgupEwAGniVS/XMmQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=NNN8mjnF2Vz3g5GOst/CbeIh72InaXfGbwD4IxSBb8c=; b=KPM88t6/E4jzduskMyIR/7isbmccRzgboOQbSKnV0+y8egEQN7UVK/FKX1z+wBB+Rb CFuAmjdZ/DMDMlBHjcPTO7o+zHVPZfFsx4HJSoZbVmi/i/dcqDMVblxXD2ilBQYaHdkk WELGJLS3B3ti9zqh3JopmY/s9+8Bb2psQvx14Lfoiqfbus+gB/jHPyU6yoRSa0kHEzjc PllLs24CyL1AAenJeAtHp5/uQMUgwUB2Mt3B+dYPZp4fnJIEBOlglQ3PfFEe3KCXvYpu 1ULfkBVkT+kXGeRnY5xuwwOChKv9Ta1selgGFu7PsDZuREZNJvoAd2KtaAT6YN5SJzKS t5fA== X-Gm-Message-State: AOUpUlF8fdJYTjfGqeCGQ+LSrRx57WcmrSWPDovZKwsKaGcm6TeYEwxb Vm7jGsNmlmfjUNTCsYV/rdUpag== X-Received: by 2002:a37:5142:: with SMTP id f63-v6mr18186304qkb.369.1532496664198; Tue, 24 Jul 2018 22:31:04 -0700 (PDT) Received: from localhost.localdomain ([104.237.86.219]) by smtp.gmail.com with ESMTPSA id v129-v6sm8621380qkd.86.2018.07.24.22.31.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Jul 2018 22:31:03 -0700 (PDT) From: Hongbo Zhang To: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Wed, 25 Jul 2018 13:30:51 +0800 Message-Id: <1532496652-26364-1-git-send-email-hongbo.zhang@linaro.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH v2 1/2] hw/arm: check fw_cfg return value before using it X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hongbo Zhang , radoslaw.biernacki@linaro.org, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fw_cfg value returned from fw_cfg_find() may be NULL, so check it before using. Signed-off-by: Hongbo Zhang --- hw/arm/boot.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index e09201c..43b217f 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -930,6 +930,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) hwaddr entry; static const ARMInsnFixup *primary_loader; AddressSpace *as = arm_boot_address_space(cpu, info); + FWCfgState *fw_cfg; /* CPU objects (unlike devices) are not automatically reset on system * reset, so we must always register a handler to do so. If we're @@ -960,11 +961,10 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) info->dtb_start = info->loader_start; } - if (info->kernel_filename) { - FWCfgState *fw_cfg; + fw_cfg = fw_cfg_find(); + if (info->kernel_filename && fw_cfg) { bool try_decompressing_kernel; - fw_cfg = fw_cfg_find(); try_decompressing_kernel = arm_feature(&cpu->env, ARM_FEATURE_AARCH64); From patchwork Wed Jul 25 05:30:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongbo Zhang X-Patchwork-Id: 142845 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp388339ljj; Tue, 24 Jul 2018 22:33:19 -0700 (PDT) X-Google-Smtp-Source: AAOMgpf+PLjdPDTl7MlMk4SFHnI0g0Ry4fPeJ8mMYdhhfFKk2Qd0H5LhmuWTzsEa6k6QKFidGfjP X-Received: by 2002:a37:9986:: with SMTP id b128-v6mr18072906qke.288.1532496799429; Tue, 24 Jul 2018 22:33:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532496799; cv=none; d=google.com; s=arc-20160816; b=OSC3ILR9Vf0fDVY3szPiqo+wRMvL5ZGhMMZFANOprgUf5aWDRuGlCQb1Dbg6QjoSth k7gYca0dkHYjZMXnXX6YtBWoeEPPAU8pmCQwOFLdsCXM3u5GMvucGgkBu9Lhpm+8DKI6 MUi8x0Buranjnm+JBL032DWbtoDYOAXYxg1OOnipOPkHkOmctVUwvi+xtHm6BWqgno61 ArpGDVRzQ4wtkbp8V5Vv8SJOCW+E4iCvUDZHJgxC6qJKncHYgOeAh4tLGZqWQ/umBcmO ZYFZaVNMgqg9Vvk34eU5PCk/wBdu1CTTzJiScxMZRjJEpnGypxRdXSdOVJscTyTly+t0 hkjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=bt/Q7cTbIxcj27rf9iVj/70mX33S56b9AMdvBc1hgFc=; b=DcU7j3XN1+OB+KoIlq244icsKoEDJHZrFtpQ4x2MRMu+ZFQYgvasTY8Uz99dYDxK0d CMp2FofShCaavO2CqciO4liNSM5Nbv0nv1LWFoSjx5pJxgbUstIHTfuXlfwxppeql5EX AM4muJQ2H6SV1AlDf5uCTgkGFtDfuZ5Zq8cipM14L46eTyWZhFgdNy2cnFYatxOOzy7C z8LrIWkboMP9/DOD0h/CS6juePuCD2I8YT9wZdssWzTP95cFi2PIMVdahcKUJkII1HlI hkx36Hx+5uuV5hClvvrvYfiAfpfB2PyKCWn0VyWqTv4f//Ya7lH6b9iiFVY+lasZ8DW7 hm+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XCGRSJ7A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p43-v6si12738080qtc.79.2018.07.24.22.33.19 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 24 Jul 2018 22:33:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XCGRSJ7A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44762 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fiCQI-00049y-UV for patch@linaro.org; Wed, 25 Jul 2018 01:33:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42622) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fiCOG-0003RS-Ig for qemu-devel@nongnu.org; Wed, 25 Jul 2018 01:31:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fiCOD-0007xW-Ja for qemu-devel@nongnu.org; Wed, 25 Jul 2018 01:31:12 -0400 Received: from mail-qk0-x241.google.com ([2607:f8b0:400d:c09::241]:45714) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fiCOD-0007xO-CN for qemu-devel@nongnu.org; Wed, 25 Jul 2018 01:31:09 -0400 Received: by mail-qk0-x241.google.com with SMTP id c192-v6so4151480qkg.12 for ; Tue, 24 Jul 2018 22:31:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bt/Q7cTbIxcj27rf9iVj/70mX33S56b9AMdvBc1hgFc=; b=XCGRSJ7AgKHdQQdaHxZM6YAVILm6xHtIUnIwXbZ/DEjb13uVglHlxxs2d/7278jQXw K/3XWbwESIZvtlQWZmVcCUop7RCdqU5i+wzAv4/SuR39CTHkQQH3UKTiBi9DUyW+YfCK ZWdTYvAmOV0I+5zOVcUqnVdlf2jVvX0/55BEI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bt/Q7cTbIxcj27rf9iVj/70mX33S56b9AMdvBc1hgFc=; b=Ta25UbAHlBHEmKtYpGUp5mDuevSH4B4U+RP9/YB3vB02093UJzICzDXoF6VlDM6ZBV b4rYSFEmJPQJfxpsbmOcXVK/tGOYMMhzlkHadPtdo/kENVTTItCkskyuC7t9RwXAYLuT gUYbMZd/zbkTxaDG/jCnTEkQcQJaCgapjoXIYsIWIOACrG4hEAtKBKwzY/1IYUesqPyT H6NuEeY+8WHBtqhipa3+y7lW+3m1FhCq/eeF9k46FwIfFTkIhNKFF74f5CbPHHkZZ+Du rhywS/NBIxj1/sBqNlH5phcfIFDee1Km2CzH85+asSVGMa+CmQFFMNvgENbbVFgA6+Qj FRDw== X-Gm-Message-State: AOUpUlGQpdWrJdkcdUGXAmW2Eet5JxMhTLSANSkMpdj1aUvDTGe7tw4i LJQKNPQBHYv+7YflopQzB/34YA== X-Received: by 2002:a37:5285:: with SMTP id g127-v6mr17351193qkb.377.1532496668699; Tue, 24 Jul 2018 22:31:08 -0700 (PDT) Received: from localhost.localdomain ([104.237.86.219]) by smtp.gmail.com with ESMTPSA id v129-v6sm8621380qkd.86.2018.07.24.22.31.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Jul 2018 22:31:08 -0700 (PDT) From: Hongbo Zhang To: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Wed, 25 Jul 2018 13:30:52 +0800 Message-Id: <1532496652-26364-2-git-send-email-hongbo.zhang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532496652-26364-1-git-send-email-hongbo.zhang@linaro.org> References: <1532496652-26364-1-git-send-email-hongbo.zhang@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [PATCH v2 2/2] hw/arm: Add Arm Enterprise machine type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hongbo Zhang , radoslaw.biernacki@linaro.org, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For the Aarch64, there is one machine 'virt', it is primarily meant to run on KVM and execute virtualization workloads, but we need an environment as faithful as possible to physical hardware, for supporting firmware and OS development for pysical Aarch64 machines. This patch introduces new machine type 'Enterprise' with main features: - Based on 'virt' machine type. - Re-designed memory map. - EL2 and EL3 are enabled by default. - GIC version 3 by default. - AHCI controller attached to system bus, and then CDROM and hard disc can be added to it. - EHCI controller attached to system bus, with USB mouse and key board installed by default. - E1000E ethernet card on PCIE bus. - VGA display adaptor on PCIE bus. - Default CPU type cortex-a57, 4 cores, and 1G bytes memory. - No virtio functions enabled, since this is to emulate real hardware. - No paravirtualized fw_cfg device either. Arm Trusted Firmware and UEFI porting to this are done accordingly. Signed-off-by: Hongbo Zhang --- Changes since v1: - rebase on v3.0.0-rc0 - introduce another auxillary patch as 1/2, so this is 2/2 - rename 'sbsa' to 'enterprise' - remove paravirualized fw_cfg - set gic_vertion to 3 instead of 2 - edit commit message to describe purpose of this platform hw/arm/virt-acpi-build.c | 59 +++++++++++++- hw/arm/virt.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++- include/hw/arm/virt.h | 3 + 3 files changed, 255 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6ea47e2..212832e 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -84,6 +84,52 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, aml_append(scope, dev); } +static void acpi_dsdt_add_ahci(Aml *scope, const MemMapEntry *ahci_memmap, + uint32_t ahci_irq) +{ + Aml *dev = aml_device("AHC0"); + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO001E"))); + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + Aml *crs = aml_resource_template(); + aml_append(crs, aml_memory32_fixed(ahci_memmap->base, + ahci_memmap->size, AML_READ_WRITE)); + aml_append(crs, + aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, + AML_EXCLUSIVE, &ahci_irq, 1)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + Aml *pkg = aml_package(3); + aml_append(pkg, aml_int(0x1)); + aml_append(pkg, aml_int(0x6)); + aml_append(pkg, aml_int(0x1)); + + /* append the SATA class id */ + aml_append(dev, aml_name_decl("_CLS", pkg)); + + aml_append(scope, dev); +} + +static void acpi_dsdt_add_ehci(Aml *scope, const MemMapEntry *ehci_memmap, + uint32_t ehci_irq) +{ + Aml *dev = aml_device("EHC0"); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0D20"))); + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + Aml *crs = aml_resource_template(); + aml_append(crs, aml_memory32_fixed(ehci_memmap->base, + ehci_memmap->size, AML_READ_WRITE)); + aml_append(crs, + aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, + AML_EXCLUSIVE, &ehci_irq, 1)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + aml_append(scope, dev); +} + static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) { Aml *dev = aml_device("FWCF"); @@ -768,14 +814,23 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) (irqmap[VIRT_UART] + ARM_SPI_BASE)); acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); - acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], - (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); + if (!vms->enterprise) { + acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], + (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); + } acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), vms->highmem, vms->highmem_ecam); acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); acpi_dsdt_add_power_button(scope); + if (vms->enterprise) { + acpi_dsdt_add_ahci(scope, &memmap[VIRT_AHCI], + (irqmap[VIRT_AHCI] + ARM_SPI_BASE)); + acpi_dsdt_add_ehci(scope, &memmap[VIRT_EHCI], + (irqmap[VIRT_EHCI] + ARM_SPI_BASE)); + } + aml_append(dsdt, scope); /* copy AML table into ACPI tables blob and patch header there */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 281ddcd..498b526 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -59,6 +59,10 @@ #include "qapi/visitor.h" #include "standard-headers/linux/input.h" #include "hw/arm/smmuv3.h" +#include "hw/ide/internal.h" +#include "hw/ide/ahci_internal.h" +#include "hw/usb.h" +#include "qemu/units.h" #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -94,6 +98,8 @@ #define PLATFORM_BUS_NUM_IRQS 64 +#define SATA_NUM_PORTS 6 + /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means * RAM can go up to the 256GB mark, leaving 256GB of the physical * address space unallocated and free for future use between 256G and 512G. @@ -168,6 +174,47 @@ static const int a15irqmap[] = { [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ }; +static const MemMapEntry enterprise_memmap[] = { + /* Space up to 0x8000000 is reserved for a boot ROM */ + [VIRT_FLASH] = { 0, 0x08000000 }, + [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, + /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ + [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, + [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, + [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, + /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ + [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, + /* This redistributor space allows up to 2*64kB*123 CPUs */ + [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, + [VIRT_UART] = { 0x09000000, 0x00001000 }, + [VIRT_RTC] = { 0x09010000, 0x00001000 }, + [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, + [VIRT_GPIO] = { 0x09030000, 0x00001000 }, + [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, + [VIRT_AHCI] = { 0x09050000, 0x00010000 }, + [VIRT_EHCI] = { 0x09060000, 0x00010000 }, + [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, + [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, + [VIRT_PCIE_MMIO] = { 0x10000000, 0x7fff0000 }, + [VIRT_PCIE_PIO] = { 0x8fff0000, 0x00010000 }, + [VIRT_PCIE_ECAM] = { 0x90000000, 0x10000000 }, + /* Second PCIe window, 508GB wide at the 4GB boundary */ + [VIRT_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0x7F00000000ULL }, + [VIRT_MEM] = { 0x8000000000ULL, RAMLIMIT_BYTES }, +}; + +static const int enterprise_irqmap[] = { + [VIRT_UART] = 1, + [VIRT_RTC] = 2, + [VIRT_PCIE] = 3, /* ... to 6 */ + [VIRT_GPIO] = 7, + [VIRT_SECURE_UART] = 8, + [VIRT_AHCI] = 9, + [VIRT_EHCI] = 10, + [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ + [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ +}; + static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a15"), ARM_CPU_TYPE_NAME("cortex-a53"), @@ -706,6 +753,72 @@ static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) g_free(nodename); } +static void create_ahci(const VirtMachineState *vms, qemu_irq *pic) +{ + char *nodename; + hwaddr base = vms->memmap[VIRT_AHCI].base; + hwaddr size = vms->memmap[VIRT_AHCI].size; + int irq = vms->irqmap[VIRT_AHCI]; + const char compat[] = "qemu,mach-virt-ahci\0generic-ahci"; + DeviceState *dev; + DriveInfo *hd[SATA_NUM_PORTS]; + SysbusAHCIState *sysahci; + AHCIState *ahci; + int i; + + dev = qdev_create(NULL, "sysbus-ahci"); + qdev_prop_set_uint32(dev, "num-ports", SATA_NUM_PORTS); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); + + sysahci = SYSBUS_AHCI(dev); + ahci = &sysahci->ahci; + ide_drive_get(hd, ARRAY_SIZE(hd)); + for (i = 0; i < ahci->ports; i++) { + if (hd[i] == NULL) { + continue; + } + ide_create_drive(&ahci->dev[i].port, 0, hd[i]); + } + + nodename = g_strdup_printf("/sata@%" PRIx64, base); + qemu_fdt_add_subnode(vms->fdt, nodename); + qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + 2, base, 2, size); + qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + g_free(nodename); +} + +static void create_ehci(const VirtMachineState *vms, qemu_irq *pic) +{ + char *nodename; + hwaddr base = vms->memmap[VIRT_EHCI].base; + hwaddr size = vms->memmap[VIRT_EHCI].size; + int irq = vms->irqmap[VIRT_EHCI]; + const char compat[] = "qemu,mach-virt-ehci\0generic-ehci"; + USBBus *usb_bus; + + sysbus_create_simple("exynos4210-ehci-usb", base, pic[irq]); + + usb_bus = usb_bus_find(-1); + usb_create_simple(usb_bus, "usb-kbd"); + usb_create_simple(usb_bus, "usb-mouse"); + + nodename = g_strdup_printf("/ehci@%" PRIx64, base); + qemu_fdt_add_subnode(vms->fdt, nodename); + qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + 2, base, 2, size); + qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + g_free(nodename); +} + static DeviceState *gpio_key_dev; static void virt_powerdown_req(Notifier *n, void *opaque) { @@ -1117,13 +1230,21 @@ static void create_pcie(VirtMachineState *vms, qemu_irq *pic) NICInfo *nd = &nd_table[i]; if (!nd->model) { - nd->model = g_strdup("virtio"); + if (vms->enterprise) { + nd->model = g_strdup("e1000e"); + } else { + nd->model = g_strdup("virtio"); + } } pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); } } + if (vms->enterprise) { + pci_create_simple(pci->bus, -1, "VGA"); + } + nodename = g_strdup_printf("/pcie@%" PRIx64, base); qemu_fdt_add_subnode(vms->fdt, nodename); qemu_fdt_setprop_string(vms->fdt, nodename, @@ -1512,14 +1633,21 @@ static void machvirt_init(MachineState *machine) create_gpio(vms, pic); + if (vms->enterprise) { + create_ahci(vms, pic); + create_ehci(vms, pic); + } + /* Create mmio transports, so the user can create virtio backends * (which will be automatically plugged in to the transports). If * no backend is created the transport will just sit harmlessly idle. */ - create_virtio_devices(vms, pic); + if (!vms->enterprise) { + create_virtio_devices(vms, pic); - vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); - rom_set_fw(vms->fw_cfg); + vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); + rom_set_fw(vms->fw_cfg); + } create_platform_bus(vms, pic); @@ -1828,6 +1956,7 @@ static void virt_3_0_instance_init(Object *obj) vms->memmap = a15memmap; vms->irqmap = a15irqmap; + vms->enterprise = false; } static void virt_machine_3_0_options(MachineClass *mc) @@ -1960,3 +2089,65 @@ static void virt_machine_2_6_options(MachineClass *mc) vmc->no_pmu = true; } DEFINE_VIRT_MACHINE(2, 6) + +static void enterprise_instance_init(Object *obj) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->secure = true; + object_property_add_bool(obj, "secure", virt_get_secure, + virt_set_secure, NULL); + object_property_set_description(obj, "secure", + "Set on/off to enable/disable the ARM " + "Security Extensions (TrustZone)", + NULL); + + vms->virt = true; + object_property_add_bool(obj, "virtualization", virt_get_virt, + virt_set_virt, NULL); + object_property_set_description(obj, "virtualization", + "Set on/off to enable/disable emulating a " + "guest CPU which implements the ARM " + "Virtualization Extensions", + NULL); + + vms->highmem = true; + + vms->gic_version = 3; + object_property_add_str(obj, "gic-version", virt_get_gic_version, + virt_set_gic_version, NULL); + object_property_set_description(obj, "gic-version", + "Set GIC version. " + "Valid values are 2, 3, host, max", NULL); + vms->its = true; + + vms->memmap = enterprise_memmap; + vms->irqmap = enterprise_irqmap; + vms->enterprise = true; +} + +static void enterprise_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->max_cpus = 246; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); + mc->block_default_type = IF_IDE; + mc->default_ram_size = 1 * GiB; + mc->default_cpus = 4; + mc->desc = "QEMU 'Enterprise' ARM Virtual Machine"; +} + +static const TypeInfo enterprise_info = { + .name = MACHINE_TYPE_NAME("enterprise"), + .parent = TYPE_VIRT_MACHINE, + .instance_init = enterprise_instance_init, + .class_init = enterprise_class_init, +}; + +static void enterprise_machine_init(void) +{ + type_register_static(&enterprise_info); +} + +type_init(enterprise_machine_init); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9a870cc..e65d478 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -78,6 +78,8 @@ enum { VIRT_GPIO, VIRT_SECURE_UART, VIRT_SECURE_MEM, + VIRT_AHCI, + VIRT_EHCI, }; typedef enum VirtIOMMUType { @@ -124,6 +126,7 @@ typedef struct { uint32_t msi_phandle; uint32_t iommu_phandle; int psci_conduit; + bool enterprise; } VirtMachineState; #define VIRT_ECAM_ID(high) (high ? VIRT_PCIE_ECAM_HIGH : VIRT_PCIE_ECAM)