From patchwork Thu Jul 26 07:09:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keiji Hayashibara X-Patchwork-Id: 142939 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp121807ljj; Thu, 26 Jul 2018 00:10:44 -0700 (PDT) X-Google-Smtp-Source: AAOMgpe+esvlP1pG9RIkaM+DbpM1L933VrHgj7lkn7KxzLZ/8QHmhGFFdEzerJGB4qrQa4Lk+zmU X-Received: by 2002:a62:df82:: with SMTP id d2-v6mr868764pfl.189.1532589044665; Thu, 26 Jul 2018 00:10:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532589044; cv=none; d=google.com; s=arc-20160816; b=W1dDWKalVcbBcg3xCg5BHcewqiIFn8/LK5v2EGNRuCusNtERPz/7kLPHfDHDjge9Jb iccPvfhAXY5+jeztFK9mdxRkzqYcXcnAkrPYDpR/CrWVNdinYfRppxaAm4PfeBUOtoo0 Q/9/RQ/h6AU6HcppHv7v39tV5p94YP+rphP0RsIiV+80O3G8Yn2n+AN7wvwzJWVcI/Su 3O0tZMbVWd49g6ulOkzOKoIiM9Pg5f/eQ8t0O7Cl1qBfh9AlErLDu7nf/To0FtwpBuXz gn51Yjk8/zfPzd70UX/abMfAQf9PIKlj9DOUuqF52466IgjyX0Q3hUZh4I/kGb8LTmVt AHCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=xri5lgYDY/gKQGrfZr5Ze6SAsyYxk7NtF98AWowoufw=; b=y/M72zQxtSbIutrjqpR9PFG7Fn4SckxCSWGLBmA+sFDqFD0g2ay39THnh661k05sZh u043k+vvhdGeAJD/6UiD6O+eqxQf3774C8tfNl+Ja8ncbgfQxa+DpUgfOJVcsroYQJJU rAcW4IIyBywR4AVYeQrwj8P0bHtoTcIUxsIyx3fz1dN3I0AhwD2x8Y3wdqdbF2rRlsk3 6MQGpUyxw5UjcbxNQ8TqoqvHqM7XCtyDlykiTpUMLZSp/YG+B4t85+h+kt8sBuhLTaFz MhuLFgNR3ZBCLgQOy8KNTLzJFSqs9+2n5v890Tx6qBPIqGtPlNGXWlfGE1TJUZ83OVkT ed7A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u30-v6si703562pfl.87.2018.07.26.00.10.44; Thu, 26 Jul 2018 00:10:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729097AbeGZIZr (ORCPT + 31 others); Thu, 26 Jul 2018 04:25:47 -0400 Received: from mx.socionext.com ([202.248.49.38]:12191 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729013AbeGZIZr (ORCPT ); Thu, 26 Jul 2018 04:25:47 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 26 Jul 2018 16:10:20 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 4C92660035; Thu, 26 Jul 2018 16:10:20 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 26 Jul 2018 16:10:20 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id D3D961A120D; Thu, 26 Jul 2018 16:10:19 +0900 (JST) From: Keiji Hayashibara To: robh+dt@kernel.org, mark.rutland@arm.com, yamada.masahiro@socionext.com, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: masami.hiramatsu@linaro.org, jaswinder.singh@linaro.org, linux-kernel@vger.kernel.org, hayashibara.keiji@socionext.com, Kunihiko Hayashi Subject: [PATCH v2 1/3] ARM: dts: uniphier: add SPI pin-mux node Date: Thu, 26 Jul 2018 16:09:58 +0900 Message-Id: <1532589000-19602-2-git-send-email-hayashibara.keiji@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532589000-19602-1-git-send-email-hayashibara.keiji@socionext.com> References: <1532589000-19602-1-git-send-email-hayashibara.keiji@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kunihiko Hayashi This commit adds pin-mux nodes for SPI controller. Signed-off-by: Kunihiko Hayashi --- arch/arm/boot/dts/uniphier-pinctrl.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.7.4 diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi index 51f0e69..5dc4cf7 100644 --- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi @@ -126,6 +126,26 @@ function = "sd1"; }; + pinctrl_spi0: spi0 { + groups = "spi0"; + function = "spi0"; + }; + + pinctrl_spi1: spi1 { + groups = "spi1"; + function = "spi1"; + }; + + pinctrl_spi2: spi2 { + groups = "spi2"; + function = "spi2"; + }; + + pinctrl_spi3: spi3 { + groups = "spi3"; + function = "spi3"; + }; + pinctrl_system_bus: system-bus { groups = "system_bus", "system_bus_cs1"; function = "system_bus"; From patchwork Thu Jul 26 07:09:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keiji Hayashibara X-Patchwork-Id: 142937 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp121514ljj; Thu, 26 Jul 2018 00:10:26 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd2mWgTGfmXVyqL4TfwpNcvTN2N4P8INuWPt7qbm3DEIJXRPpj0bkGGIJfs/oZmLDhecJxb X-Received: by 2002:a63:ff4d:: with SMTP id s13-v6mr826076pgk.150.1532589026303; Thu, 26 Jul 2018 00:10:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532589026; cv=none; d=google.com; s=arc-20160816; b=qhD1wVerDcAZUpc1GGX/KGYm8cJ1YcUgB8X43O/0sjTaay9UaIK3O3TRxGVc4PAnqL FYvBsashZ5Ngn+YxQOJwynFaW2R4fWwtm+5NjCiHkRYw1xoxG0YSYJKylgnq7X5ARwNP jMYnds/PaVcAmFD4BCr9mzGbW7Buunqzpx504vAjEh3zbkk0alVKq5kSWFC/Lgh6lNDU 97HAy87LKYq5owcLwpR+YyJNC230lCWOd0SwmO2j9CStt31wbpd084TumkZxkE4vkqJ2 Dfbjbx2BnRd6KAtTyrd0Qzv5+Pu7SIK/qypACmHfUQCgM7lRePFtsGWAQSb+qMKEaa6F l/sQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=YPbU7vlRZhpRb8oph6Ea6wM2lBij0eid3NzKF1GByeM=; b=jj9v6gn0wFiXDASxjdTBwcpylAUEggfAP+A+4ez5cUdClkmzh4jTUpqYAXJQVy1XLr 57bEey7VfwXbTtLx/Ol/DBy0T6wm68y85bE+cseQE2U1RFwmRD15rT2GIuDdmIDc9tl7 F7jiqP9IXRrN7r0Lp/jqyvtFnjNZaj8T4O+/zyJsfLFrvORBd0dcpUMFsoKpv2wjC0hA f+rAMwdZX7of9ftW+4H8bnhNdZEtjzvn+m7t4e+ptskngh6o2O5iOergpzT2iqg/gdnb u4TX3uSIZbPHknbt3ajUyc0mx68+XtzS1/hbsjaYihkIQNUIp3UCEG5Jm5lWPkg5mwCz l4Lg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j67-v6si621040pgc.186.2018.07.26.00.10.26; Thu, 26 Jul 2018 00:10:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729164AbeGZIZt (ORCPT + 31 others); Thu, 26 Jul 2018 04:25:49 -0400 Received: from mx.socionext.com ([202.248.49.38]:12186 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728310AbeGZIZs (ORCPT ); Thu, 26 Jul 2018 04:25:48 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 26 Jul 2018 16:10:20 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 861C660034; Thu, 26 Jul 2018 16:10:20 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 26 Jul 2018 16:10:20 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 2BD501A01BB; Thu, 26 Jul 2018 16:10:20 +0900 (JST) From: Keiji Hayashibara To: robh+dt@kernel.org, mark.rutland@arm.com, yamada.masahiro@socionext.com, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: masami.hiramatsu@linaro.org, jaswinder.singh@linaro.org, linux-kernel@vger.kernel.org, hayashibara.keiji@socionext.com, Kunihiko Hayashi Subject: [PATCH v2 2/3] ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs Date: Thu, 26 Jul 2018 16:09:59 +0900 Message-Id: <1532589000-19602-3-git-send-email-hayashibara.keiji@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532589000-19602-1-git-send-email-hayashibara.keiji@socionext.com> References: <1532589000-19602-1-git-send-email-hayashibara.keiji@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kunihiko Hayashi Add nodes of SPI controller for LD4, Pro4, sLD8, Pro5 and PXs2. Signed-off-by: Kunihiko Hayashi --- arch/arm/boot/dts/uniphier-ld4.dtsi | 11 +++++++++++ arch/arm/boot/dts/uniphier-pro4.dtsi | 11 +++++++++++ arch/arm/boot/dts/uniphier-pro5.dtsi | 22 ++++++++++++++++++++++ arch/arm/boot/dts/uniphier-pxs2.dtsi | 22 ++++++++++++++++++++++ arch/arm/boot/dts/uniphier-sld8.dtsi | 11 +++++++++++ 5 files changed, 77 insertions(+) -- 2.7.4 diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 37950ad..b7849be 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -63,6 +63,17 @@ cache-level = <2>; }; + spi: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 49539f0..4d20692 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -71,6 +71,17 @@ cache-level = <2>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 06c2cef..02d837d 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -156,6 +156,28 @@ cache-level = <3>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 641d961..15b4f75 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -164,6 +164,28 @@ cache-level = <2>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index e9b9b4f..83f832b 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -63,6 +63,17 @@ cache-level = <2>; }; + spi: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; From patchwork Thu Jul 26 07:10:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keiji Hayashibara X-Patchwork-Id: 142938 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp121591ljj; Thu, 26 Jul 2018 00:10:31 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd1vgSAj2R05tqQ5Q0jtotTJLUSSRdi9rUxJYZZv9Xr1ldNr7gmPg9QfDW09F+f16fbjhND X-Received: by 2002:a62:4b48:: with SMTP id y69-v6mr878757pfa.93.1532589031666; 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[209.132.180.67]) by mx.google.com with ESMTP id j184-v6si656930pge.607.2018.07.26.00.10.31; Thu, 26 Jul 2018 00:10:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729144AbeGZIZt (ORCPT + 31 others); Thu, 26 Jul 2018 04:25:49 -0400 Received: from mx.socionext.com ([202.248.49.38]:12191 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729075AbeGZIZs (ORCPT ); Thu, 26 Jul 2018 04:25:48 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 26 Jul 2018 16:10:20 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 11A191800A9; Thu, 26 Jul 2018 16:10:21 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 26 Jul 2018 16:10:21 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 6ECF71A120D; Thu, 26 Jul 2018 16:10:20 +0900 (JST) From: Keiji Hayashibara To: robh+dt@kernel.org, mark.rutland@arm.com, yamada.masahiro@socionext.com, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: masami.hiramatsu@linaro.org, jaswinder.singh@linaro.org, linux-kernel@vger.kernel.org, hayashibara.keiji@socionext.com, Kunihiko Hayashi Subject: [PATCH v2 3/3] arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3 Date: Thu, 26 Jul 2018 16:10:00 +0900 Message-Id: <1532589000-19602-4-git-send-email-hayashibara.keiji@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532589000-19602-1-git-send-email-hayashibara.keiji@socionext.com> References: <1532589000-19602-1-git-send-email-hayashibara.keiji@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kunihiko Hayashi Add nodes of SPI controller for UniPhier SoCs. Signed-off-by: Kunihiko Hayashi --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 22 ++++++++++++ arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 44 ++++++++++++++++++++++++ arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 22 ++++++++++++ 3 files changed, 88 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index d63b56e..0edab17 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -116,6 +116,28 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 0298bd0..1213101 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -222,6 +222,50 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi2: spi@54006200 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006200 0x100>; + interrupts = <0 229 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi3: spi@54006300 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006300 0x100>; + interrupts = <0 230 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi3>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 2a4cf42..5b40ec7 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -144,6 +144,28 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled";