From patchwork Thu Jun 10 13:57:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 457855 Delivered-To: patch@linaro.org Received: by 2002:a02:735a:0:0:0:0:0 with SMTP id a26csp494965jae; Thu, 10 Jun 2021 06:57:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAJYT58UnBgzA0KmEc9kwyKMMZsJivAC26Tvu3vewHxqn5BLhZEnT0DzKT/yGFV0hL67bb X-Received: by 2002:a17:906:22c8:: with SMTP id q8mr4514438eja.12.1623333463968; Thu, 10 Jun 2021 06:57:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623333463; cv=none; d=google.com; s=arc-20160816; b=R+Y4mfBlDLVKBvJ2d15C6MVmzxFDb/0KI93xuCNW9Ez2JYVA+OiybmW5SbfCYNBtmM nFgF14ah92FRuh0FP5TfptV8wOtEBJqJaeklfO3h7YLSrS6KaxoU3osDGm/bTgs42xcm UZmRV52ajuR7f2OUyjvj14jsBq872w1Qqi23T+8Obmu9e0PjvonMnBcF8afEhAKFifje R3UJqv/YD3AU7kE50NDuaVyBGkjFmGtpLvm/+uQowJQVh4E5u7QZwqHK3ju7WRxKyvfB Oi28nh1pSrNevQwg9e/opkTKZo1IUP63EbP+si6ro026+G6aV2nlf/qW9CFW6BlSPlPD 6HaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=MzDG35FD9VbNh3UGlrWmRodMCIla0xXJH4KqsHrlYHs=; b=0mmqb8cToMjEUaEQ+UBS53ye59zrE5nigzbcLdRBEoj+13ToDszOBAqY5Kuqx8pmuQ 86ZVZWfpXCgTW9VSCBw+Yw5P9Yl71GLU5pebkKc99qr4WkHVP9iLhPbsmtVVAXFev687 Dsm79FjzVOApcsEB6z+2pMdVDNO1tuUaRvzXC7ep/Xty0/LCcDrBx+g2ZhCb8srDF7yq RF3ilD4sFWvzReWnnfUjZlAnJV022xWm5kZFpzhhOBpD87f7JR+Bquwiel3mhdQDrqbB XlX4JdJ2IQSzZCEFtIVUrubCAqEriIMvkovPIYCiJGXBykq2FIUtCftzSihXOPaXFbqy 8q2Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id kg16si2150727ejc.751.2021.06.10.06.57.43; Thu, 10 Jun 2021 06:57:43 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230413AbhFJN7V (ORCPT + 7 others); Thu, 10 Jun 2021 09:59:21 -0400 Received: from foss.arm.com ([217.140.110.172]:60742 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230035AbhFJN7V (ORCPT ); Thu, 10 Jun 2021 09:59:21 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C6483106F; Thu, 10 Jun 2021 06:57:24 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EF5BD3F73D; Thu, 10 Jun 2021 06:57:23 -0700 (PDT) From: Sudeep Holla To: devicetree@vger.kernel.org, Rob Herring Cc: Sudeep Holla , Linus Walleij , Rob Herring Subject: [PATCH] dt-bindings: interrupt-controller: Convert ARM VIC to json-schema Date: Thu, 10 Jun 2021 14:57:17 +0100 Message-Id: <20210610135717.2782793-1-sudeep.holla@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the ARM VIC binding document to DT schema format using json-schema. Cc: Linus Walleij Cc: Rob Herring Signed-off-by: Sudeep Holla --- .../bindings/interrupt-controller/arm,vic.txt | 41 --------- .../interrupt-controller/arm,vic.yaml | 92 +++++++++++++++++++ 2 files changed, 92 insertions(+), 41 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml Hi Rob, This also helps to get rid of this warning. bus/arm,integrator-ap-lm.example.dt.yaml:0:0: /example-0/bus@c0000000/bus@c0000000/interrupt-controller@3000000: failed to match any schema with compatible: ['arm,pl192-vic'] Regards, Sudeep -- 2.25.1 Reviewed-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt deleted file mode 100644 index dd527216c5fb..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt +++ /dev/null @@ -1,41 +0,0 @@ -* ARM Vectored Interrupt Controller - -One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM -system for interrupt routing. For multiple controllers they can either be -nested or have the outputs wire-OR'd together. - -Required properties: - -- compatible : should be one of - "arm,pl190-vic" - "arm,pl192-vic" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : The number of cells to define the interrupts. Must be 1 as - the VIC has no configuration options for interrupt sources. The cell is a u32 - and defines the interrupt number. -- reg : The register bank for the VIC. - -Optional properties: - -- interrupts : Interrupt source for parent controllers if the VIC is nested. -- valid-mask : A one cell big bit mask of valid interrupt sources. Each bit - represents single interrupt source, starting from source 0 at LSb and ending - at source 31 at MSb. A bit that is set means that the source is wired and - clear means otherwise. If unspecified, defaults to all valid. -- valid-wakeup-mask : A one cell big bit mask of interrupt sources that can be - configured as wake up source for the system. Order of bits is the same as for - valid-mask property. A set bit means that this interrupt source can be - configured as a wake up source for the system. If unspecied, defaults to all - interrupt sources configurable as wake up sources. - -Example: - - vic0: interrupt-controller@60000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x60000 0x1000>; - - valid-mask = <0xffffff7f>; - valid-wakeup-mask = <0x0000ff7f>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml new file mode 100644 index 000000000000..aeadbd2d9398 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Vectored Interrupt Controller + +maintainers: + - Rob Herring + +description: |+ + One or more Vectored Interrupt Controllers (VIC's) can be connected in an + ARM system for interrupt routing. For multiple controllers they can either + be nested or have the outputs wire-OR'd together. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + oneOf: + - const: arm,pl190-vic + - const: arm,pl192-vic + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + description: + The number of cells to define the interrupts. It must be 1 as the + VIC has no configuration options for interrupt sources. The single + cell defines the interrupt number. + + reg: + description: The register bank for the VIC. + maxItems: 1 + + interrupts: + description: + Interrupt source for the parent interrupt controller if the VIC + is nested. + maxItems: 1 + + interrupts-extended: + description: + Interrupt source for the parent interrupt controllers if the VIC + is nested. + maxItems: 1 + + valid-mask: + description: + A one cell big bit mask of valid interrupt sources. Each bit + represents single interrupt source, starting from source 0 at + LSb and ending at source 31 at MSb. A bit that is set means + that the source is wired and clear means otherwise. If unspecified, + defaults to all valid. + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + + valid-wakeup-mask: + description: + A one cell big bit mask of interrupt sources that can be configured + as wake up source for the system. Order of bits is the same as for + valid-mask property. A set bit means that this interrupt source + can be configured as a wake up source for the system. If unspecied, + defaults to all interrupt sources configurable as wake up sources. + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + // GICv1 + vic0: interrupt-controller@60000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x60000 0x1000>; + + valid-mask = <0xffffff7f>; + valid-wakeup-mask = <0x0000ff7f>; + }; + +...