From patchwork Fri Jul 27 18:45:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 143092 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1167739ljj; Fri, 27 Jul 2018 11:48:02 -0700 (PDT) X-Google-Smtp-Source: AAOMgpc2xL+GIgfVczNbgr9qk59ec0Ijtwoxr6PMlZMJA11uGTRnJbKy1nT0VGJ62Jri1nZ40nZx X-Received: by 2002:a65:428b:: with SMTP id j11-v6mr7004733pgp.200.1532717282285; Fri, 27 Jul 2018 11:48:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532717282; cv=none; d=google.com; s=arc-20160816; b=wz7BWy1hJAAUeH35LaqlFmP0/3hD3JWeEYTnCKvkR7p8oj9Fd76rEgyNDa4vmUZMdS OLPhxPJMN+o/hmZl5/f4dpSdSOoWkXX72nVG/jMSQGUNttrkr/KCPDZae4KJCq1hiafZ 9PsTP9kN76aL5P1lvb+OVsZ4FQu1e1CloZdaknPWEX09CWU4Xv1bZmYBs+HiLCMdkOVA 6uKTKkdnKdzYunTnCSS9zZGQF10qcgeDnCZeePyFSDQU2Pf98RqVfMTsdkMSMAtvWNSs w01qJIhf6jJb7EMG2gEZSZHPchjctig9CwMpoGNpagfGTwdFcL9BBRQ7vGUvOFPdELve C1Lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=DwKugHCgj7TpoVeG3f0Y/2LdewKxgh4h4yjO9QRfsGI=; b=MNfTLIgCvgtMAvnAZHjC8ekwJa8RHLgBknMqoHwYWc7MqKK0ouc9iDryfHSqqrZKkg 0/KGkmpAA8VNb8PckBlVMOBwNmazDzOfXprEhvjth3eA7QVAhK3gW0CJLn2z1Sw3Mrzq hZOuazG2VFwgeDA4JdIwZP1H0W9yzakfrw7NM7Ao1gtiHmY0jE3FKLpE12a5mvmu+5/y 78zVTNZE3wIEg1vxCle2tn7Fjkw7YP3uWdIfdd0iSwfWqkiZCT7fIhhJXh3F6uJlCzU1 vSQwi/i7QTPmoUCzfbsBPrzK8AguFMsvo0Muawsaw+FUkLl6xzTzK4S1ND59ICxk7C20 u5ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="KAOQ9G5/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q18-v6si3923720plr.134.2018.07.27.11.48.02; Fri, 27 Jul 2018 11:48:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="KAOQ9G5/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389263AbeG0ULE (ORCPT + 31 others); Fri, 27 Jul 2018 16:11:04 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:36548 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389244AbeG0ULE (ORCPT ); Fri, 27 Jul 2018 16:11:04 -0400 Received: by mail-pf1-f196.google.com with SMTP id d14-v6so2027010pfo.3 for ; Fri, 27 Jul 2018 11:47:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DwKugHCgj7TpoVeG3f0Y/2LdewKxgh4h4yjO9QRfsGI=; b=KAOQ9G5/n0DYQdaQvRpc4Ejd/NG+ar4PlWyFTAr6EXs/oJFjvOLClwfOdwkBmnwcpm X9bOulqroRDdIAr3lbnW4a4go8g3/i1R2TTNhrEnCNwLbtWYqTJeO2KN2nQgtWbOVTST eR4SZe/Y5LQB5U/+FF7+DgQtsocAdef2k6cdI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DwKugHCgj7TpoVeG3f0Y/2LdewKxgh4h4yjO9QRfsGI=; b=ijTL3g4s97vJsb44wOiMPMDzEphG9QBLuvu+9lyBLn/nKDpgzzkOjesCSVZkZIj/CE N2yPBDCEi3HVDyHj55uWIvPFV4dnfByAFvgQbNsFLn6c73N0DAAebJ9dSos1jq4MIVB2 Gu94vshk1A4QTfHba+V2d8mWVJkrAqJn2BNz7VPkEysnpAjskNH/K2aATgmwhD4hilgz JvTwPZqz+ZW3HFj2yxxtv33T76Bn+b7MW+mb42K9VqbFf5CDQ1NTdst2990dBzqg+n2U a/toWPciZN2ZytUcz4I5Id0UlGJSYDidtY0taAQDLhxT+UDSWMOsYP1XSTbC5ci6aSMH jyjQ== X-Gm-Message-State: AOUpUlELA+I/ntu9aByI6t9gFuZiYmdie0Nn7lw4CcuWbPa1VL0fZcey O4zGV5FN5CkIDXB5s19WYtlA X-Received: by 2002:a63:2ec3:: with SMTP id u186-v6mr7085281pgu.225.1532717274622; Fri, 27 Jul 2018 11:47:54 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7308:c330:41b:cc59:b463:ec7b]) by smtp.gmail.com with ESMTPSA id t69-v6sm13817959pfj.7.2018.07.27.11.47.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 11:47:54 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org Cc: linux-clk@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, pn@denx.de, edgar.righi@lsitec.org.br, sravanhome@gmail.com, Manivannan Sadhasivam Subject: [PATCH 6/9] arm64: dts: actions: Add Reset Controller support for S900 SoC Date: Sat, 28 Jul 2018 00:15:24 +0530 Message-Id: <20180727184527.13287-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180727184527.13287-1-manivannan.sadhasivam@linaro.org> References: <20180727184527.13287-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add reset controller property and bindings header for the Actions Semi S900 SoC DTS. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s900.dtsi | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index aa3a49b0d646..4fbb39fd7971 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { compatible = "actions,s900"; @@ -172,6 +173,7 @@ reg = <0x0 0xe0160000 0x0 0x1000>; clocks = <&hosc>, <&losc>; #clock-cells = <1>; + #reset-cells = <1>; }; pinctrl: pinctrl@e01b0000 { From patchwork Fri Jul 27 18:45:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 143093 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1167860ljj; Fri, 27 Jul 2018 11:48:12 -0700 (PDT) X-Google-Smtp-Source: AAOMgpehNOUsjhZwZltRkyr16aceoMzgalTxT5cP+YCFekqMvP4HBKV3TUXOwa/NOqEdaIoFFNqi X-Received: by 2002:a17:902:b412:: with SMTP id x18-v6mr5160880plr.203.1532717292677; Fri, 27 Jul 2018 11:48:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532717292; cv=none; d=google.com; s=arc-20160816; b=zsu7IdZ2hqC6KQuKuqJY+u5LjE/4lyc8bTULTub0bY40T5RUOSugQL3hSZfguyu4VF FmO87RHt4XF/AntdnL/k6LcoqRw2tfI/VtV2e57hrZfyylGeD8j/fKUQDxO4j6kEbCVO hlPfE9sPOWrTIivfNOQFJl3R26w6UShLlrrUQw8HdwWQWtuV/efmT02Wh1I++RISr5L/ GgoFNLkl/Ux1lfCq8Obz1i3otjhsPEqFWhkiKu//jjjx+7T36sxXG/eocUM3esDdB790 EzPNVbQPMrgoqQq7u5QH2M+7qsRDbPyS+nr+t+Uksd7ahPe9//pr/4lFYCoeX/eWXxQQ b4aA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=5CIXTx7NCxUlFat9MTaYTt8/hPDWpQD7jz34bQ1ARxs=; b=pxbskKHJLssmQKYJZoDyp7Dlb1+aCIrrFACgF7IxEQYiIpypulV1VpZzgA8ayeOfkv cOmpt/2Ms4Jdu54LOUXeDJlBF/pdaotV8EALQtcbDm7seizzCP6gnKe/M1wMW0N6Ndoc uETU3QfZXK2UtwV5TKQUh6MW51LDSF0h7PUNjr0IpGIIqYbj8pnKI1wluN7uk/7nIgq0 ZDdaeMN+oBvuNu+HWIP3CsRA55K1YlHCC9LVzSCXswTHSDwgM6gERUkJpAdrMi/Ivf41 kvXdTStKc4/OD3Gi93WBG/yHGgT/76t6ZePPFYo6fs7tBlXInZ2q4G2EJrVFoNObGaJi E4Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FLnLkzID; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Kconfig | 1 + drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-common.h | 2 + drivers/clk/actions/owl-reset.c | 72 ++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-reset.h | 32 ++++++++++++++ 5 files changed, 108 insertions(+) create mode 100644 drivers/clk/actions/owl-reset.c create mode 100644 drivers/clk/actions/owl-reset.h -- 2.17.1 diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig index dc38c85a4833..04f0a6355726 100644 --- a/drivers/clk/actions/Kconfig +++ b/drivers/clk/actions/Kconfig @@ -2,6 +2,7 @@ config CLK_ACTIONS bool "Clock driver for Actions Semi SoCs" depends on ARCH_ACTIONS || COMPILE_TEST select REGMAP_MMIO + select RESET_CONTROLLER default ARCH_ACTIONS if CLK_ACTIONS diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index 78c17d56f991..ccfdf9781cef 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -7,6 +7,7 @@ clk-owl-y += owl-divider.o clk-owl-y += owl-factor.o clk-owl-y += owl-composite.o clk-owl-y += owl-pll.o +clk-owl-y += owl-reset.o # SoC support obj-$(CONFIG_CLK_OWL_S700) += owl-s700.o diff --git a/drivers/clk/actions/owl-common.h b/drivers/clk/actions/owl-common.h index 56f01f7774aa..4dc7f286831f 100644 --- a/drivers/clk/actions/owl-common.h +++ b/drivers/clk/actions/owl-common.h @@ -26,6 +26,8 @@ struct owl_clk_desc { struct owl_clk_common **clks; unsigned long num_clks; struct clk_hw_onecell_data *hw_clks; + struct owl_reset_map *resets; + unsigned long num_resets; struct regmap *regmap; }; diff --git a/drivers/clk/actions/owl-reset.c b/drivers/clk/actions/owl-reset.c new file mode 100644 index 000000000000..91b161cc68de --- /dev/null +++ b/drivers/clk/actions/owl-reset.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// +// Actions Semi Owl SoCs Reset Management Unit driver +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include +#include +#include + +#include "owl-reset.h" + +static int owl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct owl_reset *reset = to_owl_reset(rcdev); + const struct owl_reset_map *map = &reset->reset_map[id]; + u32 reg; + + regmap_read(reset->regmap, map->reg, ®); + regmap_write(reset->regmap, map->reg, reg & ~map->bit); + + return 0; +} + +static int owl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct owl_reset *reset = to_owl_reset(rcdev); + const struct owl_reset_map *map = &reset->reset_map[id]; + u32 reg; + + regmap_read(reset->regmap, map->reg, ®); + regmap_write(reset->regmap, map->reg, reg | map->bit); + + return 0; +} + +static int owl_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + owl_reset_assert(rcdev, id); + udelay(1); + owl_reset_deassert(rcdev, id); + + return 0; +} + +static int owl_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct owl_reset *reset = to_owl_reset(rcdev); + const struct owl_reset_map *map = &reset->reset_map[id]; + u32 reg; + + regmap_read(reset->regmap, map->reg, ®); + + /* + * The reset control API expects 0 if reset is not asserted, + * which is the opposite of what our hardware uses. + */ + return !(map->bit & reg); +} + +const struct reset_control_ops owl_reset_ops = { + .assert = owl_reset_assert, + .deassert = owl_reset_deassert, + .reset = owl_reset_reset, + .status = owl_reset_status, +}; diff --git a/drivers/clk/actions/owl-reset.h b/drivers/clk/actions/owl-reset.h new file mode 100644 index 000000000000..1a5e987ba99b --- /dev/null +++ b/drivers/clk/actions/owl-reset.h @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// +// Actions Semi Owl SoCs Reset Management Unit driver +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_RESET_H_ +#define _OWL_RESET_H_ + +#include +#include + +struct owl_reset_map { + u16 reg; + u32 bit; +}; + +struct owl_reset { + struct reset_controller_dev rcdev; + struct owl_reset_map *reset_map; + struct regmap *regmap; +}; + +static inline struct owl_reset *to_owl_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct owl_reset, rcdev); +} + +extern const struct reset_control_ops owl_reset_ops; + +#endif /* _OWL_RESET_H_ */