From patchwork Thu Aug 2 14:44:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 143344 Delivered-To: patches@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2252028ljj; Thu, 2 Aug 2018 07:44:34 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfEKNjExgFdGnL6chLUHwOkz/D2oid4b/ywalMJZ4Q0mpRy5vY+oGk55hvvpRvgeEGLYcPd X-Received: by 2002:adf:8f2e:: with SMTP id p43-v6mr2193845wrb.193.1533221074116; Thu, 02 Aug 2018 07:44:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533221074; cv=none; d=google.com; s=arc-20160816; b=agEMN1jZuYZFE3OrbI9MLhSkKddGptqjLARATyOPOzPHpiWC/PPfOeXWdyrmXlK3Yn uKjtVHP7JvdgVTSvc+16LVncPj68xSLV1xfSt6tf9HwUUXnKoP+Lsb0G9pnfbj/Tt7fT RwD3tdC8TdTrmXZUJTg9myaGxq9Fbos1nmoUIzadCUOoemwv3RIbElJWPBkocmi9ec9b 5xvjfNY0rNxR88DV+Cmb04y2u2tk6Tk77HslbYNJnZUXGbQrswY7VfLxgPs5lvupwTjr UsqXCroXFsvWPGWzZg02B7VFGBYe1RzhkVPDdQxSB6NZsIdAg3MMlzDq9g9iXTMR1jSs 3bmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=lNhYLOD0+nEvRhX1fFkv2OdPGcyBEU+mSG+5Gdj6pLI=; b=0k7U0ad+B3HUfCURyE9rxtEIh7Z5aJM4Aku2l+wpYLTHDv4w5oKZNhAC8ThXrF71+l jGEgt71a7BYKJx/ND8MTqdQd0kdl/2Qqu8dPbkI/LbmRaolWGP62VNxs+TDRCprjsVH2 7zGTgxNHCuFcKgQYVmoyTwUCjqnQxbuKUs81TzFNIUtMwUhSSvuyk75QWt1+//QDrI8I yxLIomeLgQSQ6Lj7FEletgV/RdPsVJnekDMh5Xw2AwqjGLTMknTNVLjJe2Qu2Qj9CZ2L OfO9Egs/Als1FJu4IzpGOnanEq1gKMSG4Ju1RETKh7XC6nWyJUw8dt+2tDbKCH6ZCa5g JlKg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id n185-v6si1476900wmb.30.2018.08.02.07.44.33 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 02 Aug 2018 07:44:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1flEq8-0006JD-5y; Thu, 02 Aug 2018 15:44:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-ppc@nongnu.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , David Gibson , Alexander Graf Subject: [PATCH 1/3] hw/ppc/prep: Remove ifdeffed-out stub of XCSR code Date: Thu, 2 Aug 2018 15:44:28 +0100 Message-Id: <20180802144430.13870-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180802144430.13870-1-peter.maydell@linaro.org> References: <20180802144430.13870-1-peter.maydell@linaro.org> The prep machine has some code which is stubs of accessors for XCSR registers. This has been disabled via #if 0 since commit b6b8bd1819ff in 2004, and doesn't have any actual interesting content. It also uses the deprecated old_mmio accessor functions. Remove it entirely. Signed-off-by: Peter Maydell --- hw/ppc/prep.c | 97 +++------------------------------------------------ 1 file changed, 4 insertions(+), 93 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Hervé Poussineau diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 3401570d981..b26138e5c47 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -78,94 +78,6 @@ static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; /* ISA IO ports bridge */ #define PPC_IO_BASE 0x80000000 -/* PowerPC control and status registers */ -#if 0 // Not used -static struct { - /* IDs */ - uint32_t veni_devi; - uint32_t revi; - /* Control and status */ - uint32_t gcsr; - uint32_t xcfr; - uint32_t ct32; - uint32_t mcsr; - /* General purpose registers */ - uint32_t gprg[6]; - /* Exceptions */ - uint32_t feen; - uint32_t fest; - uint32_t fema; - uint32_t fecl; - uint32_t eeen; - uint32_t eest; - uint32_t eecl; - uint32_t eeint; - uint32_t eemck0; - uint32_t eemck1; - /* Error diagnostic */ -} XCSR; - -static void PPC_XCSR_writeb (void *opaque, - hwaddr addr, uint32_t value) -{ - printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, - value); -} - -static void PPC_XCSR_writew (void *opaque, - hwaddr addr, uint32_t value) -{ - printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, - value); -} - -static void PPC_XCSR_writel (void *opaque, - hwaddr addr, uint32_t value) -{ - printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, - value); -} - -static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr) -{ - uint32_t retval = 0; - - printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, - retval); - - return retval; -} - -static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr) -{ - uint32_t retval = 0; - - printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, - retval); - - return retval; -} - -static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr) -{ - uint32_t retval = 0; - - printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, - retval); - - return retval; -} - -static const MemoryRegionOps PPC_XCSR_ops = { - .old_mmio = { - .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, - .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, - }, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -#endif - /* Fake super-io ports for PREP platform (Intel 82378ZB) */ typedef struct sysctrl_t { qemu_irq reset_irq; @@ -648,11 +560,10 @@ static void ppc_prep_init(MachineState *machine) portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep"); portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0); - /* PowerPC control and status register group */ -#if 0 - memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); - memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); -#endif + /* + * PowerPC control and status register group: unimplemented, + * would be at address 0xFEFF0000. + */ if (machine_usb(machine)) { pci_create_simple(pci_bus, -1, "pci-ohci"); From patchwork Thu Aug 2 14:44:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 143346 Delivered-To: patches@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2252124ljj; Thu, 2 Aug 2018 07:44:38 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcU8c8Jthy2H6C/0jsFEeQKWI26OjXBDrb4dq4ZImcRRZU2TExo03n165Oh/wmOpYxCne/X X-Received: by 2002:aa7:8307:: with SMTP id t7-v6mr3326847pfm.81.1533221078338; Thu, 02 Aug 2018 07:44:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533221078; cv=none; d=google.com; s=arc-20160816; b=iIE9HNG6RZaN8p65vH5XWz6MNYye2agSCfLoPzB3QvGYldvJkma9gSUPMBisBJYEWl ZmIkb0b1wvaBzNeZN9sqbBP5NsRdlvcz/gBnOSuttZNtpsCf1fP2T5zuD/KRhvUFuOFz x1CcOW682tSZoknAlSXCbqFAQN/zwZbbTEmZxOiiOTdkHeCoIPVWFSGQeEPMGzo+uoyc a3MMSCcDaey5eO4FwpKIXAo0VX7kKXOHGIgkKSHHcEMfHqCD6am7gVFXPE95O5UFTILW Yz/RLROPNTLGkBRkg7mljQjviVlajWwwEOFXWffX2TDw5Wu/fIobwlVyGyh15uV4i/Rh G/GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=yFpCd++udVm3ulh0FMbqgFpJVcbcC06Eeu0/NcjQs1U=; b=0rlrgUlkH6xIYoEvSQ96vSlJbQc6T9Wq2KUr7RYFzqluNUnKNqnnsBWLxMJ6KAkn+x WNyzUq4IhEzarWySd3hxIWemRmaLuZ596clW6YkvcGQlfPldAxEycK9+wSF9mgtgvRWf 1HYkNaBBihJ5ZXt35z0rWLJYPHbEagzBqMIjpB/qcdCJ2OJvEWE7caCZMwbQY4xrkwAP P5oa9D5J8eczGjNyh+kifY2bRJDiUZsJc7wWGkyo1BASCjFSHO9FD6vkoKM5TAQtID5B 7jWNNGavJtdf45BsLcneqjUzvkxitjPxecxXdhQmsMDpzmL2I7xLnCOfYdpTSGsLQQa4 9lIA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id c1-v6si1532665pla.98.2018.08.02.07.44.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 02 Aug 2018 07:44:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1flEq8-0006JQ-Qb; Thu, 02 Aug 2018 15:44:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-ppc@nongnu.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , David Gibson , Alexander Graf Subject: [PATCH 2/3] hw/ppc/ppc_boards: Don't use old_mmio for ref405ep_fpga Date: Thu, 2 Aug 2018 15:44:29 +0100 Message-Id: <20180802144430.13870-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180802144430.13870-1-peter.maydell@linaro.org> References: <20180802144430.13870-1-peter.maydell@linaro.org> Switch the ref405ep_fpga device away from using the old_mmio MemoryRegion accessors. Signed-off-by: Peter Maydell --- hw/ppc/ppc405_boards.c | 60 +++++++----------------------------------- 1 file changed, 10 insertions(+), 50 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 70111075b33..f5a9c24b6ce 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -66,7 +66,7 @@ struct ref405ep_fpga_t { uint8_t reg1; }; -static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) +static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size) { ref405ep_fpga_t *fpga; uint32_t ret; @@ -87,8 +87,8 @@ static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) return ret; } -static void ref405ep_fpga_writeb (void *opaque, - hwaddr addr, uint32_t value) +static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { ref405ep_fpga_t *fpga; @@ -105,54 +105,14 @@ static void ref405ep_fpga_writeb (void *opaque, } } -static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr) -{ - uint32_t ret; - - ret = ref405ep_fpga_readb(opaque, addr) << 8; - ret |= ref405ep_fpga_readb(opaque, addr + 1); - - return ret; -} - -static void ref405ep_fpga_writew (void *opaque, - hwaddr addr, uint32_t value) -{ - ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); -} - -static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr) -{ - uint32_t ret; - - ret = ref405ep_fpga_readb(opaque, addr) << 24; - ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; - ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; - ret |= ref405ep_fpga_readb(opaque, addr + 3); - - return ret; -} - -static void ref405ep_fpga_writel (void *opaque, - hwaddr addr, uint32_t value) -{ - ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); -} - static const MemoryRegionOps ref405ep_fpga_ops = { - .old_mmio = { - .read = { - ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, - }, - .write = { - ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, - }, - }, - .endianness = DEVICE_NATIVE_ENDIAN, + .read = ref405ep_fpga_readb, + .write = ref405ep_fpga_writeb, + .impl.min_access_size = 1, + .impl.max_access_size = 1, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .endianness = DEVICE_BIG_ENDIAN, }; static void ref405ep_fpga_reset (void *opaque) From patchwork Thu Aug 2 14:44:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 143347 Delivered-To: patches@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2252128ljj; Thu, 2 Aug 2018 07:44:38 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd4o+/p9keTdN4N7wGcpKqp/WQMhgGCxyCQ4YIKiCAwCCo4G/4gZFLE53yyKoj1LMWqfT04 X-Received: by 2002:a63:9e0a:: with SMTP id s10-v6mr3113803pgd.326.1533221078271; Thu, 02 Aug 2018 07:44:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533221078; cv=none; d=google.com; s=arc-20160816; b=wKLXFKudrdWL5V5OEHi/Gg6SgO3gOT5xOohlL9sZzZRUacqxbUwCb5ko2BYl7RVy9H 2BSg5TXw7R7O0tACfYh/F9MEXuZvItpkbqEWHtCsjpzqOjhmDEdUIZ09Q2IullI2to4R /8SMVS1eGuGzFwFsNXUZZZCDPycY7Egd81OJpk+X11io5oz6NNNmzxz7+zEkZcCUZyN1 VvyXO/U6vNOqELAPI+0IGSpfjhtX6ceJbGAJRt+1a/YhRp0fxJZLHU+bnNtpJHly+b/G pWRH03FCFXjUv/ivShP7gLAefUMyOlW4yvNc8N5iQRD+TOPlqo24UCn7Dh3RF6yEGWPn S1xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=34A3JR4CCw5LkTSCDJWUCimvPeuKN1vcriOLseh/WRc=; b=JDZOI3FtTOJr4SPQV+qo8/jKPJngm5a8smYXok7ZfLoQR/J9BKuBDoUokG2LuAj2Th Ra+J/UtDRZC40YAEkOuRXm+nOftMfVXbeTH12ieEptpJNgW/ck/ZYeaJCVxbeDRo7Qhh S3ErX1yc57ChyFQF3D54Wh5HOsUDbftX2HQbsmkVlCsFLUkjZ9mdsSKfuXqmK3/8COTI uDn/B9F3swXr0Nb8zXnKO5bBHBVrV45O3dQM867/XzMSZ4N0JJVbbVo2BDKL3KoHxHLv I9H0wd/BHMmNVouQ/LVr8hDoOus8MyLihxBkt7MSdNLPKqGHnQV7ZzFr9pa6NAZ78ACE MQaQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id t9-v6si2328527pgr.244.2018.08.02.07.44.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 02 Aug 2018 07:44:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1flEq9-0006Jd-FK; Thu, 02 Aug 2018 15:44:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-ppc@nongnu.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , David Gibson , Alexander Graf Subject: [PATCH 3/3] hw/ppc/ppc405_uc: Convert away from old_mmio Date: Thu, 2 Aug 2018 15:44:30 +0100 Message-Id: <20180802144430.13870-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180802144430.13870-1-peter.maydell@linaro.org> References: <20180802144430.13870-1-peter.maydell@linaro.org> Convert the devices in ppc405_uc away from using the old_mmio MemoryRegion accessors: * opba's 32-bit and 16-bit accessors were just calling the 8-bit accessors and assembling a big-endian order number, which we can do by setting the .impl.max_access_size to 1 and the endianness to DEVICE_BIG_ENDIAN, and letting the core memory code do the assembly * ppc405_gpio's accessors were all just stubs * ppc4xx_gpt's 8-bit and 16-bit accessors were treating the access as invalid, which we can do by setting the .valid.min_access_size and .valid.max_access_size fields Signed-off-by: Peter Maydell --- hw/ppc/ppc405_uc.c | 173 +++++++-------------------------------------- 1 file changed, 25 insertions(+), 148 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 4bd9fbcc1ef..5c58415cf1f 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -283,7 +283,7 @@ struct ppc4xx_opba_t { uint8_t pr; }; -static uint32_t opba_readb (void *opaque, hwaddr addr) +static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) { ppc4xx_opba_t *opba; uint32_t ret; @@ -307,8 +307,8 @@ static uint32_t opba_readb (void *opaque, hwaddr addr) return ret; } -static void opba_writeb (void *opaque, - hwaddr addr, uint32_t value) +static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { ppc4xx_opba_t *opba; @@ -328,61 +328,14 @@ static void opba_writeb (void *opaque, break; } } - -static uint32_t opba_readw (void *opaque, hwaddr addr) -{ - uint32_t ret; - -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - ret = opba_readb(opaque, addr) << 8; - ret |= opba_readb(opaque, addr + 1); - - return ret; -} - -static void opba_writew (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - opba_writeb(opaque, addr, value >> 8); - opba_writeb(opaque, addr + 1, value); -} - -static uint32_t opba_readl (void *opaque, hwaddr addr) -{ - uint32_t ret; - -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - ret = opba_readb(opaque, addr) << 24; - ret |= opba_readb(opaque, addr + 1) << 16; - - return ret; -} - -static void opba_writel (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - opba_writeb(opaque, addr, value >> 24); - opba_writeb(opaque, addr + 1, value >> 16); -} - static const MemoryRegionOps opba_ops = { - .old_mmio = { - .read = { opba_readb, opba_readw, opba_readl, }, - .write = { opba_writeb, opba_writew, opba_writel, }, - }, - .endianness = DEVICE_NATIVE_ENDIAN, + .read = opba_readb, + .write = opba_writeb, + .impl.min_access_size = 1, + .impl.max_access_size = 1, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .endianness = DEVICE_BIG_ENDIAN, }; static void ppc4xx_opba_reset (void *opaque) @@ -750,65 +703,27 @@ struct ppc405_gpio_t { uint32_t isr1l; }; -static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr) +static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) { #ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); + printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); #endif return 0; } -static void ppc405_gpio_writeb (void *opaque, - hwaddr addr, uint32_t value) +static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { #ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif -} - -static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - - return 0; -} - -static void ppc405_gpio_writew (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif -} - -static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - - return 0; -} - -static void ppc405_gpio_writel (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); + printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", + __func__, addr, size, value); #endif } static const MemoryRegionOps ppc405_gpio_ops = { - .old_mmio = { - .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, }, - .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, }, - }, + .read = ppc405_gpio_read, + .write = ppc405_gpio_write, .endianness = DEVICE_NATIVE_ENDIAN, }; @@ -1017,44 +932,6 @@ struct ppc4xx_gpt_t { uint32_t mask[5]; }; -static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr) -{ -#ifdef DEBUG_GPT - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - /* XXX: generate a bus fault */ - return -1; -} - -static void ppc4xx_gpt_writeb (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - /* XXX: generate a bus fault */ -} - -static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr) -{ -#ifdef DEBUG_GPT - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - /* XXX: generate a bus fault */ - return -1; -} - -static void ppc4xx_gpt_writew (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - /* XXX: generate a bus fault */ -} - static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) { /* XXX: TODO */ @@ -1107,7 +984,7 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) /* XXX: TODO */ } -static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr) +static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) { ppc4xx_gpt_t *gpt; uint32_t ret; @@ -1162,8 +1039,8 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr) return ret; } -static void ppc4xx_gpt_writel (void *opaque, - hwaddr addr, uint32_t value) +static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { ppc4xx_gpt_t *gpt; int idx; @@ -1225,10 +1102,10 @@ static void ppc4xx_gpt_writel (void *opaque, } static const MemoryRegionOps gpt_ops = { - .old_mmio = { - .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, }, - .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, }, - }, + .read = ppc4xx_gpt_read, + .write = ppc4xx_gpt_write, + .valid.min_access_size = 4, + .valid.max_access_size = 4, .endianness = DEVICE_NATIVE_ENDIAN, };