From patchwork Thu Jun 17 19:09:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 462348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8973AC49EA2 for ; Thu, 17 Jun 2021 19:09:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7324F60FE9 for ; Thu, 17 Jun 2021 19:09:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232597AbhFQTL2 (ORCPT ); Thu, 17 Jun 2021 15:11:28 -0400 Received: from mail.bugwerft.de ([46.23.86.59]:37024 "EHLO mail.bugwerft.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231807AbhFQTL2 (ORCPT ); Thu, 17 Jun 2021 15:11:28 -0400 Received: from hq-00021.fritz.box (p57bc9ba2.dip0.t-ipconnect.de [87.188.155.162]) by mail.bugwerft.de (Postfix) with ESMTPSA id A27BA4C009D; Thu, 17 Jun 2021 19:09:18 +0000 (UTC) From: Daniel Mack To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, kuninori.morimoto.gx@renesas.com, mturquette@baylibre.com, sboyd@kernel.org, Daniel Mack , Rob Herring Subject: [PATCH v3 1/9] dt-bindings: clock: convert cs2000-cp bindings to yaml Date: Thu, 17 Jun 2021 21:09:04 +0200 Message-Id: <20210617190912.262809-2-daniel@zonque.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617190912.262809-1-daniel@zonque.org> References: <20210617190912.262809-1-daniel@zonque.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The original author of the file was added as maintainer. Signed-off-by: Daniel Mack Reviewed-by: Rob Herring --- .../bindings/clock/cirrus,cs2000-cp.yaml | 63 +++++++++++++++++++ .../devicetree/bindings/clock/cs2000-cp.txt | 22 ------- 2 files changed, 63 insertions(+), 22 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml delete mode 100644 Documentation/devicetree/bindings/clock/cs2000-cp.txt diff --git a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml new file mode 100644 index 000000000000..379a8bab49ca --- /dev/null +++ b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Binding CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier + +maintainers: + - Kuninori Morimoto + +description: | + The CS2000-CP is an extremely versatile system clocking device that + utilizes a programmable phase lock loop. + + Link: https://www.cirrus.com/products/cs2000/ + +properties: + compatible: + enum: + - cirrus,cs2000-cp + + clocks: + description: + Common clock binding for CLK_IN, XTI/REF_CLK + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: clk_in + - const: ref_clk + + '#clock-cells': + const: 0 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + i2c@0 { + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&rcar_sound 0>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/cs2000-cp.txt b/Documentation/devicetree/bindings/clock/cs2000-cp.txt deleted file mode 100644 index 54e6df0bee8a..000000000000 --- a/Documentation/devicetree/bindings/clock/cs2000-cp.txt +++ /dev/null @@ -1,22 +0,0 @@ -CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier - -Required properties: - -- compatible: "cirrus,cs2000-cp" -- reg: The chip select number on the I2C bus -- clocks: common clock binding for CLK_IN, XTI/REF_CLK -- clock-names: CLK_IN : clk_in, XTI/REF_CLK : ref_clk -- #clock-cells: must be <0> - -Example: - -&i2c2 { - ... - cs2000: clk_multiplier@4f { - #clock-cells = <0>; - compatible = "cirrus,cs2000-cp"; - reg = <0x4f>; - clocks = <&rcar_sound 0>, <&x12_clk>; - clock-names = "clk_in", "ref_clk"; - }; -}; From patchwork Thu Jun 17 19:09:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 463271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5732C49EA2 for ; Thu, 17 Jun 2021 19:09:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C6310613E7 for ; Thu, 17 Jun 2021 19:09:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231807AbhFQTLf (ORCPT ); Thu, 17 Jun 2021 15:11:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231379AbhFQTLa (ORCPT ); Thu, 17 Jun 2021 15:11:30 -0400 Received: from mail.bugwerft.de (mail.bugwerft.de [IPv6:2a03:6000:1011::59]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 11E3CC061574; Thu, 17 Jun 2021 12:09:21 -0700 (PDT) Received: from hq-00021.fritz.box (p57bc9ba2.dip0.t-ipconnect.de [87.188.155.162]) by mail.bugwerft.de (Postfix) with ESMTPSA id 111A34C0879; Thu, 17 Jun 2021 19:09:19 +0000 (UTC) From: Daniel Mack To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, kuninori.morimoto.gx@renesas.com, mturquette@baylibre.com, sboyd@kernel.org, Daniel Mack Subject: [PATCH v3 2/9] dt-bindings: clock: cs2000-cp: Document aux-output-source Date: Thu, 17 Jun 2021 21:09:05 +0200 Message-Id: <20210617190912.262809-3-daniel@zonque.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617190912.262809-1-daniel@zonque.org> References: <20210617190912.262809-1-daniel@zonque.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This new optional property can be used to control the function of the auxiliary output pin. Introduce a new dt-bindings include file that contains the numerical values. Signed-off-by: Daniel Mack Reviewed-by: Rob Herring --- .../bindings/clock/cirrus,cs2000-cp.yaml | 14 ++++++++++++++ include/dt-bindings/clock/cirrus,cs2000-cp.h | 14 ++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 include/dt-bindings/clock/cirrus,cs2000-cp.h diff --git a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml index 379a8bab49ca..79b90500f6ac 100644 --- a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml +++ b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml @@ -37,6 +37,17 @@ properties: reg: maxItems: 1 + cirrus,aux-output-source: + description: + Specifies the function of the auxiliary clock output pin + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input + - 1 # CS2000CP_AUX_OUTPUT_CLK_IN: clk_in input + - 2 # CS2000CP_AUX_OUTPUT_CLK_OUT: clk_out output + - 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status + default: 0 + required: - compatible - reg @@ -48,6 +59,8 @@ additionalProperties: false examples: - | + #include + i2c@0 { reg = <0x0 0x100>; #address-cells = <1>; @@ -59,5 +72,6 @@ examples: reg = <0x4f>; clocks = <&rcar_sound 0>, <&x12_clk>; clock-names = "clk_in", "ref_clk"; + cirrus,aux-output-source = ; }; }; diff --git a/include/dt-bindings/clock/cirrus,cs2000-cp.h b/include/dt-bindings/clock/cirrus,cs2000-cp.h new file mode 100644 index 000000000000..fe3ac71750a8 --- /dev/null +++ b/include/dt-bindings/clock/cirrus,cs2000-cp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 Daniel Mack + */ + +#ifndef __DT_BINDINGS_CS2000CP_CLK_H +#define __DT_BINDINGS_CS2000CP_CLK_H + +#define CS2000CP_AUX_OUTPUT_REF_CLK 0 +#define CS2000CP_AUX_OUTPUT_CLK_IN 1 +#define CS2000CP_AUX_OUTPUT_CLK_OUT 2 +#define CS2000CP_AUX_OUTPUT_PLL_LOCK 3 + +#endif /* __DT_BINDINGS_CS2000CP_CLK_H */ From patchwork Thu Jun 17 19:09:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 463272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FA0FC49EA3 for ; Thu, 17 Jun 2021 19:09:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D90B613E7 for ; Thu, 17 Jun 2021 19:09:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232749AbhFQTLa (ORCPT ); Thu, 17 Jun 2021 15:11:30 -0400 Received: from mail.bugwerft.de ([46.23.86.59]:37026 "EHLO mail.bugwerft.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231379AbhFQTL3 (ORCPT ); Thu, 17 Jun 2021 15:11:29 -0400 Received: from hq-00021.fritz.box (p57bc9ba2.dip0.t-ipconnect.de [87.188.155.162]) by mail.bugwerft.de (Postfix) with ESMTPSA id 8315C4C087A; Thu, 17 Jun 2021 19:09:19 +0000 (UTC) From: Daniel Mack To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, kuninori.morimoto.gx@renesas.com, mturquette@baylibre.com, sboyd@kernel.org, Daniel Mack Subject: [PATCH v3 3/9] dt-bindings: clock: cs2000-cp: make clk_in optional Date: Thu, 17 Jun 2021 21:09:06 +0200 Message-Id: <20210617190912.262809-4-daniel@zonque.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617190912.262809-1-daniel@zonque.org> References: <20210617190912.262809-1-daniel@zonque.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org CLK_IN is only used in dynamic mode and is hence optional. Re-order the clocks so REF_CLK is specified first. Signed-off-by: Daniel Mack --- .../devicetree/bindings/clock/cirrus,cs2000-cp.yaml | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml index 79b90500f6ac..68efed8e5033 100644 --- a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml +++ b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml @@ -22,14 +22,15 @@ properties: clocks: description: - Common clock binding for CLK_IN, XTI/REF_CLK - minItems: 2 + Common clock binding for XTI/REF_CLK, CLK_IN. + CLK_IN is optional and only used in dynamic mode. + minItems: 1 maxItems: 2 clock-names: items: - - const: clk_in - const: ref_clk + - const: clk_in '#clock-cells': const: 0 @@ -70,8 +71,8 @@ examples: #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; - clocks = <&rcar_sound 0>, <&x12_clk>; - clock-names = "clk_in", "ref_clk"; + clocks = <&x12_clk>, <&rcar_sound 0>; + clock-names = "ref_clk", "clk_in"; cirrus,aux-output-source = ; }; }; From patchwork Thu Jun 17 19:09:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 462347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62FD3C49361 for ; Thu, 17 Jun 2021 19:09:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4BFAE60FE9 for ; Thu, 17 Jun 2021 19:09:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233118AbhFQTLe (ORCPT ); Thu, 17 Jun 2021 15:11:34 -0400 Received: from mail.bugwerft.de ([46.23.86.59]:37028 "EHLO mail.bugwerft.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231807AbhFQTLa (ORCPT ); Thu, 17 Jun 2021 15:11:30 -0400 Received: from hq-00021.fritz.box (p57bc9ba2.dip0.t-ipconnect.de [87.188.155.162]) by mail.bugwerft.de (Postfix) with ESMTPSA id E0A0D4C1579; Thu, 17 Jun 2021 19:09:19 +0000 (UTC) From: Daniel Mack To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, kuninori.morimoto.gx@renesas.com, mturquette@baylibre.com, sboyd@kernel.org, Daniel Mack Subject: [PATCH v3 4/9] dt-bindings: clock: cs2000-cp: document cirrus, clock-skip flag Date: Thu, 17 Jun 2021 21:09:07 +0200 Message-Id: <20210617190912.262809-5-daniel@zonque.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617190912.262809-1-daniel@zonque.org> References: <20210617190912.262809-1-daniel@zonque.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Daniel Mack Acked-by: Rob Herring --- .../devicetree/bindings/clock/cirrus,cs2000-cp.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml index 68efed8e5033..8ad090372988 100644 --- a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml +++ b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml @@ -49,6 +49,12 @@ properties: - 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status default: 0 + cirrus,clock-skip: + description: + This mode allows the PLL to maintain lock even when CLK_IN + has missing pulses for up to 20 ms. + $ref: /schemas/types.yaml#/definitions/flag + required: - compatible - reg From patchwork Thu Jun 17 19:09:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 462345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D835C2B9F4 for ; Thu, 17 Jun 2021 19:09:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 54197613E1 for ; Thu, 17 Jun 2021 19:09:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233085AbhFQTLg (ORCPT ); Thu, 17 Jun 2021 15:11:36 -0400 Received: from mail.bugwerft.de ([46.23.86.59]:37030 "EHLO mail.bugwerft.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232671AbhFQTLb (ORCPT ); Thu, 17 Jun 2021 15:11:31 -0400 Received: from hq-00021.fritz.box (p57bc9ba2.dip0.t-ipconnect.de [87.188.155.162]) by mail.bugwerft.de (Postfix) with ESMTPSA id 4D08B4C20B2; Thu, 17 Jun 2021 19:09:20 +0000 (UTC) From: Daniel Mack To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, kuninori.morimoto.gx@renesas.com, mturquette@baylibre.com, sboyd@kernel.org, Daniel Mack Subject: [PATCH v3 5/9] clk: cs2000-cp: Make aux output function controllable Date: Thu, 17 Jun 2021 21:09:08 +0200 Message-Id: <20210617190912.262809-6-daniel@zonque.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617190912.262809-1-daniel@zonque.org> References: <20210617190912.262809-1-daniel@zonque.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The aux output pin can be configured to output either of the two clock inputs, the generated clock or the pll lock status. Allow access to this feature through a new optional device-tree property. Signed-off-by: Daniel Mack --- drivers/clk/clk-cs2000-cp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index 92bc4aca0f95..db7290621cef 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -39,6 +39,8 @@ /* DEVICE_CFG1 */ #define RSEL(x) (((x) & 0x3) << 3) #define RSEL_MASK RSEL(0x3) +#define AUXOUTSRC(x) (((x) & 0x3) << 1) +#define AUXOUTSRC_MASK AUXOUTSRC(0x3) #define ENDEV1 (0x1) /* DEVICE_CFG2 */ @@ -421,12 +423,19 @@ static int cs2000_clk_register(struct cs2000_priv *priv) struct clk_init_data init; const char *name = np->name; static const char *parent_names[CLK_MAX]; + u32 aux_out = 0; int ch = 0; /* it uses ch0 only at this point */ int rate; int ret; of_property_read_string(np, "clock-output-names", &name); + of_property_read_u32(np, "cirrus,aux-output-source", &aux_out); + ret = cs2000_bset(priv, DEVICE_CFG1, + AUXOUTSRC_MASK, AUXOUTSRC(aux_out)); + if (ret < 0) + return ret; + /* * set default rate as 1/1. * otherwise .set_rate which setup ratio From patchwork Thu Jun 17 19:09:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 463269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6599C49361 for ; Thu, 17 Jun 2021 19:09:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CFD2E613CB for ; Thu, 17 Jun 2021 19:09:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233106AbhFQTLh (ORCPT ); Thu, 17 Jun 2021 15:11:37 -0400 Received: from mail.bugwerft.de ([46.23.86.59]:37032 "EHLO mail.bugwerft.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232676AbhFQTLb (ORCPT ); Thu, 17 Jun 2021 15:11:31 -0400 Received: from hq-00021.fritz.box (p57bc9ba2.dip0.t-ipconnect.de [87.188.155.162]) by mail.bugwerft.de (Postfix) with ESMTPSA id B245D4C3EBE; Thu, 17 Jun 2021 19:09:20 +0000 (UTC) From: Daniel Mack To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, kuninori.morimoto.gx@renesas.com, mturquette@baylibre.com, sboyd@kernel.org, Daniel Mack Subject: [PATCH v3 6/9] clk: cs2000-cp: add support for dynamic mode Date: Thu, 17 Jun 2021 21:09:09 +0200 Message-Id: <20210617190912.262809-7-daniel@zonque.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617190912.262809-1-daniel@zonque.org> References: <20210617190912.262809-1-daniel@zonque.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The CS2000 chip features two input clocks, REF_CLK and CLK_IN. REF_CLK is mandatory, while CLK_IN is optional, depending on the mode of operation. In static mode, the output clock (CLK_OUT) is directly derived from REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the digital PLL. In dynamic mode, a low-frequency ratio configuration that uses a higher multiplier factor. This patch adds support for dynamic mode and both ratios: * Make the CLK_IN input clock optional * If CLK_IN is provided, present it as parent clock * The low-frequency ratio mode is automatically selected, depending on the presence of CLK_IN and the given input and output rates Signed-off-by: Daniel Mack --- drivers/clk/clk-cs2000-cp.c | 111 ++++++++++++++++++++++++------------ 1 file changed, 73 insertions(+), 38 deletions(-) diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index db7290621cef..791f088ec9aa 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -49,7 +49,7 @@ #define LOCKCLK_MASK LOCKCLK(0x3) #define FRACNSRC_MASK (1 << 0) #define FRACNSRC_STATIC (0 << 0) -#define FRACNSRC_DYNAMIC (1 << 1) +#define FRACNSRC_DYNAMIC (1 << 0) /* GLOBAL_CFG */ #define ENDEV2 (0x1) @@ -79,6 +79,8 @@ struct cs2000_priv { struct clk *clk_in; struct clk *ref_clk; + bool lf_ratio; + /* suspend/resume */ unsigned long saved_rate; unsigned long saved_parent_rate; @@ -134,17 +136,11 @@ static int cs2000_enable_dev_config(struct cs2000_priv *priv, bool enable) if (ret < 0) return ret; - /* FIXME: for Static ratio mode */ - ret = cs2000_bset(priv, FUNC_CFG2, LFRATIO_MASK, - LFRATIO_12_20); - if (ret < 0) - return ret; - return 0; } -static int cs2000_clk_in_bound_rate(struct cs2000_priv *priv, - u32 rate_in) +static int cs2000_ref_clk_bound_rate(struct cs2000_priv *priv, + u32 rate_in) { u32 val; @@ -191,35 +187,37 @@ static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable) (AUXOUTDIS | CLKOUTDIS)); } -static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out) +static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out, bool lf_ratio) { u64 ratio; + u32 multiplier = lf_ratio ? 12 : 20; /* - * ratio = rate_out / rate_in * 2^20 + * ratio = rate_out / rate_in * 2^multiplier * * To avoid over flow, rate_out is u64. * The result should be u32. */ - ratio = (u64)rate_out << 20; + ratio = (u64)rate_out << multiplier; do_div(ratio, rate_in); return ratio; } -static unsigned long cs2000_ratio_to_rate(u32 ratio, u32 rate_in) +static unsigned long cs2000_ratio_to_rate(u32 ratio, u32 rate_in, bool lf_ratio) { u64 rate_out; + u32 multiplier = lf_ratio ? 12 : 20; /* - * ratio = rate_out / rate_in * 2^20 + * ratio = rate_out / rate_in * 2^multiplier * * To avoid over flow, rate_out is u64. * The result should be u32 or unsigned long. */ rate_out = (u64)ratio * rate_in; - return rate_out >> 20; + return rate_out >> multiplier; } static int cs2000_ratio_set(struct cs2000_priv *priv, @@ -232,7 +230,7 @@ static int cs2000_ratio_set(struct cs2000_priv *priv, if (CH_SIZE_ERR(ch)) return -EINVAL; - val = cs2000_rate_to_ratio(rate_in, rate_out); + val = cs2000_rate_to_ratio(rate_in, rate_out, priv->lf_ratio); for (i = 0; i < RATIO_REG_SIZE; i++) { ret = cs2000_write(priv, Ratio_Add(ch, i), @@ -265,22 +263,21 @@ static u32 cs2000_ratio_get(struct cs2000_priv *priv, int ch) static int cs2000_ratio_select(struct cs2000_priv *priv, int ch) { int ret; + u8 fracnsrc; if (CH_SIZE_ERR(ch)) return -EINVAL; - /* - * FIXME - * - * this driver supports static ratio mode only at this point. - */ ret = cs2000_bset(priv, DEVICE_CFG1, RSEL_MASK, RSEL(ch)); if (ret < 0) return ret; + /* Always use dynamic mode when CLK_IN is present */ + fracnsrc = priv->clk_in ? FRACNSRC_DYNAMIC : FRACNSRC_STATIC; + ret = cs2000_bset(priv, DEVICE_CFG2, - (AUTORMOD | LOCKCLK_MASK | FRACNSRC_MASK), - (LOCKCLK(ch) | FRACNSRC_STATIC)); + AUTORMOD | LOCKCLK_MASK | FRACNSRC_MASK, + LOCKCLK(ch) | fracnsrc); if (ret < 0) return ret; @@ -296,17 +293,40 @@ static unsigned long cs2000_recalc_rate(struct clk_hw *hw, ratio = cs2000_ratio_get(priv, ch); - return cs2000_ratio_to_rate(ratio, parent_rate); + return cs2000_ratio_to_rate(ratio, parent_rate, priv->lf_ratio); } static long cs2000_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { + struct cs2000_priv *priv = hw_to_priv(hw); u32 ratio; - ratio = cs2000_rate_to_ratio(*parent_rate, rate); + ratio = cs2000_rate_to_ratio(*parent_rate, rate, priv->lf_ratio); + + return cs2000_ratio_to_rate(ratio, *parent_rate, priv->lf_ratio); +} + +static int cs2000_select_ratio_mode(struct cs2000_priv *priv, + unsigned long rate, + unsigned long parent_rate) +{ + /* + * From the datasheet: + * + * | It is recommended that the 12.20 High-Resolution format be + * | utilized whenever the desired ratio is less than 4096 since + * | the output frequency accuracy of the PLL is directly proportional + * | to the accuracy of the timing reference clock and the resolution + * | of the R_UD. + * + * This mode is only available in dynamic mode (ie, with a CLK_IN input + * present). + */ + priv->lf_ratio = priv->clk_in && ((rate / parent_rate) > 4096); - return cs2000_ratio_to_rate(ratio, *parent_rate); + return cs2000_bset(priv, FUNC_CFG2, LFRATIO_MASK, + priv->lf_ratio ? LFRATIO_20_12 : LFRATIO_12_20); } static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, @@ -315,7 +335,7 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, { int ret; - ret = cs2000_clk_in_bound_rate(priv, parent_rate); + ret = cs2000_select_ratio_mode(priv, rate, parent_rate); if (ret < 0) return ret; @@ -382,8 +402,14 @@ static void cs2000_disable(struct clk_hw *hw) static u8 cs2000_get_parent(struct clk_hw *hw) { - /* always return REF_CLK */ - return REF_CLK; + struct cs2000_priv *priv = hw_to_priv(hw); + + /* + * If CLK_IN was provided, we're operating in dynamic mode, + * hence output clock rates are derived from that. + */ + + return priv->clk_in ? CLK_IN : REF_CLK; } static const struct clk_ops cs2000_ops = { @@ -400,7 +426,7 @@ static int cs2000_clk_get(struct cs2000_priv *priv) struct device *dev = priv_to_dev(priv); struct clk *clk_in, *ref_clk; - clk_in = devm_clk_get(dev, "clk_in"); + clk_in = devm_clk_get_optional(dev, "clk_in"); /* not yet provided */ if (IS_ERR(clk_in)) return -EPROBE_DEFER; @@ -424,8 +450,8 @@ static int cs2000_clk_register(struct cs2000_priv *priv) const char *name = np->name; static const char *parent_names[CLK_MAX]; u32 aux_out = 0; + int ref_clk_rate; int ch = 0; /* it uses ch0 only at this point */ - int rate; int ret; of_property_read_string(np, "clock-output-names", &name); @@ -436,16 +462,25 @@ static int cs2000_clk_register(struct cs2000_priv *priv) if (ret < 0) return ret; - /* - * set default rate as 1/1. - * otherwise .set_rate which setup ratio - * is never called if user requests 1/1 rate - */ - rate = clk_get_rate(priv->ref_clk); - ret = __cs2000_set_rate(priv, ch, rate, rate); + ref_clk_rate = clk_get_rate(priv->ref_clk); + ret = cs2000_ref_clk_bound_rate(priv, ref_clk_rate); if (ret < 0) return ret; + if (priv->clk_in) { + /* Default to low-frequency mode to allow for large ratios */ + priv->lf_ratio = true; + } else { + /* + * set default rate as 1/1. + * otherwise .set_rate which setup ratio + * is never called if user requests 1/1 rate + */ + ret = __cs2000_set_rate(priv, ch, ref_clk_rate, ref_clk_rate); + if (ret < 0) + return ret; + } + parent_names[CLK_IN] = __clk_get_name(priv->clk_in); parent_names[REF_CLK] = __clk_get_name(priv->ref_clk); From patchwork Thu Jun 17 19:09:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 462346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C440C49EA4 for ; Thu, 17 Jun 2021 19:09:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2E7F4613EC for ; Thu, 17 Jun 2021 19:09:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233094AbhFQTLg (ORCPT ); Thu, 17 Jun 2021 15:11:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233080AbhFQTLa (ORCPT ); Thu, 17 Jun 2021 15:11:30 -0400 Received: from mail.bugwerft.de (mail.bugwerft.de [IPv6:2a03:6000:1011::59]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 66BC7C06175F; Thu, 17 Jun 2021 12:09:22 -0700 (PDT) Received: from hq-00021.fritz.box (p57bc9ba2.dip0.t-ipconnect.de [87.188.155.162]) by mail.bugwerft.de (Postfix) with ESMTPSA id 153714C4957; Thu, 17 Jun 2021 19:09:21 +0000 (UTC) From: Daniel Mack To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, kuninori.morimoto.gx@renesas.com, mturquette@baylibre.com, sboyd@kernel.org, Daniel Mack Subject: [PATCH v3 7/9] clk: cs2000-cp: make clock skip setting configurable Date: Thu, 17 Jun 2021 21:09:10 +0200 Message-Id: <20210617190912.262809-8-daniel@zonque.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617190912.262809-1-daniel@zonque.org> References: <20210617190912.262809-1-daniel@zonque.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The clock skip function of this chip is not necessarily desirable in all hardware appliances. This patch makes the feature configurable through a device-tree property. Signed-off-by: Daniel Mack --- drivers/clk/clk-cs2000-cp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index 791f088ec9aa..f3093d99c639 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -80,6 +80,7 @@ struct cs2000_priv { struct clk *ref_clk; bool lf_ratio; + bool clk_skip; /* suspend/resume */ unsigned long saved_rate; @@ -132,7 +133,7 @@ static int cs2000_enable_dev_config(struct cs2000_priv *priv, bool enable) return ret; ret = cs2000_bset(priv, FUNC_CFG1, CLKSKIPEN, - enable ? CLKSKIPEN : 0); + (enable && priv->clk_skip) ? CLKSKIPEN : 0); if (ret < 0) return ret; @@ -462,6 +463,8 @@ static int cs2000_clk_register(struct cs2000_priv *priv) if (ret < 0) return ret; + priv->clk_skip = of_property_read_bool(np, "cirrus,clock-skip"); + ref_clk_rate = clk_get_rate(priv->ref_clk); ret = cs2000_ref_clk_bound_rate(priv, ref_clk_rate); if (ret < 0) From patchwork Thu Jun 17 19:09:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 463270 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0864C49EA5 for ; Thu, 17 Jun 2021 19:09:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A97D8613EC for ; Thu, 17 Jun 2021 19:09:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233080AbhFQTLg (ORCPT ); Thu, 17 Jun 2021 15:11:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233085AbhFQTLa (ORCPT ); Thu, 17 Jun 2021 15:11:30 -0400 Received: from mail.bugwerft.de (mail.bugwerft.de [IPv6:2a03:6000:1011::59]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9F1C3C061760; Thu, 17 Jun 2021 12:09:22 -0700 (PDT) Received: from hq-00021.fritz.box (p57bc9ba2.dip0.t-ipconnect.de [87.188.155.162]) by mail.bugwerft.de (Postfix) with ESMTPSA id 6916A4C009A; Thu, 17 Jun 2021 19:09:21 +0000 (UTC) From: Daniel Mack To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, kuninori.morimoto.gx@renesas.com, mturquette@baylibre.com, sboyd@kernel.org, Daniel Mack Subject: [PATCH v3 8/9] clk: cs2000-cp: freeze config during register fiddling Date: Thu, 17 Jun 2021 21:09:11 +0200 Message-Id: <20210617190912.262809-9-daniel@zonque.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617190912.262809-1-daniel@zonque.org> References: <20210617190912.262809-1-daniel@zonque.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Make sure to freeze the configuration of the chip during the programming of 32-bit registers. This avoids the processing of invalid intermediate states. Signed-off-by: Daniel Mack --- drivers/clk/clk-cs2000-cp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index f3093d99c639..a630fb75bd4c 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -52,6 +52,7 @@ #define FRACNSRC_DYNAMIC (1 << 0) /* GLOBAL_CFG */ +#define FREEZE (1 << 7) #define ENDEV2 (0x1) /* FUNC_CFG1 */ @@ -336,6 +337,10 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, { int ret; + ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, FREEZE); + if (ret < 0) + return ret; + ret = cs2000_select_ratio_mode(priv, rate, parent_rate); if (ret < 0) return ret; @@ -348,6 +353,10 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, if (ret < 0) return ret; + ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, 0); + if (ret < 0) + return ret; + priv->saved_rate = rate; priv->saved_parent_rate = parent_rate; From patchwork Thu Jun 17 19:09:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 462344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00792C48BE5 for ; Thu, 17 Jun 2021 19:09:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C8B9160FE9 for ; Thu, 17 Jun 2021 19:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233143AbhFQTLi (ORCPT ); Thu, 17 Jun 2021 15:11:38 -0400 Received: from mail.bugwerft.de ([46.23.86.59]:37034 "EHLO mail.bugwerft.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233083AbhFQTLf (ORCPT ); Thu, 17 Jun 2021 15:11:35 -0400 Received: from hq-00021.fritz.box (p57bc9ba2.dip0.t-ipconnect.de [87.188.155.162]) by mail.bugwerft.de (Postfix) with ESMTPSA id C51E94C009D; Thu, 17 Jun 2021 19:09:21 +0000 (UTC) From: Daniel Mack To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, kuninori.morimoto.gx@renesas.com, mturquette@baylibre.com, sboyd@kernel.org, Daniel Mack Subject: [PATCH v3 9/9] clk: cs2000-cp: convert driver to regmap Date: Thu, 17 Jun 2021 21:09:12 +0200 Message-Id: <20210617190912.262809-10-daniel@zonque.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617190912.262809-1-daniel@zonque.org> References: <20210617190912.262809-1-daniel@zonque.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Regmap gives us caching, debugging infrastructure and other things for free and does away with open-coded bit-fiddling implementations. Signed-off-by: Daniel Mack --- drivers/clk/Kconfig | 1 + drivers/clk/clk-cs2000-cp.c | 124 ++++++++++++++++++++---------------- 2 files changed, 69 insertions(+), 56 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index a588d56502d4..646283411a03 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -185,6 +185,7 @@ config COMMON_CLK_CDCE925 config COMMON_CLK_CS2000_CP tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier" depends on I2C + select REGMAP_I2C help If you say yes here you get support for the CS2000 clock multiplier. diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index a630fb75bd4c..352918d392ca 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -11,6 +11,7 @@ #include #include #include +#include #define CH_MAX 4 #define RATIO_REG_SIZE 4 @@ -74,11 +75,36 @@ #define REF_CLK 1 #define CLK_MAX 2 +static bool cs2000_readable_reg(struct device *dev, unsigned int reg) +{ + return reg > 0; +} + +static bool cs2000_writeable_reg(struct device *dev, unsigned int reg) +{ + return reg != DEVICE_ID; +} + +static bool cs2000_volatile_reg(struct device *dev, unsigned int reg) +{ + return reg == DEVICE_CTRL; +} + +static const struct regmap_config cs2000_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = FUNC_CFG2, + .readable_reg = cs2000_readable_reg, + .writeable_reg = cs2000_writeable_reg, + .volatile_reg = cs2000_volatile_reg, +}; + struct cs2000_priv { struct clk_hw hw; struct i2c_client *client; struct clk *clk_in; struct clk *ref_clk; + struct regmap *regmap; bool lf_ratio; bool clk_skip; @@ -100,41 +126,22 @@ static const struct i2c_device_id cs2000_id[] = { }; MODULE_DEVICE_TABLE(i2c, cs2000_id); -#define cs2000_read(priv, addr) \ - i2c_smbus_read_byte_data(priv_to_client(priv), addr) -#define cs2000_write(priv, addr, val) \ - i2c_smbus_write_byte_data(priv_to_client(priv), addr, val) - -static int cs2000_bset(struct cs2000_priv *priv, u8 addr, u8 mask, u8 val) -{ - s32 data; - - data = cs2000_read(priv, addr); - if (data < 0) - return data; - - data &= ~mask; - data |= (val & mask); - - return cs2000_write(priv, addr, data); -} - static int cs2000_enable_dev_config(struct cs2000_priv *priv, bool enable) { int ret; - ret = cs2000_bset(priv, DEVICE_CFG1, ENDEV1, - enable ? ENDEV1 : 0); + ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, ENDEV1, + enable ? ENDEV1 : 0); if (ret < 0) return ret; - ret = cs2000_bset(priv, GLOBAL_CFG, ENDEV2, - enable ? ENDEV2 : 0); + ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, ENDEV2, + enable ? ENDEV2 : 0); if (ret < 0) return ret; - ret = cs2000_bset(priv, FUNC_CFG1, CLKSKIPEN, - (enable && priv->clk_skip) ? CLKSKIPEN : 0); + ret = regmap_update_bits(priv->regmap, FUNC_CFG1, CLKSKIPEN, + (enable && priv->clk_skip) ? CLKSKIPEN : 0); if (ret < 0) return ret; @@ -155,21 +162,21 @@ static int cs2000_ref_clk_bound_rate(struct cs2000_priv *priv, else return -EINVAL; - return cs2000_bset(priv, FUNC_CFG1, - REFCLKDIV_MASK, - REFCLKDIV(val)); + return regmap_update_bits(priv->regmap, FUNC_CFG1, + REFCLKDIV_MASK, + REFCLKDIV(val)); } static int cs2000_wait_pll_lock(struct cs2000_priv *priv) { struct device *dev = priv_to_dev(priv); - s32 val; - unsigned int i; + unsigned int i, val; + int ret; for (i = 0; i < 256; i++) { - val = cs2000_read(priv, DEVICE_CTRL); - if (val < 0) - return val; + ret = regmap_read(priv->regmap, DEVICE_CTRL, &val); + if (ret < 0) + return ret; if (!(val & PLL_UNLOCK)) return 0; udelay(1); @@ -183,10 +190,10 @@ static int cs2000_wait_pll_lock(struct cs2000_priv *priv) static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable) { /* enable both AUX_OUT, CLK_OUT */ - return cs2000_bset(priv, DEVICE_CTRL, - (AUXOUTDIS | CLKOUTDIS), - enable ? 0 : - (AUXOUTDIS | CLKOUTDIS)); + return regmap_update_bits(priv->regmap, DEVICE_CTRL, + (AUXOUTDIS | CLKOUTDIS), + enable ? 0 : + (AUXOUTDIS | CLKOUTDIS)); } static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out, bool lf_ratio) @@ -234,7 +241,7 @@ static int cs2000_ratio_set(struct cs2000_priv *priv, val = cs2000_rate_to_ratio(rate_in, rate_out, priv->lf_ratio); for (i = 0; i < RATIO_REG_SIZE; i++) { - ret = cs2000_write(priv, + ret = regmap_write(priv->regmap, Ratio_Add(ch, i), Ratio_Val(val, i)); if (ret < 0) @@ -246,14 +253,14 @@ static int cs2000_ratio_set(struct cs2000_priv *priv, static u32 cs2000_ratio_get(struct cs2000_priv *priv, int ch) { - s32 tmp; + unsigned int tmp, i; u32 val; - unsigned int i; + int ret; val = 0; for (i = 0; i < RATIO_REG_SIZE; i++) { - tmp = cs2000_read(priv, Ratio_Add(ch, i)); - if (tmp < 0) + ret = regmap_read(priv->regmap, Ratio_Add(ch, i), &tmp); + if (ret < 0) return 0; val |= Val_Ratio(tmp, i); @@ -270,16 +277,16 @@ static int cs2000_ratio_select(struct cs2000_priv *priv, int ch) if (CH_SIZE_ERR(ch)) return -EINVAL; - ret = cs2000_bset(priv, DEVICE_CFG1, RSEL_MASK, RSEL(ch)); + ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, RSEL_MASK, RSEL(ch)); if (ret < 0) return ret; /* Always use dynamic mode when CLK_IN is present */ fracnsrc = priv->clk_in ? FRACNSRC_DYNAMIC : FRACNSRC_STATIC; - ret = cs2000_bset(priv, DEVICE_CFG2, - AUTORMOD | LOCKCLK_MASK | FRACNSRC_MASK, - LOCKCLK(ch) | fracnsrc); + ret = regmap_update_bits(priv->regmap, DEVICE_CFG2, + AUTORMOD | LOCKCLK_MASK | FRACNSRC_MASK, + LOCKCLK(ch) | fracnsrc); if (ret < 0) return ret; @@ -327,8 +334,8 @@ static int cs2000_select_ratio_mode(struct cs2000_priv *priv, */ priv->lf_ratio = priv->clk_in && ((rate / parent_rate) > 4096); - return cs2000_bset(priv, FUNC_CFG2, LFRATIO_MASK, - priv->lf_ratio ? LFRATIO_20_12 : LFRATIO_12_20); + return regmap_update_bits(priv->regmap, FUNC_CFG2, LFRATIO_MASK, + priv->lf_ratio ? LFRATIO_20_12 : LFRATIO_12_20); } static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, @@ -337,7 +344,7 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, { int ret; - ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, FREEZE); + ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, FREEZE, FREEZE); if (ret < 0) return ret; @@ -353,7 +360,7 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, if (ret < 0) return ret; - ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, 0); + ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, FREEZE, 0); if (ret < 0) return ret; @@ -467,8 +474,8 @@ static int cs2000_clk_register(struct cs2000_priv *priv) of_property_read_string(np, "clock-output-names", &name); of_property_read_u32(np, "cirrus,aux-output-source", &aux_out); - ret = cs2000_bset(priv, DEVICE_CFG1, - AUXOUTSRC_MASK, AUXOUTSRC(aux_out)); + ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, + AUXOUTSRC_MASK, AUXOUTSRC(aux_out)); if (ret < 0) return ret; @@ -520,12 +527,13 @@ static int cs2000_clk_register(struct cs2000_priv *priv) static int cs2000_version_print(struct cs2000_priv *priv) { struct device *dev = priv_to_dev(priv); - s32 val; const char *revision; + unsigned int val; + int ret; - val = cs2000_read(priv, DEVICE_ID); - if (val < 0) - return val; + ret = regmap_read(priv->regmap, DEVICE_ID, &val); + if (ret < 0) + return ret; /* CS2000 should be 0x0 */ if (val >> 3) @@ -574,6 +582,10 @@ static int cs2000_probe(struct i2c_client *client, priv->client = client; i2c_set_clientdata(client, priv); + priv->regmap = devm_regmap_init_i2c(client, &cs2000_regmap_config); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + ret = cs2000_clk_get(priv); if (ret < 0) return ret;