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Tue, 7 Aug 2018 10:49:04 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , stable@vger.kernel.org Subject: [PATCH v2 1/2] ARM: dts: exynos: Convert exynos5250.dtsi to opp-v2 bindings Date: Tue, 7 Aug 2018 12:48:48 +0200 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180807104757eucas1p201bd787714f50a798ee7457bdaf2c2f9~IlG8LJVcj1319313193eucas1p2R@eucas1p2.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBIsWRmVeSWpSXmKPExsWy7djP87pKlZnRBu9fsltsnLGe1eL8+Q3s FjPO72OyWHvkLrvFgo2PGB1YPTat6mTz6NuyitHj8ya5AOYoLpuU1JzMstQifbsEroyZa8+x FWxRqXi9YzJbA+Mp6S5GTg4JAROJ28faGbsYuTiEBFYwSvxeOZMFwvnCKPHm51ZWCOczo0T/ sblADgdYy4eFUEXLGSVOPW2Cav/KKHHxdxMLyFw2AUOJrrddbCC2iICqxOe2BewgRcwgOzr3 LmcCSQgLhElc3bsNzGYBKvradYIF4ih5idUbDjCDbOMUKJc4vLkEpFdC4DKbxPGVnxlBangF yiSanraxQ9S7SMyd0ssIYQtLvDq+BSouI3F6cg8LRHMzo0T7jFnsEE4Po8TWOTvYIKqsJQ4f vwj2G7OApsT6XfoQYUeJ0w0/mCFe5pO48VYQJMwMZE7aNh0qzCvR0SYEUa0mMev4Ori1By9c YoawPSSOv9vMBAmgU0AnXFrJNIFRfhbCsgWMjKsYxVNLi3PTU4uN8lLL9YoTc4tL89L1kvNz NzEC4//0v+NfdjDu+pN0iFGAg1GJhzdjWUa0EGtiWXFl7iFGCQ5mJRFe3kygEG9KYmVValF+ fFFpTmrxIUZpDhYlcV4+rbRoIYH0xJLU7NTUgtQimCwTB6dUA6Pu9EJxnmgjF9e1jjeX3Dsa obV1wzVV/d9pijXnbqy62/u2ptpXXrIruOCSxB8Hs7xz6RktvDubW9UVX7VtVHEpVZl5/55c uds8nsevI9Zq6zMs3Xp2MkODy5p9J0vYOI6+e5MTsWmVHe/NNMEoT56FMdUndz4vKpddf+SW Pavg/Xtax6uK/yuxFGckGmoxFxUnAgC4NfFt+wIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKLMWRmVeSWpSXmKPExsVy+t/xu7qKlZnRBpPW8lhsnLGe1eL8+Q3s FjPO72OyWHvkLrvFgo2PGB1YPTat6mTz6NuyitHj8ya5AOYoPZui/NKSVIWM/OISW6VoQwsj PUNLCz0jE0s9Q2PzWCsjUyV9O5uU1JzMstQifbsEvYyZa8+xFWxRqXi9YzJbA+Mp6S5GDg4J AROJDwtZuhg5OYQEljJKbLydCmJLCMhInJzWwAphC0v8udbF1sXIBVTzmVHiyoLjYA1sAoYS XW9BEpwcIgKqEp/bFrCD2MwCqxglvt1xB7GFBUIk1uz9AxZnAar52nUCrJdXwFZi+7+PLBAL 5CVWbzjADHIPp0C5xOHNJSCmkECZxMnFTBMY+RYwMqxiFEktLc5Nzy021CtOzC0uzUvXS87P 3cQIDMJtx35u3sF4aWPwIUYBDkYlHl6BJRnRQqyJZcWVuYcYJTiYlUR4eTOBQrwpiZVVqUX5 8UWlOanFhxhNgU6ayCwlmpwPjJC8knhDU0NzC0tDc2NzYzMLJXHe8waVUUIC6YklqdmpqQWp RTB9TBycUg2Mpo/lv7ZNF7yzP+virpkTe51//p5uf6n/YUSGx5zE0OwZ7Am8xf9f5isanJ++ aaY0z6MZe1JZ78fYr/vsmCA69c+xT2uCd+07+vltUqPYw9xd+pteiva6r+WIOzrLISRRsO6V rNJmp0NKL2pSz7Gv2v4864f+Ptstn/xPuTxQM1dm2yKbkfLmqxJLcUaioRZzUXEiANhk3Y9Y AgAA Message-Id: <20180807104905eucas1p262885b5e1ee707bce83da40c50feb402~IlH7UbpE_1482814828eucas1p2p@eucas1p2.samsung.com> X-CMS-MailID: 20180807104905eucas1p262885b5e1ee707bce83da40c50feb402 X-Msg-Generator: CA X-RootMTR: 20180807104905eucas1p262885b5e1ee707bce83da40c50feb402 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180807104905eucas1p262885b5e1ee707bce83da40c50feb402 References: <20180807104757eucas1p201bd787714f50a798ee7457bdaf2c2f9~IlG8LJVcj1319313193eucas1p2R@eucas1p2.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Convert Exynos5250 to OPP-v2 bindings. This is a preparation to add proper support for suspend operation point, which cannot be marked in opp-v1. CC: # 4.3.x: cd6f55457eb4 ARM: dts: exynos: Remove "cooling-{min|max}-level" for CPU nodes CC: # 4.3.x: 672f33198bee arm: dts: exynos: Add missing cooling device properties for CPUs CC: # 4.3.x Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi Acked-by: Bartlomiej Zolnierkiewicz --- arch/arm/boot/dts/exynos5250.dtsi | 130 ++++++++++++++++++++---------- 1 file changed, 88 insertions(+), 42 deletions(-) -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index da163a40af15..8746189990eb 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -54,62 +54,108 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; - clock-frequency = <1700000000>; clocks = <&clock CLK_ARM_CLK>; clock-names = "cpu"; - clock-latency = <140000>; - - operating-points = < - 1700000 1300000 - 1600000 1250000 - 1500000 1225000 - 1400000 1200000 - 1300000 1150000 - 1200000 1125000 - 1100000 1100000 - 1000000 1075000 - 900000 1050000 - 800000 1025000 - 700000 1012500 - 600000 1000000 - 500000 975000 - 400000 950000 - 300000 937500 - 200000 925000 - >; + operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; - clock-frequency = <1700000000>; clocks = <&clock CLK_ARM_CLK>; clock-names = "cpu"; - clock-latency = <140000>; - - operating-points = < - 1700000 1300000 - 1600000 1250000 - 1500000 1225000 - 1400000 1200000 - 1300000 1150000 - 1200000 1125000 - 1100000 1100000 - 1000000 1075000 - 900000 1050000 - 800000 1025000 - 700000 1012500 - 600000 1000000 - 500000 975000 - 400000 950000 - 300000 937500 - 200000 925000 - >; + operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <925000>; + clock-latency-ns = <140000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <937500>; + clock-latency-ns = <140000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <950000>; + clock-latency-ns = <140000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <975000>; + clock-latency-ns = <140000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <140000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <1012500>; + clock-latency-ns = <140000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <140000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1050000>; + clock-latency-ns = <140000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1075000>; + clock-latency-ns = <140000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <140000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1125000>; + clock-latency-ns = <140000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1150000>; + clock-latency-ns = <140000>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <140000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1225000>; + clock-latency-ns = <140000>; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <140000>; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1300000>; + clock-latency-ns = <140000>; + }; + }; + soc: soc { sysram@2020000 { compatible = "mmio-sram";