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Wed, 08 Aug 2018 10:38:47 +0000 Received: by mail-pg1-f179.google.com with SMTP id r1-v6so891438pgp.11 for ; Wed, 08 Aug 2018 03:38:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=J9FTYOvEHi22iTw+SbKWndxS/WZ//D/gIpShd+EeTTs=; b=iT28tVP8VH7OPGzwB5VCMVH1OHTrLhY/bHG64syA9+Kt/B4aqrJdF8Qc24nlA+zEVC MPcNocyBdEfXvH+IEBH9t4fIXD0bMPiV2C3ksxMWkowanFurKWhltJNbnb+45d+N5/Tg 5RSBq7hbMCBVLmrBeN2KtCXh4aQOSE4EzO57k= Return-Path: Received: from localhost.localdomain ([45.56.155.47]) by smtp.gmail.com with ESMTPSA id g5-v6sm7497802pfc.77.2018.08.08.03.38.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Aug 2018 03:38:45 -0700 (PDT) From: Hongbo Zhang To: james.greenhalgh@arm.com, gcc-patches@gcc.gnu.org Cc: Hongbo Zhang Subject: [PATCH v3] Add HXT Phecda core support Date: Wed, 8 Aug 2018 18:38:09 +0800 Message-Id: <1533724689-27404-1-git-send-email-hongbo.zhang@linaro.org> X-IsSubscribed: yes HXT semiconductor's CPU core Phecda, as a variant of Qualcomm qdf24xx, reuses the same tuning structure and pipeline with it. 2018-08-08 Hongbo Zhang * config/aarch64/aarch64-cores.def: Add phecda core. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi: Add phecda core. --- v3 changes: - use 'h' instead of 'H' in the comments. - rebased to the latest commit. gcc/config/aarch64/aarch64-cores.def | 3 +++ gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/doc/invoke.texi | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 3d876b8..437ed1e 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -71,6 +71,9 @@ AARCH64_CORE("qdf24xx", qdf24xx, falkor, 8A, AARCH64_FL_FOR_ARCH8 | AA /* Samsung ('S') cores. */ AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, 0x53, 0x001, -1) +/* HXT ('h') cores. */ +AARCH64_CORE("phecda", phecda, falkor, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x68, 0x000, -1) + /* ARMv8.1-A Architecture Processors. */ /* Broadcom ('B') cores. */ diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index f82222c..ec75b45 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55" + "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 841cb47..3944fe4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14840,7 +14840,7 @@ performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, @samp{cortex-a76}, @samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, -@samp{saphira}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, +@samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81}, @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},