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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:23 -0700 Message-Id: <20180809034033.10579-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::534 Subject: [Qemu-devel] [PATCH 01/11] target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The normal vector element is sign-extended before comparing with the wide vector element. Cc: qemu-stable@nongnu.org (3.0.1) Tested-by: Laurent Desnogues Reviewed-by: Laurent Desnogues Reviewed-by: Alex Bennée Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 54795c9194..9bd0694d55 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -2436,13 +2436,13 @@ uint32_t HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ #define DO_CMP_PPZW_S(NAME, TYPE, TYPEW, OP) \ DO_CMP_PPZW(NAME, TYPE, TYPEW, OP, H1_4, 0x1111111111111111ull) -DO_CMP_PPZW_B(sve_cmpeq_ppzw_b, uint8_t, uint64_t, ==) -DO_CMP_PPZW_H(sve_cmpeq_ppzw_h, uint16_t, uint64_t, ==) -DO_CMP_PPZW_S(sve_cmpeq_ppzw_s, uint32_t, uint64_t, ==) +DO_CMP_PPZW_B(sve_cmpeq_ppzw_b, int8_t, uint64_t, ==) +DO_CMP_PPZW_H(sve_cmpeq_ppzw_h, int16_t, uint64_t, ==) +DO_CMP_PPZW_S(sve_cmpeq_ppzw_s, int32_t, uint64_t, ==) -DO_CMP_PPZW_B(sve_cmpne_ppzw_b, uint8_t, uint64_t, !=) -DO_CMP_PPZW_H(sve_cmpne_ppzw_h, uint16_t, uint64_t, !=) -DO_CMP_PPZW_S(sve_cmpne_ppzw_s, uint32_t, uint64_t, !=) +DO_CMP_PPZW_B(sve_cmpne_ppzw_b, int8_t, uint64_t, !=) +DO_CMP_PPZW_H(sve_cmpne_ppzw_h, int16_t, uint64_t, !=) +DO_CMP_PPZW_S(sve_cmpne_ppzw_s, int32_t, uint64_t, !=) DO_CMP_PPZW_B(sve_cmpgt_ppzw_b, int8_t, int64_t, >) DO_CMP_PPZW_H(sve_cmpgt_ppzw_h, int16_t, int64_t, >) From patchwork Thu Aug 9 03:40:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 143648 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1576862ljj; Wed, 8 Aug 2018 20:46:23 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxYVwq2JdYHMJkd/Wm+6G+SB9oxo5JPx/dPKBGPF9i7gYKkVSacTXUfw71B1IX1IND0iWbP X-Received: by 2002:a37:9f90:: with SMTP id i138-v6mr335360qke.113.1533786383821; Wed, 08 Aug 2018 20:46:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533786383; cv=none; d=google.com; s=arc-20160816; b=TRTskkQOCJanbXUIJ880ljQWm8z4fbVglGWAu3VXAttsb3RpqpMm6Nu7dmk0lxTbBq N0923zaVCDUsGgjKTzZqJZpIqruH2zY0vyIExHOccijjOOYdrvFpIkzYyJbmUOxcAMMj xOIas4HKaUizBEQlRqLFM+SeRZL6Fsd/scNrbmdP0buTipIsHj6knHT9Q6yZ05gLMS2d +twCs9NyZQrl+INKt50Fh9ptnNr/ZExPXOMWQTlZFhgb7u11UbAYKB22x7bF9vaqE9db z5DKWKOAQcfCT6SjPB5rwjRVp/n4rwXh+fJ2JiAh5Tpng4dnYOGdSRELhB/5BMFg7uSF xJig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=oB1SIrg6peK9wa8OQjaurgO0tZQqjrg+qYqLcGUVKpM=; b=fRDjkljQzn3itvWiou4IvF+QWSSijfNqhfLW54YTItedBHA87u5CiqpITG0iGzWZM9 k7eqKRjBZ6H8vvGhN+m9Yl9wuTnBaQJv2a1o2PA/c9ZMSK48dU54Ex4dtNV8rMuh6QMW 4fh7FTwSvDNGtfwaMHtAyDYJpSt82SPPDVYoFM22ZZbhodtnFoWALTEnkxTh+s2Z4OJZ R/M4y+sRIqqZsi94sMDXlejc+aQSIL2QE55NyH/3GucT8pgwmRBeEbg1PTWQ9PB3fvnC bY53aShfDJmxybJQggfanJ8QwQ56TeEgrV9tvOLud0Pv1JZGZpty5wgeFSmjQX5FlrMq BhOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TWMWneuI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:24 -0700 Message-Id: <20180809034033.10579-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 02/11] target/arm: Fix typo in do_sat_addsub_64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Used the wrong temporary in the computation of subtractive overflow. Cc: qemu-stable@nongnu.org (3.0.1) Tested-by: Laurent Desnogues Reviewed-by: Laurent Desnogues Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 374051cd20..9dd4c38bab 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1625,7 +1625,7 @@ static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) /* Detect signed overflow for subtraction. */ tcg_gen_xor_i64(t0, reg, val); tcg_gen_sub_i64(t1, reg, val); - tcg_gen_xor_i64(reg, reg, t0); + tcg_gen_xor_i64(reg, reg, t1); tcg_gen_and_i64(t0, t0, reg); /* Bound the result. */ From patchwork Thu Aug 9 03:40:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 143649 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1577191ljj; Wed, 8 Aug 2018 20:46:49 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxo6lqH+gEehtskGiV+2ctFoe3lnpz6vrnskFlkkkUQ5wGHPKw/wrzG8heAkFPTcz6uXLa4 X-Received: by 2002:a0c:f685:: with SMTP id p5-v6mr369719qvn.22.1533786409858; Wed, 08 Aug 2018 20:46:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533786409; cv=none; d=google.com; s=arc-20160816; b=X0NnYwwyYFKuI+E5NBYJYv/lDBhRWqf8DAITNzuVujbdc+8xA5DvhoQlXyXj7f1r86 Lf9CmUBVMthqBe/BKoM72n4vUn1O6kN9yEVtKCLFX0LLFdNywNuvSQzdBMOJyx/dgTgX 0ZMUU7FPj4OsczfbfqUqwBFojvd+jH6X0zDkBxQ3VGWjnYdDvFHAkKgumNHsrKI/ym0b go+ITHO9DTD/mxutYJKoyORlI46TAG6NOzQ0ET9IgjIMBR0bOZ37vQpsD6d9lNzWT2Fk bXeVBE7QMZCYKKl2M8yiJV3viFu+Wn6voQLFPdABK/OW1LFcJSw8RpHSNtDnZecRqCsj 9qRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Ablu58t752cnKdeomCa6I+Hum7D6ukONMk815MNMlCI=; b=QJ0GBQ6mExK4cxoIm4GiOkMzqjmEMnTJ/CuUdJXspIz7kChbakIli36xEGuqrKjYE3 maGuMIUveKhgPVXaoRgP8q9PovnenePenNRPdTyWmN49bzGZ3zrHilVraoJfrw7c1XCt bYzB+iq25O/VgN5sjTWlXl3eBzd4kfTj9j6HMlPrV5d7/YhqyqcJHlAQHCI9bJis317f BOeog2uetx4XkgwMkXtwdwKdq0fxgfMnQBvUNmg6NDooBT2yulDYiVWRzxxyHRNCigbG Ex0+OrEF98pouD+M15se4T7PItTRzK4CU5Cgwa7FEEEXNDJSbx2wsAwhOoqNKBEw81lb ZsPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Lrh8BGuo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:25 -0700 Message-Id: <20180809034033.10579-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 03/11] target/arm: Reorganize SVE WHILE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The pseudocode for this operation is an increment + compare loop, so comparing <= the maximum integer produces an all-true predicate. Rather than bound in both the inline code and the helper, pass the helper the number of predicate bits to set instead of the number of predicate elements to set. Cc: qemu-stable@nongnu.org (3.0.1) Tested-by: Laurent Desnogues Reviewed-by: Laurent Desnogues Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 5 ---- target/arm/translate-sve.c | 49 +++++++++++++++++++++++++------------- 2 files changed, 32 insertions(+), 22 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 9bd0694d55..87594a8adb 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -2846,11 +2846,6 @@ uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc) return flags; } - /* Scale from predicate element count to bits. */ - count <<= esz; - /* Bound to the bits in the predicate. */ - count = MIN(count, oprsz * 8); - /* Set all of the requested bits. */ for (i = 0; i < count / 64; ++i) { d->p[i] = esz_mask; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9dd4c38bab..89efc80ee7 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3173,19 +3173,19 @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a, uint32_t insn) static bool trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn) { - if (!sve_access_check(s)) { - return true; - } - - TCGv_i64 op0 = read_cpu_reg(s, a->rn, 1); - TCGv_i64 op1 = read_cpu_reg(s, a->rm, 1); - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 op0, op1, t0, t1, tmax; TCGv_i32 t2, t3; TCGv_ptr ptr; unsigned desc, vsz = vec_full_reg_size(s); TCGCond cond; + if (!sve_access_check(s)) { + return true; + } + + op0 = read_cpu_reg(s, a->rn, 1); + op1 = read_cpu_reg(s, a->rm, 1); + if (!a->sf) { if (a->u) { tcg_gen_ext32u_i64(op0, op0); @@ -3198,32 +3198,47 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn) /* For the helper, compress the different conditions into a computation * of how many iterations for which the condition is true. - * - * This is slightly complicated by 0 <= UINT64_MAX, which is nominally - * 2**64 iterations, overflowing to 0. Of course, predicate registers - * aren't that large, so any value >= predicate size is sufficient. */ + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); tcg_gen_sub_i64(t0, op1, op0); - /* t0 = MIN(op1 - op0, vsz). */ - tcg_gen_movi_i64(t1, vsz); - tcg_gen_umin_i64(t0, t0, t1); + tmax = tcg_const_i64(vsz >> a->esz); if (a->eq) { /* Equality means one more iteration. */ tcg_gen_addi_i64(t0, t0, 1); + + /* If op1 is max (un)signed integer (and the only time the addition + * above could overflow), then we produce an all-true predicate by + * setting the count to the vector length. This is because the + * pseudocode is described as an increment + compare loop, and the + * max integer would always compare true. + */ + tcg_gen_movi_i64(t1, (a->sf + ? (a->u ? UINT64_MAX : INT64_MAX) + : (a->u ? UINT32_MAX : INT32_MAX))); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, op1, t1, tmax, t0); } - /* t0 = (condition true ? t0 : 0). */ + /* Bound to the maximum. */ + tcg_gen_umin_i64(t0, t0, tmax); + tcg_temp_free_i64(tmax); + + /* Set the count to zero if the condition is false. */ cond = (a->u ? (a->eq ? TCG_COND_LEU : TCG_COND_LTU) : (a->eq ? TCG_COND_LE : TCG_COND_LT)); tcg_gen_movi_i64(t1, 0); tcg_gen_movcond_i64(cond, t0, op0, op1, t0, t1); + tcg_temp_free_i64(t1); + /* Since we're bounded, pass as a 32-bit type. */ t2 = tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, t0); tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); + + /* Scale elements to bits. */ + tcg_gen_shli_i32(t2, t2, a->esz); desc = (vsz / 8) - 2; desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); From patchwork Thu Aug 9 03:40:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 143650 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1577267ljj; Wed, 8 Aug 2018 20:46:54 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyIbmBQwgGqLp4WxaRTvsNMNC+7kZ253kFclxHl082Z+vMobR62sBv6Sr/KkrtuWxS0u86n X-Received: by 2002:aed:2aa1:: with SMTP id t30-v6mr419641qtd.28.1533786414548; Wed, 08 Aug 2018 20:46:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533786414; cv=none; d=google.com; s=arc-20160816; b=MXMAfVuArRD+ty8cUi+YIwP7UrPo30w/JY4RQ1Ef+Jk3RcyVTLBxFDuIZtpH7ei7MC 2hTeMNwW5QKnz2mRpwrqlz2mzyU74Cm9PlB15WgeVM7SyZLXJQluYdmAiMvcevp7alhT qEFOm663FxwkfoFhi7UPqPeAHjrjn8VWkBUkdj+fH4nSnQlT6jaIkgFWmHi+Ln6lF7tb 8Guim9aL8uq+IIdhjdosnF7UBZ/EaUO3amiRLSSX6wk1cd3ne1gjULDPtUpHmMij7y6n dcN6jw6/W5sYu8V9HPnCZXFSbv5gaOa762N24Bz6hTlg3fczjVeo4+lrBhva5G2DLgFu ey1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=qR6U/BTO+a4k2WnIzfIot/cfXtAcIXt0pK5MsJgp23M=; b=mAtg2SvhtY9aeus3ynYKyDRKmq491pUFDexrVVvNtGaK68inC9t9zw7ZDGqFmhymF+ R3Iix6X3PjmhR5hTbdZAhqIkMz3rJsho+Bg2Rpz9TSbZajjVQrAFCSFTDiSiDK8hXbi1 dmFuPgiD+R8KtVKCTU1JU17rpfN7q+U0hGEiTaO67hxPksdOU8u+L04VCK+1RqdoeaIm XcOdtQtpUASKLTYEcD/ZfmA7cgrx33aT4eags2A1H1ZH37tVjMyIcUZ7Z6Zw8ksL9ME7 bqE84ChtMqhVeC1cyTKQOMptXNU194PJKGsH4e8QqYo8sWdX22ET71SfwGnzEbkOs+8U 5EWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=I6edYR4M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:26 -0700 Message-Id: <20180809034033.10579-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52f Subject: [Qemu-devel] [PATCH 04/11] target/arm: Fix typo in helper_sve_movz_d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: qemu-stable@nongnu.org (3.0.1) Tested-by: Laurent Desnogues Reviewed-by: Laurent Desnogues Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 87594a8adb..c3cbec9cf5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1042,7 +1042,7 @@ void HELPER(sve_movz_d)(void *vd, void *vn, void *vg, uint32_t desc) uint64_t *d = vd, *n = vn; uint8_t *pg = vg; for (i = 0; i < opr_sz; i += 1) { - d[i] = n[1] & -(uint64_t)(pg[H1(i)] & 1); + d[i] = n[i] & -(uint64_t)(pg[H1(i)] & 1); } } From patchwork Thu Aug 9 03:40:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 143645 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1575266ljj; Wed, 8 Aug 2018 20:43:57 -0700 (PDT) X-Google-Smtp-Source: AA+uWPwXsL2gb4wlR+IvWsOS5ThPVBU/2oKPLJyUmkNLNLV5nIj6xeVsUst9rFczGTSLhORBWW48 X-Received: by 2002:a0c:bf49:: with SMTP id b9-v6mr339188qvj.65.1533786236906; Wed, 08 Aug 2018 20:43:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533786236; cv=none; d=google.com; s=arc-20160816; b=e3pbo1Ivuq8/5PdN9k6Z/ORd0j21igXaeOzV9QZe8WYIFSFNc7t5xDRKid1RFnjbpq 63srd5KTGUO49DnuA6T2NDh1UH6HmusqSKNM3kk7Xr7Z1ND7rmnCqThp6bwSr/r3Fkg7 ElEja+2NI5uMtKnARVheSTqJA+HGYYMl/2uxPM7XO9O2PXAtqbaqc+dTa0NCVHupX9tz UH8buLPXz61sIlClBxRzjz+dKgzemLuN9nfpRnVQeT0hyTlqhDvByupWFjqFBTe5kn5o sxlLquVrHrBteNpMUi/q3yKiPlRcA7kZo+aM+gVvbl0BHZoTceWqYRI64kpafYvEIA3r fk4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=kEZMUYaytNPYVnvdmUwTXFQcXwltXvxGgn6PoSnchC8=; b=BKP8olSCbBPpxdPnOZP5/PZ55C9+cyZNMdfWoNWnCL7kxrSRYZ5dxtvnRjhlcXhY2M 6AVvgeiwHp0IHExg34L1bC+j31BZNufa8IJEmJUGsMi3MkkyAwatGUcKth6F5TQvLUTo FYP+StHeseNWXG5ooYXDAPaPOKDdAyRQNYXjNLjT18NHfhMmyYIaVL2LqQkrv8pFssOk ZPiDExgSPZ/XR6Uu064049QacQnu5uoseJiWx7ljUok8q9YZAo4FP9aIWzhZZK80bNM2 8trjWMpdXocyVtxVI9tza+ODYBC//TkvyLjASXLtZqQxZvYPCuHdJYHSMcMbhl5eALNs zc+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dGBhcnR4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:27 -0700 Message-Id: <20180809034033.10579-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PATCH 05/11] target/arm: Fix typo in helper_sve_ld1hss_r X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: qemu-stable@nongnu.org (3.0.1) Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index c3cbec9cf5..e03f954a26 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4045,7 +4045,7 @@ DO_LD1(sve_ld1bdu_r, cpu_ldub_data_ra, uint64_t, uint8_t, ) DO_LD1(sve_ld1bds_r, cpu_ldsb_data_ra, uint64_t, int8_t, ) DO_LD1(sve_ld1hsu_r, cpu_lduw_data_ra, uint32_t, uint16_t, H1_4) -DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int8_t, H1_4) +DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int16_t, H1_4) DO_LD1(sve_ld1hdu_r, cpu_lduw_data_ra, uint64_t, uint16_t, ) DO_LD1(sve_ld1hds_r, cpu_ldsw_data_ra, uint64_t, int16_t, ) From patchwork Thu Aug 9 03:40:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 143651 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1577277ljj; Wed, 8 Aug 2018 20:46:55 -0700 (PDT) X-Google-Smtp-Source: AA+uWPy8Dee2VxqsDOIvHq3zorXjVIytZclzJf7vmZVKaKAnIoNpivjbUJjP73fYF0F2h+xCfYfz X-Received: by 2002:a0c:e7ca:: with SMTP id c10-v6mr366894qvo.48.1533786415129; Wed, 08 Aug 2018 20:46:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533786415; cv=none; d=google.com; s=arc-20160816; b=yX327Lls29Y8zKLrCzQt7DInziZH7L5/WDzmpxFVK5xfBZS7bwYSMHogPZ0btsxH9k 250nrgWh4ZuxxlEiX2broAyUgOnrT0idyZQ/7YK7RgQhnlJE7hVNwYGrTvFeW5T+vD5d d2gJzxvPq0aQap2zk1WIrmGLGHIfoffyQCw56lPduEfwy2cjA9A/RyEzVh2JAUrHTmJb 0awZ0yKFHulGf9TP7gutjbwnpCKhC0eaOOLX8TBWwcOOyB2Wd14+EcHd74PS2SdGNVoJ N90rv5k4EinlpDCmVvbxTtys6yucD8N/0SHxm7lUCInLRX0Me2Fm7YvRAWDOdIShI6rA laWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=6a/GOR0oVfrC4aMp6j4tHYOY3mUq7Mczl/rWUwhb0gg=; b=KD4gAB7k8zvJd4MjDo7jZk1mLdRRwQt0pkwZEHhSeNuy1nlLyJ3lkh8Rs5+SNBOAHp 1/zIkdCU/HIbk0yt5neyoRTIX4jiy9+f18J6rgyrMCHPVkM2hUQMFsLkWIIX6vYZ6MRC kjkmvLooovfdYJejnUa2XQOJVAmZlxyaHLS0E2YBsQ7/GR1t279ow928uWLNKjBaj+2K 3uH9ws3R/sE3ITX0Hxvu/EtETE9aLGPW+t37eQE3XB7PKpbAaAgZbpIXjUrzXNG21w9g IoM2h7vpLsypB4zeKXs+RKbaRkzXsF+rXAZqhw0uA53v1FrFd+Sn70yR2wm/Vh7GE7s2 oUnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ebzIbn4n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:28 -0700 Message-Id: <20180809034033.10579-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 06/11] target/arm: Fix sign-extension in sve do_ldr/do_str X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The expression (int) imm + (uint32_t) len_align turns into uint32_t and thus with negative imm produces a memory operation at the wrong offset. None of the numbers involved are particularly large, so change everything to use int. Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) -- 2.17.1 Tested-by: Laurent Desnogues Reviewed-by: Laurent Desnogues Reviewed-by: Alex Bennée diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 89efc80ee7..9e63b5f8e5 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4372,12 +4372,11 @@ static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) * The load should begin at the address Rn + IMM. */ -static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len, - int rn, int imm) +static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) { - uint32_t len_align = QEMU_ALIGN_DOWN(len, 8); - uint32_t len_remain = len % 8; - uint32_t nparts = len / 8 + ctpop8(len_remain); + int len_align = QEMU_ALIGN_DOWN(len, 8); + int len_remain = len % 8; + int nparts = len / 8 + ctpop8(len_remain); int midx = get_mem_index(s); TCGv_i64 addr, t0, t1; @@ -4458,12 +4457,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len, } /* Similarly for stores. */ -static void do_str(DisasContext *s, uint32_t vofs, uint32_t len, - int rn, int imm) +static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) { - uint32_t len_align = QEMU_ALIGN_DOWN(len, 8); - uint32_t len_remain = len % 8; - uint32_t nparts = len / 8 + ctpop8(len_remain); + int len_align = QEMU_ALIGN_DOWN(len, 8); + int len_remain = len % 8; + int nparts = len / 8 + ctpop8(len_remain); int midx = get_mem_index(s); TCGv_i64 addr, t0; From patchwork Thu Aug 9 03:40:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 143652 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1578694ljj; Wed, 8 Aug 2018 20:49:03 -0700 (PDT) X-Google-Smtp-Source: AA+uWPx3g3jqXQs+DVwwRtHlnL7+Y4DYiZLvxURSOFg19ME7uIsQwaOYPIplj+iVdyLIXQoF8WNN X-Received: by 2002:ac8:3913:: with SMTP id s19-v6mr393615qtb.344.1533786543508; Wed, 08 Aug 2018 20:49:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533786543; cv=none; d=google.com; s=arc-20160816; b=guPh5rPi5fCgnEFmAfR99nZK5yQswXKO+t1fC1cqZqdF4c9FzEmMisxcA75Q+2uw/l vrDGcWVK7DPkkkcyLPdVGjv5cP1qtV3lRfIe0Mu2YZ51nxNToWRXejJRsJP+BB5axEdD saDFzcWj4n0g4xKxh90LYRUS3Ig/i4Jnltz9i3/rUukAv4GMtGcxGIYTUnwU+xnWhbae v77M8+NnFGzpcFa0p5GG3olP40fFV3jmywtUGUNfqA1DNI+PxmP7Bm2XsGIR3Fkgkew1 6yAoSdB0NuQn1KRlButO4Pvs6LQ4z/piD41QshU5pUtx5a9Odf0M6b3TOTTgME1m6Vvz p/ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=oR7/ZohV9ZWM7zkPc+xrlk2h0PYh/osElGNKWerwJO0=; b=YqgVCWVaR3wAXlvHe1NB/eOHqGsUoTj4N4VLrZvDUxLip6cFELxCnIeVLd4xWvVwJy yW+t7h1dd3xcT9DJOTLpuNrkOvfIP8/TMWF5J9VNjonpgnS/AE7WPw7qTj4hQUlJzzAh KCAHoraFIZ66fooQJBMX8Z9z+6a9ga7lEg9IJSo2BHChsGMktG7YDQ5ZLWByWEbWWW8p tuDQqUiPV23/AzpaKymddrzwBTIT9SOFWzJw+f4lBoWO6RoXm+OErCO52YMw6sC+T1Ih Qji7BdaSLW88B5YUiQmK2+GBcZx9VJGyQOt7jkZDFaj9vRGYm0BGw+VT/nfwa0zlMxKk 8wCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XXZM90Qc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:29 -0700 Message-Id: <20180809034033.10579-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22a Subject: [Qemu-devel] [PATCH 07/11] target/arm: Fix offset for LD1R instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The immediate should be scaled by the size of the memory reference, not the size of the elements into which it is loaded. Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 Tested-by: Laurent Desnogues Reviewed-by: Laurent Desnogues diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9e63b5f8e5..f635822a61 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4819,6 +4819,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn) unsigned vsz = vec_full_reg_size(s); unsigned psz = pred_full_reg_size(s); unsigned esz = dtype_esz[a->dtype]; + unsigned msz = dtype_msz(a->dtype); TCGLabel *over = gen_new_label(); TCGv_i64 temp; @@ -4842,7 +4843,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn) /* Load the data. */ temp = tcg_temp_new_i64(); - tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << esz); + tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s), s->be_data | dtype_mop[a->dtype]); From patchwork Thu Aug 9 03:40:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 143653 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1579623ljj; Wed, 8 Aug 2018 20:50:29 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzXVVaGCWTPwNYUG0bAU4d5Ita09EY5JpUyMyS3sVwl2aXUts3uSKMmCDmO+mWRa845kBDF X-Received: by 2002:ac8:3477:: with SMTP id v52-v6mr384694qtb.316.1533786629148; Wed, 08 Aug 2018 20:50:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533786629; cv=none; d=google.com; s=arc-20160816; b=fmA2hXf2TdHNdk2Zk44uu6zYaQTnSECT164VgH57Pi7r7sB6XniBcHvfWxKi6xe9PA XV+CXvDqGXF1u9VrFYZ/txH4zQ2PMa0tt87eFonOwt/IU3SVhyIQgL92+f3GuM8AkjDA mKmtPduwypDcYio+vSGUNSjvyx63Ac9agipFDyUCAgG7zUP0fJnE2GmsdFwiIHRkq24G EQIWksu+q3XkyUtr2733N0BLIaCHipkPq3CJ/tn2QXDQ3UM2gnkz7TKUqvzZNv9p8vE3 d1fNvtyZA8CeldxpbmtV1O009tsamVFNd7Yv91VOzIkcAlE1fmFUfkm+lZfswhVWNK1C tvJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=u5hBbJUuDc7/ufplT19/aY8WnnQKtZVUsYURNw4zFxs=; b=dWOPH+HRcPkpGL9yGEulV/ztwTCeI78ReuPs87Vr9LIk6IsWMFDtQ3eVgEMMW6nIi3 x2fKDrtpeXriKs1ajxZ25jvUwE2IKWuGe+aTCKagSNU60P6ruPw8wGFDx1XAVhmYxquu YiSJ1djjKNe6ZA1hdsO4M6ztWJdVexIVpksbFAVxwZmdUm/v2c+sPu/bEhsX+zJCuqp3 9ZG766WTGG7jy5ub+1BpAZ+ALdCQzSKRvFoA0d61APbKP/P/FjG3pzZwm7twU0mugTLI UMOxNuFzkEtoIu8u8899Q7gYIFfkWr7Wteemx7sOhideE/9YA83ubcIk0ZTrypApy4ol 8j5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HZ41eiFH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:30 -0700 Message-Id: <20180809034033.10579-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH 08/11] target/arm: Fix offset scaling for LD_zprr and ST_zprr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The scaling should be solely on the memory operation size; the number of registers being loaded does not come in to the initial computation. Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.17.1 Tested-by: Laurent Desnogues Reviewed-by: Laurent Desnogues diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index f635822a61..d27bc8c946 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4665,8 +4665,7 @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn) } if (sve_access_check(s)) { TCGv_i64 addr = new_tmp_a64(s); - tcg_gen_muli_i64(addr, cpu_reg(s, a->rm), - (a->nreg + 1) << dtype_msz(a->dtype)); + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg); } @@ -4899,7 +4898,7 @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t insn) } if (sve_access_check(s)) { TCGv_i64 addr = new_tmp_a64(s); - tcg_gen_muli_i64(addr, cpu_reg(s, a->rm), (a->nreg + 1) << a->msz); + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg); } From patchwork Thu Aug 9 03:40:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 143646 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1576128ljj; Wed, 8 Aug 2018 20:45:18 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxpsynnU1WduzD8F05mbQszk3F06sTBwddaMtjuiqbq1poCvLlr9yyKKTF0XfYDEh5BunzK X-Received: by 2002:aed:3e14:: with SMTP id l20-v6mr400142qtf.62.1533786318449; Wed, 08 Aug 2018 20:45:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533786318; cv=none; d=google.com; s=arc-20160816; b=ZAoIkGmiTk3YK+yfyGMKvZjcsB9NostDDHJVA3kyl+V54FKPpeSrvPFUhqGXH+V9ud bCe2dSgO2u3fM3gsEyEtidQau0GpHA8SLv6IJb5vV05lW2XR843/h9DRzt2PYCtS3O9n 4u2LVYpOV2tCBSDOsWycxTnBLxPlGKQ7xP1HhVArMQESnN08aZgiKPkyJ4G3fwS2C+YK I+aKKRJwPUuuKy27XoK59SyemzxjMP2Lwzg96KCARPRNZNjw0DInqX8Y4whP5dGlxHzo PPkGreUWiCg8TQQeZq90CNsIERUP5RR2879BeHmyEfr89gMpegpPtjuMyp8B2JceJ23z 2zNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ibaa2x/FVJzOL9C446Qkj9eSHPvGG5P1FYKx2aZVL6Q=; b=yihLs49AMNNh8UNS/ZPjeRnnV2Ao4/0ffAifePaYomxgd2f1eNywvcya2L62pQwHU6 oDOuR5kmMoGE25BYU59O5YUq2TF8KzVOeTmPaKjOrCpcBUh3d/UO7l5I7+bM4fuL2BHd SA0AaloORVu8eXhEAVYrG472ZalGvItuJVLDQAOPl4Fp/kI6zJ6lyvDqCHPzCGcEPRi2 ZWlFREdvYNE1UnKrrm/wPaB7GigvhUtVWE2YO91ntl+xnEZR4qDNGHgoX6Iv9mxWBifx WVx6DoGQRqF2TZyi/DL6G375KhGmV1sNlk7Ck35JklnH/yT7zk380UJxqQnUxlbC6MkF yb8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iYIPfgxf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:31 -0700 Message-Id: <20180809034033.10579-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22e Subject: [Qemu-devel] [PATCH 09/11] target/arm: Reformat integer register dump X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With PC, there are 33 registers. Three per line lines up nicely without overflowing 80 columns. Cc: qemu-stable@nongnu.org (3.0.1) Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée Reviewed-by: Alex Bennée diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 45a6c2a3aa..358f169c75 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -137,14 +137,13 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int el = arm_current_el(env); const char *ns_status; - cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", - env->pc, env->xregs[31]); - for (i = 0; i < 31; i++) { - cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]); - if ((i % 4) == 3) { - cpu_fprintf(f, "\n"); + cpu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); + for (i = 0; i < 32; i++) { + if (i == 31) { + cpu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); } else { - cpu_fprintf(f, " "); + cpu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], + (i + 2) % 3 ? " " : "\n"); } } From patchwork Thu Aug 9 03:40:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 143647 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1576494ljj; Wed, 8 Aug 2018 20:45:50 -0700 (PDT) X-Google-Smtp-Source: AA+uWPz7U6UkCVl2sUcyNm4Ugng6yK5fEHpz/3gebbuhHPnR0kNDkh2pPXiJhS5m2z/ujP4VNJSo X-Received: by 2002:aed:3ea5:: with SMTP id n34-v6mr366447qtf.275.1533786350435; Wed, 08 Aug 2018 20:45:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533786350; cv=none; d=google.com; s=arc-20160816; b=aoQb6kgs7E8Bl52cVzXfmS7JOTVbjHLedJAOqH2DmhHahmBZBavnvA7dMrgX6infgT /wY7AsCVtKPC+tSeXQnAJQWIulxeGOfSIfpuPmL8Yg8233NSU8l/dmHYuAd0C+hpv1eY nuIxb24cV56NUA2zVRDebUIUZZ9UD5WnRHCgIFTwQyaQB1qqW/ONcn8du7KTufJdiIrq kC+jyDjKpAo4PAB550ahQZjoLLSzN1v9wVJfCyTa65gTXSttQkaIQ0Jpuz5qw3Rp6oRb jhQ0rCtuol5MfR/fo6UdJt7C/moSkzVL9x//XIP0oNFngv2Hd4hH6RR6/AIDmNpK+hgF awhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=0FcppwMQ/VVPQuPzY24/U6P82x5KiB0C2CbAGzzrE6M=; b=yTw4Ltr990GIunb8R6DJjl6wL45p6CXYwITyA6uJA2z0pkiWNDI/cpxMRBqZd8ItMD Nz0LTtJWa6JKulwsKSMyTUwD00EPJ6Sa4HVjFv1sj45FvPV3l7t/VRRzH/0AGKpR7hYN PgVPrUNn7vHwwKXeGu1yzLHRc+ZbNH1+3VhTj+KKwltTuTRRZTtU/ukW7enpQTfxUXpE 28PY+RqrLaG7Y31JoZkfXky2cWA4USZTboPmZ1c8ppyrui1JmAjGcc4kHvjRIYkPoZ1O VkPDw7suMKd9QNhjt921fXXCBxS8wyE+3wGYD5ZCXmyhB0ssGKwpBT8Ph5VoYycJo0sP J4SA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=S7aUEd8E; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:32 -0700 Message-Id: <20180809034033.10579-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::232 Subject: [Qemu-devel] [PATCH 10/11] target/arm: Dump SVE state if enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Also fold the FPCR/FPSR state onto the same line as PSTATE, and mention but do not dump disabled FPU state. Cc: qemu-stable@nongnu.org (3.0.1) Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 95 +++++++++++++++++++++++++++++++++----- 1 file changed, 83 insertions(+), 12 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée Tested-by: Alex Bennée diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 358f169c75..b29dc49c4f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -152,8 +152,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, } else { ns_status = ""; } - - cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n", + cpu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", psr, psr & PSTATE_N ? 'N' : '-', psr & PSTATE_Z ? 'Z' : '-', @@ -163,17 +162,89 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, el, psr & PSTATE_SP ? 'h' : 't'); - if (flags & CPU_DUMP_FPU) { - int numvfpregs = 32; - for (i = 0; i < numvfpregs; i++) { - uint64_t *q = aa64_vfp_qreg(env, i); - uint64_t vlo = q[0]; - uint64_t vhi = q[1]; - cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "%c", - i, vhi, vlo, (i & 1 ? '\n' : ' ')); + if (!(flags & CPU_DUMP_FPU)) { + cpu_fprintf(f, "\n"); + return; + } + cpu_fprintf(f, " FPCR=%08x FPSR=%08x\n", + vfp_get_fpcr(env), vfp_get_fpsr(env)); + + if (arm_feature(env, ARM_FEATURE_SVE)) { + int j, zcr_len = env->vfp.zcr_el[1] & 0xf; /* fix for system mode */ + + for (i = 0; i <= FFR_PRED_NUM; i++) { + bool eol; + if (i == FFR_PRED_NUM) { + cpu_fprintf(f, "FFR="); + /* It's last, so end the line. */ + eol = true; + } else { + cpu_fprintf(f, "P%02d=", i); + switch (zcr_len) { + case 0: + eol = i % 8 == 7; + break; + case 1: + eol = i % 6 == 5; + break; + case 2: + case 3: + eol = i % 3 == 2; + break; + default: + /* More than one quadword per predicate. */ + eol = true; + break; + } + } + for (j = zcr_len / 4; j >= 0; j--) { + int digits; + if (j * 4 + 4 <= zcr_len + 1) { + digits = 16; + } else { + digits = (zcr_len % 4 + 1) * 4; + } + cpu_fprintf(f, "%0*" PRIx64 "%s", digits, + env->vfp.pregs[i].p[j], + j ? ":" : eol ? "\n" : " "); + } + } + + for (i = 0; i < 32; i++) { + if (zcr_len == 0) { + cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", + i, env->vfp.zregs[i].d[1], + env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); + } else if (zcr_len == 1) { + cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 + ":%016" PRIx64 ":%016" PRIx64 "\n", + i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], + env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); + } else { + for (j = zcr_len; j >= 0; j--) { + bool odd = (zcr_len - j) % 2 != 0; + if (j == zcr_len) { + cpu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); + } else if (!odd) { + if (j > 0) { + cpu_fprintf(f, " [%x-%x]=", j, j - 1); + } else { + cpu_fprintf(f, " [%x]=", j); + } + } + cpu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", + env->vfp.zregs[i].d[j * 2 + 1], + env->vfp.zregs[i].d[j * 2], + odd || j == 0 ? "\n" : ":"); + } + } + } + } else { + for (i = 0; i < 32; i++) { + uint64_t *q = aa64_vfp_qreg(env, i); + cpu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", + i, q[1], q[0], (i & 1 ? "\n" : " ")); } - cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", - vfp_get_fpcr(env), vfp_get_fpsr(env)); } } From patchwork Thu Aug 9 03:40:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 143654 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1580791ljj; Wed, 8 Aug 2018 20:52:16 -0700 (PDT) X-Google-Smtp-Source: AA+uWPx7JkCzUNcupMPNhInedyQziqo90AzyNokHK42e+/XRPfuhIdRvUP03IJewSK7Rjz2Vrc4Y X-Received: by 2002:a0c:d4d7:: with SMTP id y23-v6mr356094qvh.234.1533786736365; Wed, 08 Aug 2018 20:52:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533786736; cv=none; d=google.com; s=arc-20160816; b=nTC/sVC7CvFVjKw+ZSXz6YpZEk20kvXM7zcr35Q45xn1swu0IS4lscvk9RH/0La1HC 2/70YJVdYPDWkLSy0JNRx/896HEjX0dWHHgdLLZXKmbQIexVAXavUa7g2tjunuTKStn+ vidsH5A8E6owRjomBF1KQe7YeXwRP1NO8N6axIYmCNleQnxSS6VEZOvuEJW6SBlEbXBz OC4rAuvtjhFoVf7iClt+IphDSvjbj3hj03C57i1Wzp2IY4iVH2QpAYPvBrLjg7verHzN 6Qz7xD59kIiY9GedHiT7Pdz++mYzktLW/EEpxb4zOdV7p/HgQlQ1Rj7SRr+gOBcaqFDV l64Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=RTV9YUpP5y3oJ9ECtxuaAeHR5syAJ7q9647bx+XF62o=; b=Y/hMIKbL3fjMYRHE0pVHt/V7ui7Z4wSmSnmH7Q5pOeJtldqDv81HP35G3ONoxouhzY KQEBgtnQRXFdXafl/Na1lM23WKC6XSzMIwFXj6jdEPeTPBhyrtJCh4fyupSxmzIvKwUu M5Jet2amqDQ/BEHXdq1ebR8s2171hoIfd1MrOZ8oIQk6I1vGK/7ll0+rrCgCkKEzv0E9 OYZQtL639odfaDvYEl+hyhyAIj3CP9wZeB9UxBxpsoKWeKA8DpriiJRkR8OZ/5/r+tvt u+wlqWSVPZ/0ckgs7L2bMkVXQxe5Rx2YC0aIKhzM6M3x8QSfhPrhqD7ABL7lWEd/sRX3 ugdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=b0RwnkoG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:33 -0700 Message-Id: <20180809034033.10579-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 11/11] target/arm: Add sve-max-vq cpu property to -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows the default (and maximum) vector length to be set from the command-line. Which is extraordinarily helpful in debuging problems depending on vector length without having to bake knowledge of PR_SET_SVE_VL into every guest binary. Cc: qemu-stable@nongnu.org (3.0.1) Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 +++ linux-user/syscall.c | 19 +++++++++++++------ target/arm/cpu.c | 6 +++--- target/arm/cpu64.c | 29 +++++++++++++++++++++++++++++ target/arm/helper.c | 7 +++++-- 5 files changed, 53 insertions(+), 11 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée Tested-by: Alex Bennée diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e310ffc29d..9526ed27cb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -857,6 +857,9 @@ struct ARMCPU { /* Used to synchronize KVM and QEMU in-kernel device levels */ uint8_t device_irq_level; + + /* Used to set the maximum vector length the cpu will support. */ + uint32_t sve_max_vq; }; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index dfc851cc35..5a4af76c03 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10848,15 +10848,22 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, #endif #ifdef TARGET_AARCH64 case TARGET_PR_SVE_SET_VL: - /* We cannot support either PR_SVE_SET_VL_ONEXEC - or PR_SVE_VL_INHERIT. Therefore, anything above - ARM_MAX_VQ results in EINVAL. */ + /* + * We cannot support either PR_SVE_SET_VL_ONEXEC or + * PR_SVE_VL_INHERIT. Note the kernel definition + * of sve_vl_valid allows for VQ=512, i.e. VL=8192, + * even though the current architectural maximum is VQ=16. + */ ret = -TARGET_EINVAL; if (arm_feature(cpu_env, ARM_FEATURE_SVE) - && arg2 >= 0 && arg2 <= ARM_MAX_VQ * 16 && !(arg2 & 15)) { + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { CPUARMState *env = cpu_env; - int old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; - int vq = MAX(arg2 / 16, 1); + ARMCPU *cpu = arm_env_get_cpu(env); + uint32_t vq, old_vq; + + old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; + vq = MAX(arg2 / 16, 1); + vq = MIN(vq, cpu->sve_max_vq); if (vq < old_vq) { aarch64_sve_narrow_vq(env, vq); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 64a8005a4b..b25898ed4c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -168,9 +168,9 @@ static void arm_cpu_reset(CPUState *s) env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cptr_el[3] |= CPTR_EZ; /* with maximum vector length */ - env->vfp.zcr_el[1] = ARM_MAX_VQ - 1; - env->vfp.zcr_el[2] = ARM_MAX_VQ - 1; - env->vfp.zcr_el[3] = ARM_MAX_VQ - 1; + env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; + env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; + env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d0581d59d8..800bff780e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -29,6 +29,7 @@ #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "kvm_arm.h" +#include "qapi/visitor.h" static inline void set_feature(CPUARMState *env, int feature) { @@ -217,6 +218,29 @@ static void aarch64_a53_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } +static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + visit_type_uint32(v, name, &cpu->sve_max_vq, errp); +} + +static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + Error *err = NULL; + + visit_type_uint32(v, name, &cpu->sve_max_vq, &err); + + if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) { + error_setg(&err, "unsupported SVE vector length"); + error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n", + ARM_MAX_VQ); + } + error_propagate(errp, err); +} + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -253,6 +277,10 @@ static void aarch64_max_initfn(Object *obj) cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ #endif + + cpu->sve_max_vq = ARM_MAX_VQ; + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq, + cpu_max_set_sve_vq, NULL, NULL, &error_fatal); } } @@ -405,6 +433,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) uint64_t pmask; assert(vq >= 1 && vq <= ARM_MAX_VQ); + assert(vq <= arm_env_get_cpu(env)->sve_max_vq); /* Zap the high bits of the zregs. */ for (i = 0; i < 32; i++) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 66afb08ee0..c24c66d43e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12408,9 +12408,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, zcr_len = 0; } else { int current_el = arm_current_el(env); + ARMCPU *cpu = arm_env_get_cpu(env); - zcr_len = env->vfp.zcr_el[current_el <= 1 ? 1 : current_el]; - zcr_len &= 0xf; + zcr_len = cpu->sve_max_vq - 1; + if (current_el <= 1) { + zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + } if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); }