From patchwork Thu Aug 9 13:40:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 143860 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2109794ljj; Thu, 9 Aug 2018 06:40:28 -0700 (PDT) X-Google-Smtp-Source: AA+uWPySn6ZJq9iFKbE+rZNc74x2DqGdDjae9kof/lN6o0L2DtsSumDkeVJMZtQYx7E86UDja8Bj X-Received: by 2002:a62:a05:: with SMTP id s5-v6mr2436672pfi.147.1533822028560; Thu, 09 Aug 2018 06:40:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533822028; cv=none; d=google.com; s=arc-20160816; b=YCTpFmFnQNPybH+WUiOlN5/sVlGfKM/6Oi6dndggxbFeI+YyrM6x5KXRZEvXBuFcfu Sw13D4E4l0m/pKQEz2mRIhnL1iUdq+7te9/LsxDxBmftCFxM89fk9/d/uAEA3+BQ6QME nCzCuwar+arOY9Tv9LM+p1DrEHyKcqTrglnvZoBNM32qWxPkpLfUqEdKVHYoNL4qulu/ Dy7MLTAeHwWOnuxfKvWFnsfthQvHjEbi4c31q5F51WI1sLM/201LsAonNak4tEGZhrbq RtgmYcwAjkDgHxinXGFe/iP+TfpVcF6t1b+7C0HpQ7LaOPIiOMz/ZFbZnW5tNOEk0gKh ab3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:date:message-id:openpgp:subject:from:to :delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=dM5+5NfEmBcuiB/ULHeOuMP0EPJnfHCuDWoOY3+QCaY=; b=fbaShPF7/01eBj42S5glbl9Z3eOFgzgG6+T3ytO+1YyNJeEG1RjnMmADuC6BhoEIcH jgKW4xPHyOrdAWjSRx/X7yKu1BimfR/N3N88IjmxVnRn5WcyqcUtWR4F3pr7pXS4Y5WE bqiVxWmK1GIUCyvJpzYbnsj63uf7rq4bNZgkBVocaMvIlPwT8rYdKKdWjoow6AopeNCg 4jtjpHWK6OOZiMpMG+x80ro5jDq/Prft39mcxp/WFXlQPRyWgPxwttf8URmdyz6NHstt gr1eTJLK0hJDA+jJYhRon2G3XLVMGubJxc9HD468dPGpxeHeWMyXwUNNHDWIAc8oCK26 xwpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=TaRXszar; spf=pass (google.com: domain of gcc-patches-return-483454-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-483454-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id ba4-v6si5701373plb.240.2018.08.09.06.40.28 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Aug 2018 06:40:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-483454-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=TaRXszar; spf=pass (google.com: domain of gcc-patches-return-483454-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-483454-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=UknZTS18n81FrxDoOKgd8JSRH8llpusesB1U25+2iEypRl9fHs 1gtPMXzf2tsZs5fFU2mYZ2VUa8SfipeAa9XzAfGNVRbMCWfNng26LYqt28aVVjDA GmnoLlF6/dDCe7e1qrfTauO+HjBccoBWEioFSgOJ6yqhMHd30HCnTWcgI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=b1Nq80VGS4dCnQE8OQFlFZ1qjTY=; b=TaRXszarA6NjljEdGbF6 2UgHl5aLEAiYMw05/uH2GknPekYucBhgm0PEZZ7X8iOHyZA/r7IPWZUG2k95r05Y QOq2Ppaqb8blWqluJxNNekJ9z5AX/RpYoMp2aTejwnH3g8PdTFCl52cEz8LwPgKa L5Vthl/g6B4rVNdO1/zE3ds= Received: (qmail 66287 invoked by alias); 9 Aug 2018 13:40:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 66277 invoked by uid 89); 9 Aug 2018 13:40:16 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 09 Aug 2018 13:40:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2A42B80D; Thu, 9 Aug 2018 06:40:13 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A608E3F5B3; Thu, 9 Aug 2018 06:40:12 -0700 (PDT) To: gcc-patches From: "Richard Earnshaw (lists)" Subject: aarch64 - PR target/86887 Fix missing register constraints in carryin patterns Openpgp: preference=signencrypt Message-ID: Date: Thu, 9 Aug 2018 14:40:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 Some of the carryin insn patterns are missing a register constraint. That means that the register allocator can pick practically anything to hold that value, including memory locations, or registers of the wrong class. PR target/86887 * config/aarch64/aarch64.md (add3_carryinC_zero): Add missing register constraint to operand 0. (add3_carryinC): Likewise. (add3_carryinV_zero, add3_carryinV): Likewise. R. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 955bf18..a73ecc7 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2429,7 +2429,7 @@ (define_insn "*add3_carryinC_zero" (plus:GPI (match_operand:GPI 3 "aarch64_carry_operation" "") (match_dup 1))))) - (set (match_operand:GPI 0 "register_operand") + (set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (match_dup 3) (match_dup 1)))] "" "adcs\\t%0, %1, zr" @@ -2450,7 +2450,7 @@ (define_insn "*add3_carryinC" (match_operand:GPI 4 "aarch64_carry_operation" "") (match_dup 1)) (match_dup 2))))) - (set (match_operand:GPI 0 "register_operand") + (set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (plus:GPI (match_dup 4) (match_dup 1)) (match_dup 2)))] @@ -2495,7 +2495,7 @@ (define_insn "*add3_carryinV_zero" (plus:GPI (match_operand:GPI 3 "aarch64_carry_operation" "") (match_dup 1))))) - (set (match_operand:GPI 0 "register_operand") + (set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (match_dup 3) (match_dup 1)))] "" "adcs\\t%0, %1, zr" @@ -2516,7 +2516,7 @@ (define_insn "*add3_carryinV" (match_operand:GPI 4 "aarch64_carry_operation" "") (match_dup 1)) (match_dup 2))))) - (set (match_operand:GPI 0 "register_operand") + (set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (plus:GPI (match_dup 4) (match_dup 1)) (match_dup 2)))]