From patchwork Fri Aug 10 14:20:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 143931 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp15787ljj; Fri, 10 Aug 2018 07:21:43 -0700 (PDT) X-Google-Smtp-Source: AA+uWPx5FL2ZPyu6qO47DbAkBfe0eZnUXK8uCWKlDDvv2God1edMUX98H5wvY2dYF6AJ9Jomwq11 X-Received: by 2002:a17:902:14cb:: with SMTP id y11-v6mr6357818plg.317.1533910903830; Fri, 10 Aug 2018 07:21:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533910903; cv=none; d=google.com; s=arc-20160816; b=HSVQ7k7tzPq5d1qnthNZIq8Sm1Vr501T0Vj2TncrMlE1r8xInq2HftrdqRgqZgWe3I e5nJ/9iuf8sgy9wxpb9i7eh4VmYIKXzGWcu7ta5p3YWLIHC/crdVEtd1962r87kNLisA NTAnIwDbjCJyrgQjALPQ2ZLx6mtLxheAjA+a5lwnuzaVaKUDaY5MXwx4NySbw+413ebx hNkLOgf8aUvaeaa9w9H60aadDL06KpC+rzhz3U7U25Mz2A8U83IazApr4Fev1H4W89Nd TxRhKQRT6+pWjcO09tL3WsAWAQdomlybNRnX5k052dLBr3K7tFqf01rRWl3awkxsrdGs T/Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=n5Fk+QSieIDr78QoVoz95w1f7JIKqQlBkHuUssyUCpQ=; b=BRNeJZDlbccaE2A45GtPc4fNH79D+YsKy3xNvNyZnSPl9rO68f4InhS3vmEPUr6Rnc 4TR6VsFC+q9LdyOCqkalN2Zd1dhNcsGXEOFNjC9bxipvBQQQ/LaZPHJOQq2Cro0D8pQS RvQqQlevhdDxX64ReMNnFEfrnWKJgTLpaWA0QSwBOyseDx15+p4ORe3odj/dLjaSezJ9 nD0UpJXmiJI6MoW/YvxJzWPmboXcMdVG3W6kHeLEayVPTxU1yO4CxNOk6Avd7a/VA5zV bjZ5rQVHMMF+KimATROlMI5xYqGHj8yxPcse3RHumYVDIIIV262fa+74dWEqeDCe49Ul aOJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iQENPb20; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 91-v6si7981107ply.405.2018.08.10.07.21.43; Fri, 10 Aug 2018 07:21:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iQENPb20; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728159AbeHJQvt (ORCPT + 4 others); Fri, 10 Aug 2018 12:51:49 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:52261 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728064AbeHJQvt (ORCPT ); Fri, 10 Aug 2018 12:51:49 -0400 Received: by mail-wm0-f65.google.com with SMTP id o11-v6so2091915wmh.2 for ; Fri, 10 Aug 2018 07:21:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n5Fk+QSieIDr78QoVoz95w1f7JIKqQlBkHuUssyUCpQ=; b=iQENPb20rXhT5BoKN8O6fkLyEkgNpr7VlJnf5qwG6ChB7TtDrKeQsDdDIQr9sUD3zp rsbeGCobsNLl1brkIP/6j9UCNMTJPxHKCGjbhDBse/sWD00N2pImGKN7wZ2G6gynkeho AJ/eullZE/3JhzO+8HwLywGe6sFpr64Hf2STU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n5Fk+QSieIDr78QoVoz95w1f7JIKqQlBkHuUssyUCpQ=; b=ApzYeh7hI9igco50tNdG+8KWvQeszVQntL4IsKjoQUPhHhDcwygj6DKSG19S+UngU2 2PM91BXggLfZ8CDTtHyk2QXKOEwHrZhT8jUMbz5+5bc7sQAU+3lpvIghERPu37fpbk8H z4DLh5eYXbf+Qf/it5iYyH4eArXO9z5KnFfaDL9104Wg4WNTRnABPDOwMjX9wjH4nEcD p/7Q8zaZBn+gl2LjgCZVItmhpps8CTOlcimrHQn8XAujIRDCurZY+cigPolojR6O55UO 849Lj92ch33IdtZ9vHdtlWUeiqB8pghO7yHsJGTr1bh0aKN6HcxytxBouCs8pMHpeN31 Y/pQ== X-Gm-Message-State: AOUpUlEJ1yqh0a9ln27ZtzFEOGMcbKmyiegUof6crsyTfh/44Nmsp5AR B51wsCfDM64SPF+Iab3D8ftp9Q== X-Received: by 2002:a1c:13ca:: with SMTP id 193-v6mr1607075wmt.127.1533910898426; Fri, 10 Aug 2018 07:21:38 -0700 (PDT) Received: from arch-late.local (a109-49-46-234.cpe.netcabo.pt. [109.49.46.234]) by smtp.gmail.com with ESMTPSA id b13-v6sm13077578wrn.17.2018.08.10.07.21.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Aug 2018 07:21:37 -0700 (PDT) From: Rui Miguel Silva To: mchehab@kernel.org, sakari.ailus@linux.intel.com, Philipp Zabel , Rob Herring Cc: linux-media@vger.kernel.org, devel@driverdev.osuosl.org, Fabio Estevam , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ryan Harkin , Rui Miguel Silva Subject: [PATCH v7 03/12] media: staging/imx7: add imx7 CSI subdev driver Date: Fri, 10 Aug 2018 15:20:36 +0100 Message-Id: <20180810142045.27657-4-rui.silva@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180810142045.27657-1-rui.silva@linaro.org> References: <20180810142045.27657-1-rui.silva@linaro.org> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This add the media entity subdevice and control driver for the i.MX7 CMOS Sensor Interface. Signed-off-by: Rui Miguel Silva --- drivers/staging/media/imx/Kconfig | 9 +- drivers/staging/media/imx/Makefile | 2 + drivers/staging/media/imx/imx7-media-csi.c | 1352 ++++++++++++++++++++ 3 files changed, 1362 insertions(+), 1 deletion(-) create mode 100644 drivers/staging/media/imx/imx7-media-csi.c -- 2.18.0 diff --git a/drivers/staging/media/imx/Kconfig b/drivers/staging/media/imx/Kconfig index bfc17de56b17..40a11f988fc6 100644 --- a/drivers/staging/media/imx/Kconfig +++ b/drivers/staging/media/imx/Kconfig @@ -11,7 +11,7 @@ config VIDEO_IMX_MEDIA driver for the i.MX5/6 SOC. if VIDEO_IMX_MEDIA -menu "i.MX5/6 Media Sub devices" +menu "i.MX5/6/7 Media Sub devices" config VIDEO_IMX_CSI tristate "i.MX5/6 Camera Sensor Interface driver" @@ -20,5 +20,12 @@ config VIDEO_IMX_CSI ---help--- A video4linux camera sensor interface driver for i.MX5/6. +config VIDEO_IMX7_CSI + tristate "i.MX7 Camera Sensor Interface driver" + depends on VIDEO_IMX_MEDIA && VIDEO_DEV && I2C + default y + ---help--- + A video4linux camera sensor interface driver for i.MX7. + endmenu endif diff --git a/drivers/staging/media/imx/Makefile b/drivers/staging/media/imx/Makefile index a30b3033f9a3..074f016d3519 100644 --- a/drivers/staging/media/imx/Makefile +++ b/drivers/staging/media/imx/Makefile @@ -12,3 +12,5 @@ obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx-media-ic.o obj-$(CONFIG_VIDEO_IMX_CSI) += imx-media-csi.o obj-$(CONFIG_VIDEO_IMX_CSI) += imx6-mipi-csi2.o + +obj-$(CONFIG_VIDEO_IMX7_CSI) += imx7-media-csi.o diff --git a/drivers/staging/media/imx/imx7-media-csi.c b/drivers/staging/media/imx/imx7-media-csi.c new file mode 100644 index 000000000000..7facb7fcbc67 --- /dev/null +++ b/drivers/staging/media/imx/imx7-media-csi.c @@ -0,0 +1,1352 @@ +// SPDX-License-Identifier: GPL +/* + * V4L2 Capture CSI Subdev for Freescale i.MX7 SOC + * + * Copyright (c) 2018 Linaro Ltd + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include "imx-media.h" + +#define IMX7_CSI_PAD_SINK 0 +#define IMX7_CSI_PAD_SRC 1 +#define IMX7_CSI_PADS_NUM 2 + +/* reset values */ +#define CSICR1_RESET_VAL 0x40000800 +#define CSICR2_RESET_VAL 0x0 +#define CSICR3_RESET_VAL 0x0 + +/* csi control reg 1 */ +#define BIT_SWAP16_EN BIT(31) +#define BIT_EXT_VSYNC BIT(30) +#define BIT_EOF_INT_EN BIT(29) +#define BIT_PRP_IF_EN BIT(28) +#define BIT_CCIR_MODE BIT(27) +#define BIT_COF_INT_EN BIT(26) +#define BIT_SF_OR_INTEN BIT(25) +#define BIT_RF_OR_INTEN BIT(24) +#define BIT_SFF_DMA_DONE_INTEN BIT(22) +#define BIT_STATFF_INTEN BIT(21) +#define BIT_FB2_DMA_DONE_INTEN BIT(20) +#define BIT_FB1_DMA_DONE_INTEN BIT(19) +#define BIT_RXFF_INTEN BIT(18) +#define BIT_SOF_POL BIT(17) +#define BIT_SOF_INTEN BIT(16) +#define BIT_MCLKDIV (0xF << 12) +#define BIT_HSYNC_POL BIT(11) +#define BIT_CCIR_EN BIT(10) +#define BIT_MCLKEN BIT(9) +#define BIT_FCC BIT(8) +#define BIT_PACK_DIR BIT(7) +#define BIT_CLR_STATFIFO BIT(6) +#define BIT_CLR_RXFIFO BIT(5) +#define BIT_GCLK_MODE BIT(4) +#define BIT_INV_DATA BIT(3) +#define BIT_INV_PCLK BIT(2) +#define BIT_REDGE BIT(1) +#define BIT_PIXEL_BIT BIT(0) + +#define SHIFT_MCLKDIV 12 + +/* control reg 3 */ +#define BIT_FRMCNT (0xFFFF << 16) +#define BIT_FRMCNT_RST BIT(15) +#define BIT_DMA_REFLASH_RFF BIT(14) +#define BIT_DMA_REFLASH_SFF BIT(13) +#define BIT_DMA_REQ_EN_RFF BIT(12) +#define BIT_DMA_REQ_EN_SFF BIT(11) +#define BIT_STATFF_LEVEL (0x7 << 8) +#define BIT_HRESP_ERR_EN BIT(7) +#define BIT_RXFF_LEVEL (0x7 << 4) +#define BIT_TWO_8BIT_SENSOR BIT(3) +#define BIT_ZERO_PACK_EN BIT(2) +#define BIT_ECC_INT_EN BIT(1) +#define BIT_ECC_AUTO_EN BIT(0) + +#define SHIFT_FRMCNT 16 +#define SHIFT_RXFIFO_LEVEL 4 + +/* csi status reg */ +#define BIT_ADDR_CH_ERR_INT BIT(28) +#define BIT_FIELD0_INT BIT(27) +#define BIT_FIELD1_INT BIT(26) +#define BIT_SFF_OR_INT BIT(25) +#define BIT_RFF_OR_INT BIT(24) +#define BIT_DMA_TSF_DONE_SFF BIT(22) +#define BIT_STATFF_INT BIT(21) +#define BIT_DMA_TSF_DONE_FB2 BIT(20) +#define BIT_DMA_TSF_DONE_FB1 BIT(19) +#define BIT_RXFF_INT BIT(18) +#define BIT_EOF_INT BIT(17) +#define BIT_SOF_INT BIT(16) +#define BIT_F2_INT BIT(15) +#define BIT_F1_INT BIT(14) +#define BIT_COF_INT BIT(13) +#define BIT_HRESP_ERR_INT BIT(7) +#define BIT_ECC_INT BIT(1) +#define BIT_DRDY BIT(0) + +/* csi control reg 18 */ +#define BIT_CSI_HW_ENABLE BIT(31) +#define BIT_MIPI_DATA_FORMAT_RAW8 (0x2a << 25) +#define BIT_MIPI_DATA_FORMAT_RAW10 (0x2b << 25) +#define BIT_MIPI_DATA_FORMAT_RAW12 (0x2c << 25) +#define BIT_MIPI_DATA_FORMAT_RAW14 (0x2d << 25) +#define BIT_MIPI_DATA_FORMAT_YUV422_8B (0x1e << 25) +#define BIT_MIPI_DATA_FORMAT_MASK (0x3F << 25) +#define BIT_MIPI_DATA_FORMAT_OFFSET 25 +#define BIT_DATA_FROM_MIPI BIT(22) +#define BIT_MIPI_YU_SWAP BIT(21) +#define BIT_MIPI_DOUBLE_CMPNT BIT(20) +#define BIT_BASEADDR_CHG_ERR_EN BIT(9) +#define BIT_BASEADDR_SWITCH_SEL BIT(5) +#define BIT_BASEADDR_SWITCH_EN BIT(4) +#define BIT_PARALLEL24_EN BIT(3) +#define BIT_DEINTERLACE_EN BIT(2) +#define BIT_TVDECODER_IN_EN BIT(1) +#define BIT_NTSC_EN BIT(0) + +#define CSI_MCLK_VF 1 +#define CSI_MCLK_ENC 2 +#define CSI_MCLK_RAW 4 +#define CSI_MCLK_I2C 8 + +#define CSI_CSICR1 0x0 +#define CSI_CSICR2 0x4 +#define CSI_CSICR3 0x8 +#define CSI_STATFIFO 0xC +#define CSI_CSIRXFIFO 0x10 +#define CSI_CSIRXCNT 0x14 +#define CSI_CSISR 0x18 + +#define CSI_CSIDBG 0x1C +#define CSI_CSIDMASA_STATFIFO 0x20 +#define CSI_CSIDMATS_STATFIFO 0x24 +#define CSI_CSIDMASA_FB1 0x28 +#define CSI_CSIDMASA_FB2 0x2C +#define CSI_CSIFBUF_PARA 0x30 +#define CSI_CSIIMAG_PARA 0x34 + +#define CSI_CSICR18 0x48 +#define CSI_CSICR19 0x4c + +struct imx7_csi { + struct device *dev; + struct imx_media_dev *md; + struct v4l2_subdev sd; + struct imx_media_video_dev *vdev; + struct imx_media_dev *imxmd; + struct media_pad pad[IMX7_CSI_PADS_NUM]; + + struct mutex lock; + spinlock_t irqlock; + + struct v4l2_subdev *src_sd; + + struct media_entity *sink; + + struct v4l2_fwnode_endpoint upstream_ep; + + struct v4l2_mbus_framefmt format_mbus[IMX7_CSI_PADS_NUM]; + const struct imx_media_pixfmt *cc[IMX7_CSI_PADS_NUM]; + struct v4l2_fract frame_interval[IMX7_CSI_PADS_NUM]; + + struct v4l2_ctrl_handler ctrl_hdlr; + + void __iomem *regbase; + int irq; + + struct clk *clk_disp_axi; + struct clk *clk_disp_dcic; + struct clk *clk_csi_mclk; + + /* active vb2 buffers to send to video dev sink */ + struct imx_media_buffer *active_vb2_buf[2]; + struct imx_media_dma_buf underrun_buf; + + int buf_num; + u32 frame_sequence; + + bool last_eof; + bool is_init; + bool is_streaming; + bool is_csi2; + + struct completion last_eof_completion; +}; + +#define imx7_csi_reg_read(_csi, _offset) __raw_readl(_csi->regbase + _offset) +#define imx7_csi_reg_write(_csi, _val, _offset) \ + __raw_writel(_val, _csi->regbase + _offset) + +static void imx7_csi_clk_enable(struct imx7_csi *csi) +{ + clk_prepare_enable(csi->clk_disp_axi); + clk_prepare_enable(csi->clk_disp_dcic); + clk_prepare_enable(csi->clk_csi_mclk); +} + +static void imx7_csi_clk_disable(struct imx7_csi *csi) +{ + clk_disable_unprepare(csi->clk_csi_mclk); + clk_disable_unprepare(csi->clk_disp_dcic); + clk_disable_unprepare(csi->clk_disp_axi); +} + +static void imx7_csi_hw_reset(struct imx7_csi *csi) +{ + imx7_csi_reg_write(csi, + imx7_csi_reg_read(csi, CSI_CSICR3) | BIT_FRMCNT_RST, + CSI_CSICR3); + + imx7_csi_reg_write(csi, CSICR1_RESET_VAL, CSI_CSICR1); + imx7_csi_reg_write(csi, CSICR2_RESET_VAL, CSI_CSICR2); + imx7_csi_reg_write(csi, CSICR3_RESET_VAL, CSI_CSICR3); +} + +static unsigned long imx7_csi_irq_clear(struct imx7_csi *csi) +{ + unsigned long isr; + + isr = imx7_csi_reg_read(csi, CSI_CSISR); + imx7_csi_reg_write(csi, isr, CSI_CSISR); + + return isr; +} + +static void imx7_csi_init_interface(struct imx7_csi *csi) +{ + unsigned int val = 0; + unsigned int imag_para; + + val = BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE | BIT_HSYNC_POL | + BIT_FCC | 1 << SHIFT_MCLKDIV | BIT_MCLKEN; + imx7_csi_reg_write(csi, val, CSI_CSICR1); + + imag_para = (800 << 16) | 600; + imx7_csi_reg_write(csi, imag_para, CSI_CSIIMAG_PARA); + + val = BIT_DMA_REFLASH_RFF; + imx7_csi_reg_write(csi, val, CSI_CSICR3); +} + +static void imx7_csi_hw_enable_irq(struct imx7_csi *csi) +{ + unsigned long cr1 = imx7_csi_reg_read(csi, CSI_CSICR1); + + cr1 |= BIT_SOF_INTEN; + cr1 |= BIT_RFF_OR_INT; + + /* still capture needs DMA interrupt */ + cr1 |= BIT_FB1_DMA_DONE_INTEN; + cr1 |= BIT_FB2_DMA_DONE_INTEN; + + cr1 |= BIT_EOF_INT_EN; + + imx7_csi_reg_write(csi, cr1, CSI_CSICR1); +} + +static void imx7_csi_hw_disable_irq(struct imx7_csi *csi) +{ + unsigned long cr1 = imx7_csi_reg_read(csi, CSI_CSICR1); + + cr1 &= ~BIT_SOF_INTEN; + cr1 &= ~BIT_RFF_OR_INT; + cr1 &= ~BIT_FB1_DMA_DONE_INTEN; + cr1 &= ~BIT_FB2_DMA_DONE_INTEN; + cr1 &= ~BIT_EOF_INT_EN; + + imx7_csi_reg_write(csi, cr1, CSI_CSICR1); +} + +static void imx7_csi_hw_enable(struct imx7_csi *csi) +{ + unsigned long cr = imx7_csi_reg_read(csi, CSI_CSICR18); + + cr |= BIT_CSI_HW_ENABLE; + + imx7_csi_reg_write(csi, cr, CSI_CSICR18); +} + +static void imx7_csi_hw_disable(struct imx7_csi *csi) +{ + unsigned long cr = imx7_csi_reg_read(csi, CSI_CSICR18); + + cr &= ~BIT_CSI_HW_ENABLE; + + imx7_csi_reg_write(csi, cr, CSI_CSICR18); +} + +static void imx7_csi_dma_reflash(struct imx7_csi *csi) +{ + unsigned long cr3 = imx7_csi_reg_read(csi, CSI_CSICR18); + + cr3 = imx7_csi_reg_read(csi, CSI_CSICR3); + cr3 |= BIT_DMA_REFLASH_RFF; + imx7_csi_reg_write(csi, cr3, CSI_CSICR3); +} + +static void imx7_csi_rx_fifo_clear(struct imx7_csi *csi) +{ + unsigned long cr1; + + cr1 = imx7_csi_reg_read(csi, CSI_CSICR1); + imx7_csi_reg_write(csi, cr1 & ~BIT_FCC, CSI_CSICR1); + cr1 = imx7_csi_reg_read(csi, CSI_CSICR1); + imx7_csi_reg_write(csi, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1); + + cr1 = imx7_csi_reg_read(csi, CSI_CSICR1); + imx7_csi_reg_write(csi, cr1 | BIT_FCC, CSI_CSICR1); +} + +static void imx7_csi_buf_stride_set(struct imx7_csi *csi, u32 stride) +{ + imx7_csi_reg_write(csi, stride, CSI_CSIFBUF_PARA); +} + +static void imx7_csi_deinterlace_enable(struct imx7_csi *csi, bool enable) +{ + unsigned long cr18 = imx7_csi_reg_read(csi, CSI_CSICR18); + + if (enable) + cr18 |= BIT_DEINTERLACE_EN; + else + cr18 &= ~BIT_DEINTERLACE_EN; + + imx7_csi_reg_write(csi, cr18, CSI_CSICR18); +} + +static void imx7_csi_dmareq_rff_enable(struct imx7_csi *csi) +{ + unsigned long cr3 = imx7_csi_reg_read(csi, CSI_CSICR3); + unsigned long cr2 = imx7_csi_reg_read(csi, CSI_CSICR2); + + /* Burst Type of DMA Transfer from RxFIFO. INCR16 */ + cr2 |= 0xC0000000; + + cr3 |= BIT_DMA_REQ_EN_RFF; + cr3 |= BIT_HRESP_ERR_EN; + cr3 &= ~BIT_RXFF_LEVEL; + cr3 |= 0x2 << 4; + + imx7_csi_reg_write(csi, cr3, CSI_CSICR3); + imx7_csi_reg_write(csi, cr2, CSI_CSICR2); +} + +static void imx7_csi_dmareq_rff_disable(struct imx7_csi *csi) +{ + unsigned long cr3 = imx7_csi_reg_read(csi, CSI_CSICR3); + + cr3 &= ~BIT_DMA_REQ_EN_RFF; + cr3 &= ~BIT_HRESP_ERR_EN; + imx7_csi_reg_write(csi, cr3, CSI_CSICR3); +} + +static void imx7_csi_set_imagpara(struct imx7_csi *csi, int width, int height) +{ + int imag_para; + int rx_count; + + rx_count = (width * height) >> 2; + imx7_csi_reg_write(csi, rx_count, CSI_CSIRXCNT); + + imag_para = (width << 16) | height; + imx7_csi_reg_write(csi, imag_para, CSI_CSIIMAG_PARA); + + /* reflash the embedded DMA controller */ + imx7_csi_dma_reflash(csi); +} + +static void imx7_csi_sw_reset(struct imx7_csi *csi) +{ + imx7_csi_hw_disable(csi); + + imx7_csi_rx_fifo_clear(csi); + + imx7_csi_dma_reflash(csi); + + usleep_range(2000, 3000); + + imx7_csi_irq_clear(csi); + + imx7_csi_hw_enable(csi); +} + +static void imx7_csi_error_recovery(struct imx7_csi *csi) +{ + imx7_csi_hw_disable(csi); + + imx7_csi_rx_fifo_clear(csi); + + imx7_csi_dma_reflash(csi); + + imx7_csi_hw_enable(csi); +} + +static void imx7_csi_init(struct imx7_csi *csi) +{ + if (csi->is_init) + return; + + imx7_csi_clk_enable(csi); + imx7_csi_hw_reset(csi); + imx7_csi_init_interface(csi); + imx7_csi_dmareq_rff_enable(csi); + + csi->is_init = true; +} + +static void imx7_csi_deinit(struct imx7_csi *csi) +{ + if (!csi->is_init) + return; + + imx7_csi_hw_reset(csi); + imx7_csi_init_interface(csi); + imx7_csi_dmareq_rff_disable(csi); + imx7_csi_clk_disable(csi); + + csi->is_init = false; +} + +static int imx7_csi_get_upstream_endpoint(struct imx7_csi *csi, + struct v4l2_fwnode_endpoint *ep, + bool skip_mux) +{ + struct device_node *endpoint, *port; + struct media_entity *src; + struct v4l2_subdev *sd; + struct media_pad *pad; + + if (!csi->src_sd) + return -EPIPE; + + src = &csi->src_sd->entity; + +skip_video_mux: + /* get source pad of entity directly upstream from src */ + pad = imx_media_find_upstream_pad(csi->md, src, 0); + if (IS_ERR(pad)) + return PTR_ERR(pad); + + sd = media_entity_to_v4l2_subdev(pad->entity); + + /* To get bus type we may need to skip video mux */ + if (skip_mux && src->function == MEDIA_ENT_F_VID_MUX) { + src = &sd->entity; + goto skip_video_mux; + } + + /* + * NOTE: this assumes an OF-graph port id is the same as a + * media pad index. + */ + port = of_graph_get_port_by_id(sd->dev->of_node, pad->index); + if (!port) + return -ENODEV; + + endpoint = of_get_next_child(port, NULL); + of_node_put(port); + if (!endpoint) + return -ENODEV; + + v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), ep); + of_node_put(endpoint); + + return 0; +} + +static int imx7_csi_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); + struct imx7_csi *csi = v4l2_get_subdevdata(sd); + struct v4l2_subdev *remote_sd; + int ret = 0; + + dev_dbg(csi->dev, "link setup %s -> %s\n", remote->entity->name, + local->entity->name); + + mutex_lock(&csi->lock); + + if (local->flags & MEDIA_PAD_FL_SINK) { + if (!is_media_entity_v4l2_subdev(remote->entity)) { + ret = -EINVAL; + goto unlock; + } + + remote_sd = media_entity_to_v4l2_subdev(remote->entity); + + if (flags & MEDIA_LNK_FL_ENABLED) { + if (csi->src_sd) { + ret = -EBUSY; + goto unlock; + } + csi->src_sd = remote_sd; + } else { + csi->src_sd = NULL; + } + + goto init; + } + + /* source pad */ + if (flags & MEDIA_LNK_FL_ENABLED) { + if (csi->sink) { + ret = -EBUSY; + goto unlock; + } + csi->sink = remote->entity; + } else { + v4l2_ctrl_handler_free(&csi->ctrl_hdlr); + v4l2_ctrl_handler_init(&csi->ctrl_hdlr, 0); + csi->sink = NULL; + } + +init: + if (csi->sink || csi->src_sd) + imx7_csi_init(csi); + else + imx7_csi_deinit(csi); + +unlock: + mutex_unlock(&csi->lock); + + return ret; +} + +static int imx7_csi_pad_link_validate(struct v4l2_subdev *sd, + struct media_link *link, + struct v4l2_subdev_format *source_fmt, + struct v4l2_subdev_format *sink_fmt) +{ + struct imx7_csi *csi = v4l2_get_subdevdata(sd); + struct v4l2_fwnode_endpoint upstream_ep; + int ret; + + ret = v4l2_subdev_link_validate_default(sd, link, source_fmt, sink_fmt); + if (ret) + return ret; + + ret = imx7_csi_get_upstream_endpoint(csi, &upstream_ep, true); + if (ret) { + v4l2_err(&csi->sd, "failed to find upstream endpoint\n"); + return ret; + } + + mutex_lock(&csi->lock); + + csi->upstream_ep = upstream_ep; + csi->is_csi2 = (upstream_ep.bus_type == V4L2_MBUS_CSI2); + + mutex_unlock(&csi->lock); + + return 0; +} + +static void imx7_csi_update_buf(struct imx7_csi *csi, dma_addr_t phys, + int buf_num) +{ + if (buf_num == 1) + imx7_csi_reg_write(csi, phys, CSI_CSIDMASA_FB2); + else + imx7_csi_reg_write(csi, phys, CSI_CSIDMASA_FB1); +} + +static void imx7_csi_setup_vb2_buf(struct imx7_csi *csi) +{ + struct imx_media_video_dev *vdev = csi->vdev; + struct imx_media_buffer *buf; + struct vb2_buffer *vb2_buf; + dma_addr_t phys[2]; + int i; + + for (i = 0; i < 2; i++) { + buf = imx_media_capture_device_next_buf(vdev); + if (buf) { + csi->active_vb2_buf[i] = buf; + vb2_buf = &buf->vbuf.vb2_buf; + phys[i] = vb2_dma_contig_plane_dma_addr(vb2_buf, 0); + } else { + csi->active_vb2_buf[i] = NULL; + phys[i] = csi->underrun_buf.phys; + } + + imx7_csi_update_buf(csi, phys[i], i); + } +} + +static void imx7_csi_dma_unsetup_vb2_buf(struct imx7_csi *csi, + enum vb2_buffer_state return_status) +{ + struct imx_media_buffer *buf; + int i; + + /* return any remaining active frames with return_status */ + for (i = 0; i < 2; i++) { + buf = csi->active_vb2_buf[i]; + if (buf) { + struct vb2_buffer *vb = &buf->vbuf.vb2_buf; + + vb->timestamp = ktime_get_ns(); + vb2_buffer_done(vb, return_status); + } + } +} + +static void imx7_csi_vb2_buf_done(struct imx7_csi *csi) +{ + struct imx_media_video_dev *vdev = csi->vdev; + struct imx_media_buffer *done, *next; + struct vb2_buffer *vb; + dma_addr_t phys; + + done = csi->active_vb2_buf[csi->buf_num]; + if (done) { + done->vbuf.field = vdev->fmt.fmt.pix.field; + done->vbuf.sequence = csi->frame_sequence; + vb = &done->vbuf.vb2_buf; + vb->timestamp = ktime_get_ns(); + vb2_buffer_done(vb, VB2_BUF_STATE_DONE); + } + csi->frame_sequence++; + + /* get next queued buffer */ + next = imx_media_capture_device_next_buf(vdev); + if (next) { + phys = vb2_dma_contig_plane_dma_addr(&next->vbuf.vb2_buf, 0); + csi->active_vb2_buf[csi->buf_num] = next; + } else { + phys = csi->underrun_buf.phys; + csi->active_vb2_buf[csi->buf_num] = NULL; + } + + imx7_csi_update_buf(csi, phys, csi->buf_num); +} + +static irqreturn_t imx7_csi_irq_handler(int irq, void *data) +{ + struct imx7_csi *csi = data; + unsigned long status; + + spin_lock(&csi->irqlock); + + status = imx7_csi_irq_clear(csi); + + if (status & BIT_RFF_OR_INT) { + dev_warn(csi->dev, "Rx fifo overflow\n"); + imx7_csi_error_recovery(csi); + } + + if (status & BIT_HRESP_ERR_INT) { + dev_warn(csi->dev, "Hresponse error detected\n"); + imx7_csi_error_recovery(csi); + } + + if (status & BIT_ADDR_CH_ERR_INT) { + imx7_csi_hw_disable(csi); + + imx7_csi_dma_reflash(csi); + + imx7_csi_hw_enable(csi); + } + + if ((status & BIT_DMA_TSF_DONE_FB1) && + (status & BIT_DMA_TSF_DONE_FB2)) { + /* + * For both FB1 and FB2 interrupter bits set case, + * CSI DMA is work in one of FB1 and FB2 buffer, + * but software can not know the state. + * Skip it to avoid base address updated + * when csi work in field0 and field1 will write to + * new base address. + */ + } else if (status & BIT_DMA_TSF_DONE_FB1) { + csi->buf_num = 0; + } else if (status & BIT_DMA_TSF_DONE_FB2) { + csi->buf_num = 1; + } + + if ((status & BIT_DMA_TSF_DONE_FB1) || + (status & BIT_DMA_TSF_DONE_FB2)) { + imx7_csi_vb2_buf_done(csi); + + if (csi->last_eof) { + complete(&csi->last_eof_completion); + csi->last_eof = false; + } + } + + + spin_unlock(&csi->irqlock); + + return IRQ_HANDLED; +} + +static int imx7_csi_dma_start(struct imx7_csi *csi) +{ + struct imx_media_video_dev *vdev = csi->vdev; + struct v4l2_pix_format *out_pix = &vdev->fmt.fmt.pix; + int ret; + + ret = imx_media_alloc_dma_buf(csi->md, &csi->underrun_buf, + out_pix->sizeimage); + if (ret < 0) { + v4l2_warn(&csi->sd, "consider increasing the CMA area\n"); + return ret; + } + + csi->frame_sequence = 0; + csi->last_eof = false; + init_completion(&csi->last_eof_completion); + + imx7_csi_setup_vb2_buf(csi); + + return 0; +} + +static void imx7_csi_dma_stop(struct imx7_csi *csi) +{ + unsigned long flags; + int ret; + + /* mark next EOF interrupt as the last before stream off */ + spin_lock_irqsave(&csi->irqlock, flags); + csi->last_eof = true; + spin_unlock_irqrestore(&csi->irqlock, flags); + + /* + * and then wait for interrupt handler to mark completion. + */ + ret = wait_for_completion_timeout(&csi->last_eof_completion, + msecs_to_jiffies(IMX_MEDIA_EOF_TIMEOUT)); + if (ret == 0) + v4l2_warn(&csi->sd, "wait last EOF timeout\n"); + + imx7_csi_hw_disable_irq(csi); + + imx7_csi_dma_unsetup_vb2_buf(csi, VB2_BUF_STATE_ERROR); + + imx_media_free_dma_buf(csi->md, &csi->underrun_buf); +} + +static int imx7_csi_configure(struct imx7_csi *csi) +{ + struct imx_media_video_dev *vdev = csi->vdev; + struct v4l2_pix_format *out_pix = &vdev->fmt.fmt.pix; + __u32 in_code = csi->format_mbus[IMX7_CSI_PAD_SINK].code; + u32 cr1, cr18; + + if (out_pix->field == V4L2_FIELD_INTERLACED) { + imx7_csi_deinterlace_enable(csi, true); + imx7_csi_buf_stride_set(csi, out_pix->width); + } else { + imx7_csi_deinterlace_enable(csi, false); + imx7_csi_buf_stride_set(csi, 0); + } + + imx7_csi_set_imagpara(csi, out_pix->width, out_pix->height); + + if (!csi->is_csi2) + return 0; + + cr1 = imx7_csi_reg_read(csi, CSI_CSICR1); + cr1 &= ~BIT_GCLK_MODE; + + cr18 = imx7_csi_reg_read(csi, CSI_CSICR18); + cr18 &= BIT_MIPI_DATA_FORMAT_MASK; + cr18 |= BIT_DATA_FROM_MIPI; + + switch (out_pix->pixelformat) { + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_YUYV: + cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B; + break; + case V4L2_PIX_FMT_SBGGR8: + cr18 |= BIT_MIPI_DATA_FORMAT_RAW8; + break; + case V4L2_PIX_FMT_SBGGR16: + if (in_code == MEDIA_BUS_FMT_SBGGR10_1X10) + cr18 |= BIT_MIPI_DATA_FORMAT_RAW10; + else if (in_code == MEDIA_BUS_FMT_SBGGR12_1X12) + cr18 |= BIT_MIPI_DATA_FORMAT_RAW12; + else if (in_code == MEDIA_BUS_FMT_SBGGR14_1X14) + cr18 |= BIT_MIPI_DATA_FORMAT_RAW14; + cr1 |= BIT_PIXEL_BIT; + break; + default: + return -EINVAL; + } + + imx7_csi_reg_write(csi, cr1, CSI_CSICR1); + imx7_csi_reg_write(csi, cr18, CSI_CSICR18); + + return 0; +} + +static int imx7_csi_enable(struct imx7_csi *csi) +{ + imx7_csi_sw_reset(csi); + + if (csi->is_csi2) { + imx7_csi_dmareq_rff_enable(csi); + imx7_csi_hw_enable_irq(csi); + imx7_csi_hw_enable(csi); + return 0; + } + + return 0; +} + +static void imx7_csi_disable(struct imx7_csi *csi) +{ + imx7_csi_dmareq_rff_disable(csi); + + imx7_csi_hw_disable_irq(csi); + + imx7_csi_buf_stride_set(csi, 0); + + imx7_csi_hw_disable(csi); +} + +static int imx7_csi_streaming_start(struct imx7_csi *csi) +{ + int ret; + + ret = imx7_csi_dma_start(csi); + if (ret < 0) + return ret; + + ret = imx7_csi_configure(csi); + if (ret < 0) + goto dma_stop; + + imx7_csi_enable(csi); + + return 0; + +dma_stop: + imx7_csi_dma_stop(csi); + + return ret; +} + +static int imx7_csi_streaming_stop(struct imx7_csi *csi) +{ + imx7_csi_dma_stop(csi); + + imx7_csi_disable(csi); + + return 0; +} + +static int imx7_csi_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct imx7_csi *csi = v4l2_get_subdevdata(sd); + int ret = 0; + + mutex_lock(&csi->lock); + + if (!csi->src_sd || !csi->sink) { + ret = -EPIPE; + goto out_unlock; + } + + if (csi->is_streaming == !!enable) + goto out_unlock; + + if (enable) { + ret = v4l2_subdev_call(csi->src_sd, video, s_stream, 1); + if (ret < 0) + goto out_unlock; + + ret = imx7_csi_streaming_start(csi); + if (ret < 0) { + v4l2_subdev_call(csi->src_sd, video, s_stream, 0); + goto out_unlock; + } + } else { + imx7_csi_streaming_stop(csi); + + v4l2_subdev_call(csi->src_sd, video, s_stream, 0); + } + + csi->is_streaming = !!enable; + +out_unlock: + mutex_unlock(&csi->lock); + + return ret; +} + +static struct v4l2_mbus_framefmt *imx7_csi_get_format(struct imx7_csi *csi, + struct v4l2_subdev_pad_config *cfg, + unsigned int pad, + enum v4l2_subdev_format_whence which) +{ + if (which == V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_get_try_format(&csi->sd, cfg, pad); + + return &csi->format_mbus[pad]; +} + +static int imx7_csi_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct imx7_csi *csi = v4l2_get_subdevdata(sd); + const struct imx_media_pixfmt *in_cc; + struct v4l2_mbus_framefmt *in_fmt; + int ret = 0; + + mutex_lock(&csi->lock); + + in_fmt = imx7_csi_get_format(csi, cfg, IMX7_CSI_PAD_SINK, code->which); + + in_cc = imx_media_find_mbus_format(in_fmt->code, CS_SEL_ANY, true); + + switch (code->pad) { + case IMX7_CSI_PAD_SINK: + ret = imx_media_enum_mbus_format(&code->code, code->index, + CS_SEL_ANY, true); + break; + case IMX7_CSI_PAD_SRC: + if (code->index != 0) { + ret = -EINVAL; + goto out_unlock; + } + + code->code = in_fmt->code; + break; + default: + ret = -EINVAL; + } + +out_unlock: + mutex_unlock(&csi->lock); + + return ret; +} + +static int imx7_csi_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *sdformat) +{ + struct imx7_csi *csi = v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *fmt; + int ret = 0; + + if (sdformat->pad >= IMX7_CSI_PADS_NUM) + return -EINVAL; + + mutex_lock(&csi->lock); + + fmt = imx7_csi_get_format(csi, cfg, sdformat->pad, sdformat->which); + if (!fmt) { + ret = -EINVAL; + goto out_unlock; + } + + sdformat->format = *fmt; + +out_unlock: + mutex_unlock(&csi->lock); + + return ret; +} + +static void imx7_csi_try_fmt(struct imx7_csi *csi, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *sdformat, + const struct imx_media_pixfmt **cc) +{ + const struct imx_media_pixfmt *in_cc; + struct v4l2_mbus_framefmt *in_fmt; + u32 code; + + in_fmt = imx7_csi_get_format(csi, cfg, IMX7_CSI_PAD_SINK, + sdformat->which); + if (!in_fmt) + return; + + switch (sdformat->pad) { + case IMX7_CSI_PAD_SRC: + in_cc = imx_media_find_mbus_format(in_fmt->code, CS_SEL_ANY, + true); + + sdformat->format.width = in_fmt->width; + sdformat->format.height = in_fmt->height; + sdformat->format.code = in_fmt->code; + *cc = in_cc; + + sdformat->format.colorspace = in_fmt->colorspace; + sdformat->format.xfer_func = in_fmt->xfer_func; + sdformat->format.quantization = in_fmt->quantization; + sdformat->format.ycbcr_enc = in_fmt->ycbcr_enc; + break; + case IMX7_CSI_PAD_SINK: + *cc = imx_media_find_mbus_format(sdformat->format.code, + CS_SEL_ANY, true); + if (!*cc) { + imx_media_enum_mbus_format(&code, 0, CS_SEL_ANY, false); + *cc = imx_media_find_mbus_format(code, CS_SEL_ANY, + false); + sdformat->format.code = (*cc)->codes[0]; + } + + imx_media_fill_default_mbus_fields(&sdformat->format, in_fmt, + false); + break; + default: + break; + } +} + +static int imx7_csi_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *sdformat) +{ + struct imx7_csi *csi = v4l2_get_subdevdata(sd); + struct imx_media_video_dev *vdev = csi->vdev; + const struct imx_media_pixfmt *outcc; + struct v4l2_mbus_framefmt *outfmt; + struct v4l2_pix_format vdev_fmt; + const struct imx_media_pixfmt *cc; + struct v4l2_mbus_framefmt *fmt; + struct v4l2_subdev_format format; + int ret = 0; + + if (sdformat->pad >= IMX7_CSI_PADS_NUM) + return -EINVAL; + + mutex_lock(&csi->lock); + + if (csi->is_streaming) { + ret = -EBUSY; + goto out_unlock; + } + + imx7_csi_try_fmt(csi, cfg, sdformat, &cc); + + fmt = imx7_csi_get_format(csi, cfg, sdformat->pad, sdformat->which); + if (!fmt) { + ret = -EINVAL; + goto out_unlock; + } + + *fmt = sdformat->format; + + if (sdformat->pad == IMX7_CSI_PAD_SINK) { + /* propagate format to source pads */ + format.pad = IMX7_CSI_PAD_SRC; + format.which = sdformat->which; + format.format = sdformat->format; + imx7_csi_try_fmt(csi, cfg, &format, &outcc); + + outfmt = imx7_csi_get_format(csi, cfg, IMX7_CSI_PAD_SRC, + sdformat->which); + *outfmt = format.format; + + if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE) + csi->cc[IMX7_CSI_PAD_SRC] = outcc; + } + + if (sdformat->which == V4L2_SUBDEV_FORMAT_TRY) + goto out_unlock; + + csi->cc[sdformat->pad] = cc; + + /* propagate output pad format to capture device */ + imx_media_mbus_fmt_to_pix_fmt(&vdev_fmt, + &csi->format_mbus[IMX7_CSI_PAD_SRC], + csi->cc[IMX7_CSI_PAD_SRC]); + mutex_unlock(&csi->lock); + imx_media_capture_device_set_format(vdev, &vdev_fmt); + + return 0; + +out_unlock: + mutex_unlock(&csi->lock); + + return ret; +} + +static int imx7_csi_registered(struct v4l2_subdev *sd) +{ + struct imx7_csi *csi = v4l2_get_subdevdata(sd); + int ret; + int i; + + csi->md = dev_get_drvdata(sd->v4l2_dev->dev); + + for (i = 0; i < IMX7_CSI_PADS_NUM; i++) { + csi->pad[i].flags = (i == IMX7_CSI_PAD_SINK) ? + MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE; + + /* set a default mbus format */ + ret = imx_media_init_mbus_fmt(&csi->format_mbus[i], + 800, 600, 0, V4L2_FIELD_NONE, + &csi->cc[i]); + if (ret < 0) + return ret; + + /* init default frame interval */ + csi->frame_interval[i].numerator = 1; + csi->frame_interval[i].denominator = 30; + } + + ret = media_entity_pads_init(&sd->entity, IMX7_CSI_PADS_NUM, csi->pad); + if (ret < 0) + return ret; + + ret = imx_media_capture_device_register(csi->vdev); + if (ret < 0) + return ret; + + ret = imx_media_add_video_device(csi->md, csi->vdev); + if (ret < 0) { + imx_media_capture_device_unregister(csi->vdev); + return ret; + } + + return 0; +} + +static void imx7_csi_unregistered(struct v4l2_subdev *sd) +{ + struct imx7_csi *csi = v4l2_get_subdevdata(sd); + + imx_media_capture_device_unregister(csi->vdev); +} + +static int imx7_csi_init_cfg(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg) +{ + struct imx7_csi *csi = v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *mf; + int ret; + int i; + + for (i = 0; i < IMX7_CSI_PADS_NUM; i++) { + mf = v4l2_subdev_get_try_format(sd, cfg, i); + + ret = imx_media_init_mbus_fmt(mf, 800, 600, 0, V4L2_FIELD_NONE, + &csi->cc[i]); + if (ret < 0) + return ret; + } + + return 0; +} + +static const struct media_entity_operations imx7_csi_entity_ops = { + .link_setup = imx7_csi_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +static const struct v4l2_subdev_video_ops imx7_csi_video_ops = { + .s_stream = imx7_csi_s_stream, +}; + +static const struct v4l2_subdev_pad_ops imx7_csi_pad_ops = { + .init_cfg = imx7_csi_init_cfg, + .enum_mbus_code = imx7_csi_enum_mbus_code, + .get_fmt = imx7_csi_get_fmt, + .set_fmt = imx7_csi_set_fmt, + .link_validate = imx7_csi_pad_link_validate, +}; + +static const struct v4l2_subdev_ops imx7_csi_subdev_ops = { + .video = &imx7_csi_video_ops, + .pad = &imx7_csi_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops imx7_csi_internal_ops = { + .registered = imx7_csi_registered, + .unregistered = imx7_csi_unregistered, +}; + +static int imx7_csi_parse_endpoint(struct device *dev, + struct v4l2_fwnode_endpoint *vep, + struct v4l2_async_subdev *asd) +{ + return fwnode_device_is_available(asd->match.fwnode) ? 0 : -EINVAL; +} + +static int imx7_csi_parse_dt(struct imx7_csi *csi) +{ + struct device *dev = csi->dev; + + csi->clk_disp_axi = devm_clk_get(dev, "axi"); + if (IS_ERR(csi->clk_disp_axi)) { + dev_err(dev, "Could not get csi axi clock\n"); + return -ENODEV; + } + + csi->clk_disp_dcic = devm_clk_get(dev, "dcic"); + if (IS_ERR(csi->clk_disp_dcic)) { + dev_err(dev, "Could not get disp dcic clock\n"); + return -ENODEV; + } + + csi->clk_csi_mclk = devm_clk_get(dev, "mclk"); + if (IS_ERR(csi->clk_csi_mclk)) { + dev_err(dev, "Could not get csi mclk clock\n"); + return -ENODEV; + } + + return 0; +} + +static int imx7_csi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct imx7_csi *csi; + struct resource *res; + int ret; + + csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL); + if (!csi) + return -ENOMEM; + + platform_set_drvdata(pdev, &csi->sd); + csi->dev = dev; + + ret = imx7_csi_parse_dt(csi); + if (ret < 0) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + csi->irq = platform_get_irq(pdev, 0); + if (!res || csi->irq < 0) { + dev_err(dev, "Missing platform resources data\n"); + return -ENODEV; + } + + csi->regbase = devm_ioremap_resource(dev, res); + if (IS_ERR(csi->regbase)) { + dev_err(dev, "Failed platform resources map\n"); + return -ENODEV; + } + + spin_lock_init(&csi->irqlock); + mutex_init(&csi->lock); + + /* install interrupt handler */ + ret = devm_request_irq(dev, csi->irq, imx7_csi_irq_handler, 0, "csi", + (void *)csi); + if (ret < 0) { + dev_err(dev, "Request CSI IRQ failed.\n"); + return -ENODEV; + } + + /* add media device */ + csi->imxmd = imx_media_dev_init(dev); + if (IS_ERR(csi->imxmd)) + return PTR_ERR(csi->imxmd); + + ret = imx_media_of_add_csi(csi->imxmd, node); + if (ret < 0) + goto media_cleanup; + + ret = imx_media_dev_notifier_register(csi->imxmd); + if (ret < 0) + goto media_cleanup; + + v4l2_subdev_init(&csi->sd, &imx7_csi_subdev_ops); + v4l2_set_subdevdata(&csi->sd, csi); + csi->sd.internal_ops = &imx7_csi_internal_ops; + csi->sd.entity.ops = &imx7_csi_entity_ops; + csi->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; + csi->sd.dev = &pdev->dev; + csi->sd.owner = THIS_MODULE; + csi->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; + csi->sd.grp_id = IMX_MEDIA_GRP_ID_CSI; + snprintf(csi->sd.name, sizeof(csi->sd.name), "csi"); + + csi->vdev = imx_media_capture_device_init(&csi->sd, IMX7_CSI_PAD_SRC); + if (IS_ERR(csi->vdev)) + return PTR_ERR(csi->vdev); + + v4l2_ctrl_handler_init(&csi->ctrl_hdlr, 0); + csi->sd.ctrl_handler = &csi->ctrl_hdlr; + + ret = v4l2_async_register_fwnode_subdev(&csi->sd, + sizeof(struct v4l2_async_subdev), + NULL, 0, imx7_csi_parse_endpoint); + if (ret) + goto free; + + return 0; + +free: + v4l2_ctrl_handler_free(&csi->ctrl_hdlr); + mutex_destroy(&csi->lock); + imx_media_capture_device_remove(csi->vdev); + +media_cleanup: + imx_media_dev_cleanup(csi->imxmd); + + return ret; +} + +static int imx7_csi_remove(struct platform_device *pdev) +{ + struct v4l2_subdev *sd = platform_get_drvdata(pdev); + struct imx7_csi *csi = v4l2_get_subdevdata(sd); + + v4l2_ctrl_handler_free(&csi->ctrl_hdlr); + mutex_destroy(&csi->lock); + imx_media_capture_device_remove(csi->vdev); + imx_media_dev_notifier_unregister(csi->imxmd); + imx_media_dev_cleanup(csi->imxmd); + media_entity_cleanup(&sd->entity); + v4l2_async_unregister_subdev(sd); + + return 0; +} + +static const struct of_device_id imx7_csi_of_match[] = { + { .compatible = "fsl,imx7-csi" }, + { }, +}; +MODULE_DEVICE_TABLE(of, imx7_csi_of_match); + +static struct platform_driver imx7_csi_driver = { + .probe = imx7_csi_probe, + .remove = imx7_csi_remove, + .driver = { + .of_match_table = imx7_csi_of_match, + .name = "imx7-csi", + }, +}; +module_platform_driver(imx7_csi_driver); + +MODULE_DESCRIPTION("i.MX7 CSI subdev driver"); +MODULE_AUTHOR("Rui Miguel Silva "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:imx7-csi"); From patchwork Fri Aug 10 14:20:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 143934 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp15913ljj; Fri, 10 Aug 2018 07:21:48 -0700 (PDT) X-Google-Smtp-Source: AA+uWPy1TgMyPxMtoVlP0T1ah7CbWM3Ld3GgL0joXYr6Ya4ZoEWFh14wJbfhAuLsHJN/CzHs0j8a X-Received: by 2002:a17:902:d906:: with SMTP id c6-v6mr6320067plz.65.1533910908406; Fri, 10 Aug 2018 07:21:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533910908; cv=none; d=google.com; s=arc-20160816; b=UYWmFnrYCyTzzWt3A8Je+Vsr5viZ22VmOZRSm5LigQJZhIYuxroI5qQv6Frg8uLpmy BQhZAZpJDplnpFTt5btpbOllfH8gs3eI+BDxpjOCZmCLjtBlL/HKvvD7CzKQoZRlDprS VDklAGGkpO3W6uBG+Rn/r4bkaNo/ezQXlmxxZIgsoTDL2aq+B31ixI+9uD3frxI9i1Wh 4HQngwW432EKMRarYPQyPE3OulhzhB9q0NZjOWFqd3kIuscflGbJ277ww4SbOjJkNt8u PrP1dhEesXlvBwIzy0rlrvfbsv2VdpAqqQ8/Z0QqkSy0tyqtvB1clH6Lm6RNBm1bO9Zf s/yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=IGWVcBV2+cy8yLFTjp/FPwItzRNGc2ueXRY+hvUH13o=; b=mlSipKH8jY5dc4+YOcqtmrOCv/ovu+aP9PaOasc/iBUWkEkMdlrG2nFktPog6nauJl ocKzmiBwE1qAg3z/+x8zULuf7MLKCpMwNOgGbGIXDQAjGlCB8Y+RgBsjYuXr4l8G4o+X EcfacHlRuIyH10OS5upm3SgtHCJJ3rBvL5ZimotJRntNINQ1evWxxYTfiUNJmVHAisnm GEtel7h2sab02MjtsnB8Dt43UwSRIO3yC0+VNu3fQsHeHOvAXVgG/1kPknbSpZjCgDRg wWdmAu8xn/nGBTIB/1cdynMggz21bfQuAXqbeQuS4SQ4uZSKuLtqbCLjExPheW5YM6ji dDbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bx0E7cn1; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 91-v6si7981107ply.405.2018.08.10.07.21.48; Fri, 10 Aug 2018 07:21:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bx0E7cn1; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728205AbeHJQvx (ORCPT + 4 others); Fri, 10 Aug 2018 12:51:53 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:55013 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728064AbeHJQvw (ORCPT ); Fri, 10 Aug 2018 12:51:52 -0400 Received: by mail-wm0-f66.google.com with SMTP id c14-v6so2096577wmb.4 for ; Fri, 10 Aug 2018 07:21:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IGWVcBV2+cy8yLFTjp/FPwItzRNGc2ueXRY+hvUH13o=; b=bx0E7cn1im4c31YWJMATdv5qf+O27k8iVLFxcNPti/fHvfxNTsYNVcOkzj6Dv0JUU1 PI1662kdSE5VQ82sapBkMJNsBDun3KiV1k62njLuLEOYaFzM6E9mb9QAz4N2k8rwv2Zo NHnwFSi/5XC8qD1k5KwW8PWqPDJ6Z8+4776ag= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IGWVcBV2+cy8yLFTjp/FPwItzRNGc2ueXRY+hvUH13o=; b=pXAB/zao21wCx2JfCLiFHv1FnuGB+i8745+YH7pVyMV3aG3lHj/qAvpm1VFj1VuPPA fAPkefQY6YzwSh7q8D8T9XtTvLvNPbvhw05UkrYBeGgCNBhndOGjLiihZElGmP3SMcil Y1MNqtZ2iSFjjvFwpOiOcBhNRA/ucC7PUj9grrj2aQX/crD7p+2a5zH7BgZoXb0bJHFP RFKPwfY2komUQwQuAUDngA7D0BPysxL3uav6Cat4I/jjvwAeoEf32KEOvhtrnL5vcI1i zly//n4eQ93+88GNmzOr4Z69F7nPG/Z+oNrPrMUz8A7sdHoiBNr8iNNaBahfKYPxmmfo eH2w== X-Gm-Message-State: AOUpUlFaGfAfXjvaEJlv+BkKhBjS5UUKRiONg3uVlNyxjD1IWENvK5+7 mdbf69ZGdCBhGelPR/hM+r1RGA== X-Received: by 2002:a1c:e904:: with SMTP id q4-v6mr1687411wmc.154.1533910905338; Fri, 10 Aug 2018 07:21:45 -0700 (PDT) Received: from arch-late.local (a109-49-46-234.cpe.netcabo.pt. [109.49.46.234]) by smtp.gmail.com with ESMTPSA id b13-v6sm13077578wrn.17.2018.08.10.07.21.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Aug 2018 07:21:44 -0700 (PDT) From: Rui Miguel Silva To: mchehab@kernel.org, sakari.ailus@linux.intel.com, Philipp Zabel , Rob Herring Cc: linux-media@vger.kernel.org, devel@driverdev.osuosl.org, Fabio Estevam , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ryan Harkin , Rui Miguel Silva Subject: [PATCH v7 06/12] ARM: dts: imx7s: add mipi phy power domain Date: Fri, 10 Aug 2018 15:20:39 +0100 Message-Id: <20180810142045.27657-7-rui.silva@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180810142045.27657-1-rui.silva@linaro.org> References: <20180810142045.27657-1-rui.silva@linaro.org> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add power domain index 0 related with mipi-phy to imx7s. While at it rename pcie power-domain node to remove pgc prefix. Signed-off-by: Rui Miguel Silva --- arch/arm/boot/dts/imx7s.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.18.0 diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 9ced589bfa96..df4a29365468 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -610,7 +610,13 @@ #address-cells = <1>; #size-cells = <0>; - pgc_pcie_phy: pgc-power-domain@1 { + pgc_mipi_phy: power-domain@0 { + #power-domain-cells = <0>; + reg = <0>; + power-supply = <®_1p0d>; + }; + + pgc_pcie_phy: power-domain@1 { #power-domain-cells = <0>; reg = <1>; power-supply = <®_1p0d>; From patchwork Fri Aug 10 14:20:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 143935 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp15948ljj; Fri, 10 Aug 2018 07:21:50 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyybBozJHgyJtlAN6BQPKnc1mgvPsv2GeagjTexFjKZUB3sHHnK2R5yi6fu15bLdWo4JTaL X-Received: by 2002:a17:902:76c7:: with SMTP id j7-v6mr6351438plt.275.1533910910386; Fri, 10 Aug 2018 07:21:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533910910; cv=none; d=google.com; s=arc-20160816; b=bMlVoQgS9B4myFgMC82ngyqopCK4Yyb8rXdwOuzs+emlwsscbbbxcUdW+1+9NuOG9h RFNhGXgnD/PtKlrMxX+6y2z67DhKA0Jb5UsgtTPu2a0kYmXrQ0DF0BZ6teuarOvN3a4c 37tq0dFnZ4Njuemy6Hui/JYi9bqGyEUJ+bb4/HaYtG2r5fTScQ3/l/y2LjTAOUMUVGcj AZggiu+g6mzKer9UTqqYG3GM0uAH49CDLabj2k01xUPrzpbcWdK3wmH3HAd2oTa1ZMt9 m0fOUoZQKGTSL2hJZYu8BsjfjeCKr7cUvl6oVpSey56d54kJOXzOC2jRE4g4QPCjdsea HPeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=n9zzKDPmKdR5LHHLq7O0JVaGG4NvFBHS7OWGbVGVKR0=; b=tAIAmUEDWngktiTyq6SxdRghzssOzs79PWfV5AMdEreMQigVMDDNDYUt14hFeh3b5B 7FF2Q7gGid3CJ5PzprwDdH+1w0LzR6dNLdMn5JffM4kt6jYJ7vxmrLt3BaYn84YdSoOs sdcAIYCX2Xdm4Po9xiHU12eBJ8sM1+qEAkG2FOUScIJ8vtCi386JHW4Sw8pVrFVT2rDR acl3Iay7ns3svhva0iW9+3KziIntMB/pMYQQYMnxNeVatkMMNN089ZzuXYXuGJCGzmW/ vMJ84sVDgbB5kNz8Bc8Pb3RhqDv2hGnDxdsK8c4cwJetbW2q+U7cz58ZLSj0ojvB71Yk d/+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kcO5P2c1; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 91-v6si7981107ply.405.2018.08.10.07.21.50; Fri, 10 Aug 2018 07:21:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kcO5P2c1; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728211AbeHJQv4 (ORCPT + 4 others); Fri, 10 Aug 2018 12:51:56 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:52019 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728188AbeHJQvz (ORCPT ); Fri, 10 Aug 2018 12:51:55 -0400 Received: by mail-wm0-f66.google.com with SMTP id y2-v6so2108974wma.1 for ; Fri, 10 Aug 2018 07:21:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n9zzKDPmKdR5LHHLq7O0JVaGG4NvFBHS7OWGbVGVKR0=; b=kcO5P2c1oaHFyIeQSlMx58Rm7e5yXsTU6GC8XQX2bQ9Rq0FmJjzwhbFA4KpVJwOCaa xE8040TtTiWvQy81fu1terAnhJko2pBH69txLNWRBFWjVQnevLWNhpjEDyLeU697QPcF ozAd2J4oWn/uGelU/tApYsi1GsF/VzPhbJwnA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n9zzKDPmKdR5LHHLq7O0JVaGG4NvFBHS7OWGbVGVKR0=; b=ewWjQo2d32yU+qS6CB994dJlELooVz5I68q+TCmvXj+6fKgGpRzaSkJjreCqWaGhzs IwpGLEhJO872lKhv0RqFcF9x+ec0WZQpx9jQch9WEpWvvaAWor32Sblb1o8b9onqzsdk lSzZrelG9iyxXtfrVFC8QyKqfCzOcMhyAq7jnNQndMGKb2iG91zw00ihimp79gaPAtOH HXUY3ujKS72u1vuF+fvQgiSGnahRNPjCIiyJlM/fBit2HhK2AlQhk5kHbGP4vwz1Cltn rSymg+1M49xDlNlp6ycnHmsNyCbpKDMmUhi92OBdD6PnJCLD082HVeU5jHwMVcemKNaM W3Ig== X-Gm-Message-State: AOUpUlHwwIZie8g7qYAbxX+iYcdBgcB56ntvqu/Ks41QjtCZcGGrtVmb E91JFIg7JvNkJRtYeGt/itky5g== X-Received: by 2002:a1c:a691:: with SMTP id p139-v6mr1650261wme.42.1533910907696; Fri, 10 Aug 2018 07:21:47 -0700 (PDT) Received: from arch-late.local (a109-49-46-234.cpe.netcabo.pt. [109.49.46.234]) by smtp.gmail.com with ESMTPSA id b13-v6sm13077578wrn.17.2018.08.10.07.21.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Aug 2018 07:21:46 -0700 (PDT) From: Rui Miguel Silva To: mchehab@kernel.org, sakari.ailus@linux.intel.com, Philipp Zabel , Rob Herring Cc: linux-media@vger.kernel.org, devel@driverdev.osuosl.org, Fabio Estevam , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ryan Harkin , Rui Miguel Silva Subject: [PATCH v7 07/12] ARM: dts: imx7s: add multiplexer controls Date: Fri, 10 Aug 2018 15:20:40 +0100 Message-Id: <20180810142045.27657-8-rui.silva@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180810142045.27657-1-rui.silva@linaro.org> References: <20180810142045.27657-1-rui.silva@linaro.org> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The IOMUXC General Purpose Register has bitfield to control video bus multiplexer to control the CSI input between the MIPI-CSI2 and parallel interface. Add that register and mask. Signed-off-by: Rui Miguel Silva Reviewed-by: Philipp Zabel --- arch/arm/boot/dts/imx7s.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.18.0 diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index df4a29365468..f6c7afa51dc1 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -493,8 +493,14 @@ gpr: iomuxc-gpr@30340000 { compatible = "fsl,imx7d-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; + "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; reg = <0x30340000 0x10000>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <0>; + mux-reg-masks = <0x14 0x00000010>; + }; }; ocotp: ocotp-ctrl@30350000 { From patchwork Fri Aug 10 14:20:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 143937 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp16042ljj; Fri, 10 Aug 2018 07:21:54 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxEi1/Jd+6NegqisaCaO9At3zBsH6YSUI7EtajtmktIdLeRiijf+G1cuanoyJ9TweOYfD0M X-Received: by 2002:a63:bf08:: with SMTP id v8-v6mr6549736pgf.3.1533910914636; Fri, 10 Aug 2018 07:21:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533910914; cv=none; d=google.com; s=arc-20160816; b=0EYx06ynJh1JTX8957JuHBD5EjtaIitDPO4OsoF9C4IgVN8PRvfphHFExTCB48cxuA PNxi+39pDlOhj5RUSklkrM62NI3hdBZyNj1+W+c1XtHQDZLvFfxiOprQG7gu3ygH7pDg yLgQv/atRxcmpUttK7xCTLOi9VaLgj4yn/Ruh2vbViA5rO1yMQu2gvEMauWNpmQNZ9Yx cqMELTasb02uaQsVBDWzdQwDqeZWPyAR9Ww8555lGWusuahDyNp6ulRXRwZTfYwxtaAv HhTQOvQN4CHNIJQgNk2h1MPrBcEJBtUoQPXDYewx1ETuXJQUl6Aw/fX2oKPHavDs2Bd9 DeEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=tNknw4rkY8W6ATOIefm+Gpr/5bs/KMOFzqtezxuRjSQ=; b=APJob0CITvIyYD5gMgrNJ/Uwj2Fk3vwGIY7eB3pZaeYOH8NDrkRouOEYCTTEWXezOT eplpnM5z3QxnmWRp2K/RFU8AiMdwJWF8TY+1q9LTGwZk7M7ftx4j7jRysHrMvIDeZogr CXwq5kDCEhnrv3C18a8MU2e4hOREXor7g4f1TTH/+idsPI/MJ9pNtZfykAHW6F4aNkKo BlylXP+PoKz+v6N4Urj+LsfQPx1u+2IKDXTF6+tc4sWxDD6c6rfDx7GdqEBBCZr6Lnzu pilYyBzbYwzJiNWhN6fCgYs+vbNrH3uPVxAM+ekCul1aR4s0oRFFE5XMJ6qakC5BKIy8 yJow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f6NTW4rA; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 91-v6si7981107ply.405.2018.08.10.07.21.54; Fri, 10 Aug 2018 07:21:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f6NTW4rA; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728229AbeHJQwA (ORCPT + 4 others); Fri, 10 Aug 2018 12:52:00 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:38409 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728224AbeHJQwA (ORCPT ); Fri, 10 Aug 2018 12:52:00 -0400 Received: by mail-wr1-f66.google.com with SMTP id v14-v6so8468230wro.5 for ; Fri, 10 Aug 2018 07:21:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tNknw4rkY8W6ATOIefm+Gpr/5bs/KMOFzqtezxuRjSQ=; b=f6NTW4rAm//pcyyOJxDfjXP6gt+NTbsAjGiVpSeK3VbhOPw9kgG+wEW2o6kE41HHeC aUSm9ulF7FxSZykytoxNHTmQQ9/HHnCsLn8Vd4ucaQVCyRWttZ2inY/4MhL19ZBONbdE JPpihJAxfY1hqE8bEBcSqgeDv3uC/ZLWggNi0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tNknw4rkY8W6ATOIefm+Gpr/5bs/KMOFzqtezxuRjSQ=; b=o3ovU1S4evYy6Ooygi+DdpBXmDiD+0zUOtRaxz3D+O26p+WO2SVOUToABWT3R0Yd7Y GE01KxxUjHeLNXC6Zh7T18aUbNMBxGmw8b7/qe4lzgJM1CfVO1U/wvicqVKbOsLb/3Qc UNC9iZS02uADQiUrEvXUp9xlyITSso3R+pIMcXFBUF3DjheqAqLOwlQs3eFHvHmy8yFQ 7JmUqZXntjR9N0QZvKungQRTDltOx2QBxns+90u2JqDKeJGXFhG1Q7IVBA9YCOh0kB7m HFeYbf9Rk9/Zznfu82WY6HVA7w2PJHjlFTEcCjx9SbIm+i5tF+TfEH4WG9+lWzr90M2G G+0Q== X-Gm-Message-State: AOUpUlHZ2DgFN1LJdq8mD8fbHKXLZvzK75RXy5e9gJfwK9NfNFhSQXZ8 hYBnr8AVERYpJVknRhp71ElBQQ== X-Received: by 2002:adf:e287:: with SMTP id v7-v6mr4593380wri.139.1533910912234; Fri, 10 Aug 2018 07:21:52 -0700 (PDT) Received: from arch-late.local (a109-49-46-234.cpe.netcabo.pt. [109.49.46.234]) by smtp.gmail.com with ESMTPSA id b13-v6sm13077578wrn.17.2018.08.10.07.21.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Aug 2018 07:21:51 -0700 (PDT) From: Rui Miguel Silva To: mchehab@kernel.org, sakari.ailus@linux.intel.com, Philipp Zabel , Rob Herring Cc: linux-media@vger.kernel.org, devel@driverdev.osuosl.org, Fabio Estevam , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ryan Harkin , Rui Miguel Silva Subject: [PATCH v7 09/12] ARM: dts: imx7s-warp: add ov2680 sensor node Date: Fri, 10 Aug 2018 15:20:42 +0100 Message-Id: <20180810142045.27657-10-rui.silva@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180810142045.27657-1-rui.silva@linaro.org> References: <20180810142045.27657-1-rui.silva@linaro.org> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Warp7 comes with a Omnivision OV2680 sensor, add the node here to make complete the camera data path for this system. Add the needed regulator to the analog voltage supply, the port and endpoints in mipi_csi node and the pinctrl for the reset gpio. Signed-off-by: Rui Miguel Silva --- arch/arm/boot/dts/imx7s-warp.dts | 44 ++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) -- 2.18.0 diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 8e098b90c525..b1c5d8f8a2ba 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -91,6 +91,14 @@ regulator-always-on; }; + reg_peri_3p15v: regulator-peri-3p15v { + compatible = "regulator-fixed"; + regulator-name = "peri_3p15v_reg"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "imx7-sgtl5000"; @@ -214,6 +222,27 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + ov2680: camera@36 { + compatible = "ovti,ov2680"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov2680>; + reg = <0x36>; + clocks = <&osc>; + clock-names = "xvclk"; + reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + DOVDD-supply = <&sw2_reg>; + DVDD-supply = <&sw2_reg>; + AVDD-supply = <®_peri_3p15v>; + + port { + ov2680_to_mipi: endpoint { + remote-endpoint = <&mipi_from_sensor>; + clock-lanes = <0>; + data-lanes = <1>; + }; + }; + }; }; &i2c4 { @@ -348,6 +377,15 @@ #size-cells = <0>; fsl,csis-hs-settle = <3>; + port@0 { + reg = <0>; + + mipi_from_sensor: endpoint { + remote-endpoint = <&ov2680_to_mipi>; + data-lanes = <1>; + }; + }; + port@1 { reg = <1>; @@ -404,6 +442,12 @@ >; }; + pinctrl_ov2680: ov2660grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 + >; + }; + pinctrl_sai1: sai1grp { fsl,pins = < MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f From patchwork Fri Aug 10 14:20:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 143938 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp16116ljj; Fri, 10 Aug 2018 07:21:57 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxtBlhtVaJvA9+rqjJqnc/BNtzklrhH0dFQw+fGbX8ZUepnj+DTmg8qZ32xJvNNUZtT99Uj X-Received: by 2002:a63:1015:: with SMTP id f21-v6mr6792392pgl.354.1533910917501; Fri, 10 Aug 2018 07:21:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533910917; cv=none; d=google.com; s=arc-20160816; b=RsZ+cZSuWSt8r8KYyVuCiAu+1IBNTCcTVZ1jmq0avLRtB34W5ro42lrf4F/RgSyUoQ jwdhfARN5gJYOMdAL6bIyY2ICWs6U1oKsakykMWGTMBmUNsao01CP94nNfrCjLjlWwi3 1PmYLneVgryQE4Yb5ilfldOfZHV6IASesd+ojLNIG3y/VVDedYS1mLMNWClw6i1X9yMn 3mi8cQhsMe6jPR22+hAp1ThFK5X8FiHhjQr6mkv4jW5fb7Hnr5riuRzeSaKxc/n3K2fm +/Yjoh/c0TZECNDJE2Wkyyt7d8i4RZe2wkF4AgCyj9GGjkiV8ltgaykHQ+cIVOF+8+sG d9iA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=HLhi6DLyeVM7vNAvlklQUJ7sBVfU/dAer7JD04mR7ps=; b=pQBsh14/U440V2QVGXGULsdyoOeSsemkIbxC05txBqU8qIPzWADz13scwWtxt7xGZM ccSw9pa6im5eM+CGlGmBBpR171wVH2EVfNC0RzMzLdAV34ibwVNfaWFV7giBJBIkP9k3 A3Zn8vXUiwXkadDPnnZLu4YNgL2IwRVjvV+McTNP3u8tEcCQqSLm5V0BQN2TK8504DI1 PGj5GyCdsR5qd8vZmQea84uovOR8ZMiGATGL9bqOE0J9ED6ZVKPtX8weNW7jXD3if4E0 4Fq7wZywKYF3UC7ETsC+9qIh7VXPi8EV+wIyniDMZCtlfAE/xhoF6VHosoFh55a8GuVk ndJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cjCfpwGI; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 91-v6si7981107ply.405.2018.08.10.07.21.57; Fri, 10 Aug 2018 07:21:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cjCfpwGI; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728234AbeHJQwD (ORCPT + 4 others); Fri, 10 Aug 2018 12:52:03 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:52304 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727778AbeHJQwD (ORCPT ); Fri, 10 Aug 2018 12:52:03 -0400 Received: by mail-wm0-f66.google.com with SMTP id o11-v6so2092916wmh.2 for ; Fri, 10 Aug 2018 07:21:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HLhi6DLyeVM7vNAvlklQUJ7sBVfU/dAer7JD04mR7ps=; b=cjCfpwGIugY34lwsOAPtil+qba3eKeRXL81luzpY27rtnd0DTGZyhUtGVfHYPf2Obj HyF2yC9+03vwwkMljwDdU3PU7jhRdN1hDAFYnU8hhGq+4/StyEniKlA+tNMD8zWHDDrQ zYuUkoYM8FuZz9HJnaAtsrhoX3Cf4kSn3JBHE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HLhi6DLyeVM7vNAvlklQUJ7sBVfU/dAer7JD04mR7ps=; b=oEe6C997+OBqeWIaQyJ48wgp99GsyOYZlrs3AtV+t/QuRLoyrMPxZOQPVKojtQKkqM UBEvlCWEqP/qprbMg4U/UO+B5VqpNokDebV9uVlxlutJH49kO8W0tA+VOG+IcmQ46VAu dvuzhp0KKz1tr9Z0bVmD7uFHVygHqrRQSAplZXuV2vuYRWY92NRua31Xy3Xy/MgeagWX Q6Aj3tlrvjnHlIWYyod/GZmP11tkjSNsPDrmdvWMw4Q3RSB12QvaaPvQjamt8Ud7a/1r 1a0h+6YoyeKorzHmZKa38bsHgWn/C0XQ+aa73wCpPbN7an7inruMxtHT+dQXs1CH5/2o 3GkA== X-Gm-Message-State: AOUpUlGqMgxWkLdSx+4FtvmRd/WlByYcXLm38wU/F/edL+F3ip0eIt62 uNCX8C7hnUy7wPkEAKUoKMdqmw== X-Received: by 2002:a1c:545:: with SMTP id 66-v6mr1746623wmf.140.1533910914520; Fri, 10 Aug 2018 07:21:54 -0700 (PDT) Received: from arch-late.local (a109-49-46-234.cpe.netcabo.pt. [109.49.46.234]) by smtp.gmail.com with ESMTPSA id b13-v6sm13077578wrn.17.2018.08.10.07.21.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Aug 2018 07:21:53 -0700 (PDT) From: Rui Miguel Silva To: mchehab@kernel.org, sakari.ailus@linux.intel.com, Philipp Zabel , Rob Herring Cc: linux-media@vger.kernel.org, devel@driverdev.osuosl.org, Fabio Estevam , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ryan Harkin , Rui Miguel Silva Subject: [PATCH v7 10/12] media: imx7.rst: add documentation for i.MX7 media driver Date: Fri, 10 Aug 2018 15:20:43 +0100 Message-Id: <20180810142045.27657-11-rui.silva@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180810142045.27657-1-rui.silva@linaro.org> References: <20180810142045.27657-1-rui.silva@linaro.org> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add rst document to describe the i.MX7 media driver and also a working example from the Warp7 board usage with a OV2680 sensor. Signed-off-by: Rui Miguel Silva --- Documentation/media/v4l-drivers/imx7.rst | 157 ++++++++++++++++++++++ Documentation/media/v4l-drivers/index.rst | 1 + 2 files changed, 158 insertions(+) create mode 100644 Documentation/media/v4l-drivers/imx7.rst -- 2.18.0 diff --git a/Documentation/media/v4l-drivers/imx7.rst b/Documentation/media/v4l-drivers/imx7.rst new file mode 100644 index 000000000000..cd1195d391c5 --- /dev/null +++ b/Documentation/media/v4l-drivers/imx7.rst @@ -0,0 +1,157 @@ +i.MX7 Video Capture Driver +========================== + +Introduction +------------ + +The i.MX7 contrary to the i.MX5/6 family does not contain an Image Processing +Unit (IPU); because of that the capabilities to perform operations or +manipulation of the capture frames are less feature rich. + +For image capture the i.MX7 has three units: +- CMOS Sensor Interface (CSI) +- Video Multiplexer +- MIPI CSI-2 Receiver + +:: + |\ + MIPI Camera Input ---> MIPI CSI-2 --- > | \ + | \ + | M | + | U | ------> CSI ---> Capture + | X | + | / + Parallel Camera Input ----------------> | / + |/ + +For additional information, please refer to the latest versions of the i.MX7 +reference manual [#f1]_. + +Entities +-------- + +imx7-mipi-csi2 +-------------- + +This is the MIPI CSI-2 receiver entity. It has one sink pad to receive the pixel +data from MIPI CSI-2 camera sensor. It has one source pad, corresponding to the +virtual channel 0. This module is compliant to previous version of Samsung +D-phy, and supports two D-PHY Rx Data lanes. + +csi_mux +------- + +This is the video multiplexer. It has two sink pads to select from either camera +sensor with a parallel interface or from MIPI CSI-2 virtual channel 0. It has +a single source pad that routes to the CSI. + +csi +--- + +The CSI enables the chip to connect directly to external CMOS image sensor. CSI +can interface directly with Parallel and MIPI CSI-2 buses. It has 256 x 64 FIFO +to store received image pixel data and embedded DMA controllers to transfer data +from the FIFO through AHB bus. + +This entity has one sink pad that receives from the csi_mux entity and a single +source pad that routes video frames directly to memory buffers. This pad is +routed to a capture device node. + +Usage Notes +----------- + +To aid in configuration and for backward compatibility with V4L2 applications +that access controls only from video device nodes, the capture device interfaces +inherit controls from the active entities in the current pipeline, so controls +can be accessed either directly from the subdev or from the active capture +device interface. For example, the sensor controls are available either from the +sensor subdevs or from the active capture device. + +Warp7 with OV2680 +----------------- + +On this platform an OV2680 MIPI CSI-2 module is connected to the internal MIPI +CSI-2 receiver. The following example configures a video capture pipeline with +an output of 800x600, and BGGR 10 bit bayer format: + +.. code-block:: none + # Setup links + media-ctl -l "'ov2680 1-0036':0 -> 'imx7-mipi-csis.0':0[1]" + media-ctl -l "'imx7-mipi-csis.0':1 -> 'csi_mux':1[1]" + media-ctl -l "'csi_mux':2 -> 'csi':0[1]" + media-ctl -l "'csi':1 -> 'csi capture':0[1]" + + # Configure pads for pipeline + media-ctl -V "'ov2680 1-0036':0 [fmt:SBGGR10_1X10/800x600 field:none]" + media-ctl -V "'csi_mux':1 [fmt:SBGGR10_1X10/800x600 field:none]" + media-ctl -V "'csi_mux':2 [fmt:SBGGR10_1X10/800x600 field:none]" + media-ctl -V "'imx7-mipi-csis.0':0 [fmt:SBGGR10_1X10/800x600 field:none]" + media-ctl -V "'csi':0 [fmt:SBGGR10_1X10/800x600 field:none]" + +After this streaming can start. The v4l2-ctl tool can be used to select any of +the resolutions supported by the sensor. + +.. code-block:: none + root@imx7s-warp:~# media-ctl -p + Media controller API version 4.17.0 + + Media device information + ------------------------ + driver imx-media + model imx-media + serial + bus info + hw revision 0x0 + driver version 4.17.0 + + Device topology + - entity 1: csi (2 pads, 2 links) + type V4L2 subdev subtype Unknown flags 0 + device node name /dev/v4l-subdev0 + pad0: Sink + [fmt:SBGGR10_1X10/800x600 field:none] + <- "csi_mux":2 [ENABLED] + pad1: Source + [fmt:SBGGR10_1X10/800x600 field:none] + -> "csi capture":0 [ENABLED] + + - entity 4: csi capture (1 pad, 1 link) + type Node subtype V4L flags 0 + device node name /dev/video0 + pad0: Sink + <- "csi":1 [ENABLED] + + - entity 10: csi_mux (3 pads, 2 links) + type V4L2 subdev subtype Unknown flags 0 + device node name /dev/v4l-subdev1 + pad0: Sink + [fmt:unknown/0x0] + pad1: Sink + [fmt:unknown/800x600 field:none] + <- "imx7-mipi-csis.0":1 [ENABLED] + pad2: Source + [fmt:unknown/800x600 field:none] + -> "csi":0 [ENABLED] + + - entity 14: imx7-mipi-csis.0 (2 pads, 2 links) + type V4L2 subdev subtype Unknown flags 0 + device node name /dev/v4l-subdev2 + pad0: Sink + [fmt:SBGGR10_1X10/800x600 field:none] + <- "ov2680 1-0036":0 [ENABLED] + pad1: Source + [fmt:SBGGR10_1X10/800x600 field:none] + -> "csi_mux":1 [ENABLED] + + - entity 17: ov2680 1-0036 (1 pad, 1 link) + type V4L2 subdev subtype Sensor flags 0 + device node name /dev/v4l-subdev3 + pad0: Source + [fmt:SBGGR10_1X10/800x600 field:none] + -> "imx7-mipi-csis.0":0 [ENABLED] + + +References +---------- + +.. [#f1] https://www.nxp.com/docs/en/reference-manual/IMX7SRM.pdf diff --git a/Documentation/media/v4l-drivers/index.rst b/Documentation/media/v4l-drivers/index.rst index 679238e786a7..693295bbc53f 100644 --- a/Documentation/media/v4l-drivers/index.rst +++ b/Documentation/media/v4l-drivers/index.rst @@ -44,6 +44,7 @@ For more details see the file COPYING in the source distribution of Linux. davinci-vpbe fimc imx + imx7 ivtv max2175 meye From patchwork Fri Aug 10 14:20:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 143939 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp16155ljj; Fri, 10 Aug 2018 07:21:59 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyjVVcf2Dq2xdOwS/EsguC3Z8MW0BZCJ9/lPoinldnOgeXhK7UZIqi9wkLBChJsESvXGl4J X-Received: by 2002:a17:902:14cb:: with SMTP id y11-v6mr6358592plg.317.1533910919404; Fri, 10 Aug 2018 07:21:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533910919; cv=none; d=google.com; s=arc-20160816; b=wsqpgBYqLYCTfoyG24SXgEGRiOR/2WcO8sTO1ukAMu+qG36+cL549r9ImZm5Pdcdbp hSn6/5ZohHw9E4XWETyJKhFG+szQ7Lhvz4HQ5ViBCacsuJorDUTaufCQg6bXMveNwZGm zJWI231qFLDwPxyZoeVjxnRY9YYNAycpUfL2YFsJUo5wnOtN5eB751qGTE37IcHsqQAn VZhvs0gBrhpbIOsPUMu+bxhyMWCpaXdEolZ3E9p5VUflm4OuMvUpaRQg6nFzPGRY7TPn AuKk81tQU3mWfaaiM3+Amk5kT0wEFgElnMZySDVitXSwiJkblj18g2L7NJW7smtrCeMr MFIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=uSbBtqSPAxWQFdM8x3nmuj9bK3YqAczna83k8c5H+bg=; b=di7NqDvSNwxsk/mGn/VTL84ky7Wv53QgVTayYa9sJda97ak6SODoUjEXbkG8vhsXwQ jR2+fG4L1BCUvjsBnv2ko91faVg5cXj8mcRTwsK9EqZX+AMDXtTCXQ4k66RGdVXrhVQJ u/Lh+lGJUEJJ9RooHs7VEe8gJ+5HeGvxp7dMQCTryXItBMa9SttNsFnpNyWcIbR/kJSj 1QYWOR7xJoeZFT3Uy1GTYtBGbaSLRPn/mmzRi/eDADXokHzPvp8uCFbwRQaaqcSiYsjM vtVgxLkNllZLQOVE86CKqnHEhaZnO0dzgegRE+1YJAvDPVlrQVlOnO8TH3HOF6Q1syM9 JuDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="X+CUDu/F"; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 91-v6si7981107ply.405.2018.08.10.07.21.59; Fri, 10 Aug 2018 07:21:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="X+CUDu/F"; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728238AbeHJQwF (ORCPT + 4 others); Fri, 10 Aug 2018 12:52:05 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:39050 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728236AbeHJQwF (ORCPT ); Fri, 10 Aug 2018 12:52:05 -0400 Received: by mail-wr1-f65.google.com with SMTP id h10-v6so8460054wre.6 for ; Fri, 10 Aug 2018 07:21:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uSbBtqSPAxWQFdM8x3nmuj9bK3YqAczna83k8c5H+bg=; b=X+CUDu/FXlZrJuU6Aw8R1aRzwBMO6XRpu6wxmof25mNyg2HCsdOTQYsesqUKfK3NQP 21I42e2EfpWPyT6bleu+oXWeZ2qvNaumlHWE2Az6sJThrYPm8TlNPuTY4LIo7t0ejCVr rMB99Dd0a6gVz5BQ6QTP5g32McgDJ4a5Hi0Ec= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uSbBtqSPAxWQFdM8x3nmuj9bK3YqAczna83k8c5H+bg=; b=H8OoQKHHnywhqZeikrrN/n5XoUcCZauHNpVjzcaVexuWeIPx/jV56oPCGjSmx9n/Ii MDaR03jSIhj5fmqHcl9efGRK+saBTcrMsMBtZ0/en5016vDb3HIAOzVihV0vA3E7T2/1 V+ytgQGsWTgdtGhquobN9Md+t85ozM8mNpOewT+bhmd1MveEsYvQs0tnAbq/2CHlDZ5E gSml/bqV53iH4XKWbkxJWnuKW14Fdtffwp1XhXEsdHACM77iDVQW1j4tqW77lDGAzMbp S2E0L9ieO1ZG8dvFtQvdfIH/aOBQRpNtWAYmwC0qFIv5BFO285pKwD80aYOdeXpTYovG WI+w== X-Gm-Message-State: AOUpUlFDEmNSBKzyvvW6Z6GGgUV//i6wwxzYUzW5KkOg7DRhsmS9rK+T hRHiGwEzi52azu4CAtVtk75Ltg== X-Received: by 2002:adf:fe42:: with SMTP id m2-v6mr4259933wrs.171.1533910916843; Fri, 10 Aug 2018 07:21:56 -0700 (PDT) Received: from arch-late.local (a109-49-46-234.cpe.netcabo.pt. [109.49.46.234]) by smtp.gmail.com with ESMTPSA id b13-v6sm13077578wrn.17.2018.08.10.07.21.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Aug 2018 07:21:56 -0700 (PDT) From: Rui Miguel Silva To: mchehab@kernel.org, sakari.ailus@linux.intel.com, Philipp Zabel , Rob Herring Cc: linux-media@vger.kernel.org, devel@driverdev.osuosl.org, Fabio Estevam , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ryan Harkin , Rui Miguel Silva Subject: [PATCH v7 11/12] media: staging/imx: add i.MX7 entries to TODO file Date: Fri, 10 Aug 2018 15:20:44 +0100 Message-Id: <20180810142045.27657-12-rui.silva@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180810142045.27657-1-rui.silva@linaro.org> References: <20180810142045.27657-1-rui.silva@linaro.org> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add some i.MX7 related entries to TODO file. Signed-off-by: Rui Miguel Silva --- drivers/staging/media/imx/TODO | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.18.0 diff --git a/drivers/staging/media/imx/TODO b/drivers/staging/media/imx/TODO index aeeb15494a49..6f29b5ca5324 100644 --- a/drivers/staging/media/imx/TODO +++ b/drivers/staging/media/imx/TODO @@ -45,3 +45,12 @@ Which means a port must not contain mixed-use endpoints, they must all refer to media links between V4L2 subdevices. + +- i.MX7: all of the above, since it uses the imx media core + +- i.MX7: use Frame Interval Monitor + +- i.MX7: runtime testing with parallel sensor, links setup and streaming + +- i.MX7: runtime testing with different formats, for the time only 10-bit bayer + is tested