From patchwork Thu Aug 16 07:16:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 144317 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1729317ljj; Thu, 16 Aug 2018 00:17:35 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzM7pGSQFxXfSKsqqsKqwhsif1YO00V40GumEvOmORvrTM5oWAqy9iH6mTk8qvzWq6DgFqt X-Received: by 2002:a63:ce12:: with SMTP id y18-v6mr27868697pgf.144.1534403855645; Thu, 16 Aug 2018 00:17:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534403855; cv=none; d=google.com; s=arc-20160816; b=q64YhCiErcbBeszUNsUQn+Azzxl8L758xoYiw5W6iaHsYMrYHNrGblJJWa1j9+HOAS Gmqa4/N9f1cWTVMIsV1i3FACuhiEippjzeImEMam0lvzZf92yoVNx/PyjD+TYVUEUp3O WloRAzIevfWT9bMrwwZHo7/Oukf4cIZY+5bQfkmOIWRao7WZk4KRCHIRcYdmZ3lJjAU1 ssgREVnfKDFyNCpkvvXsLHYelYfOfxAlc1C6TYVlzzFgtbeNZfRTc6B37HK9RiKvQKcR z1cYwdSi8tGp1jJqO993k9rZ5FUmV8JSkAEcMvWT8dxVFztdR8c/+VlX582PVy84cRoK N9vA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=iOqa3MVJTgThLO3R5ogXzqteEtZmxKIA0o0Ba20+3BE=; b=lPgI4EdAriMrgkBM+xYLW/gB0mbt2DtuLJi1G53y+KdoAf8Uzu+Jyalof3CVLMXUX0 8kh3VrQ6SMey+IrsAPNBbsd2jb0tA80GOGF9gQngvaEfpC9Wvc9zoLiwGXa1fjkp17yK DYHEyQ/tFxdTEYDFzad5w9j+lCaxiuHK/mkdMVlAFSCF08vP9o4Q6D0khmavY1VLhcWz GZB+KZ+nES16s9U7yHpyTEzy0u+dR41ecBVSV6CJMwEvPfi8B1hupf8z2Ux7yZ25c7V9 v3cPl1znG5W3hz4nrAMJ2GKronahvW/FlGovHY6k7tjNUjGdXMLhRI1J6bp697FbSMJz B84Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=LYK8ndVH; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f12-v6si24878828pgm.601.2018.08.16.00.17.35; Thu, 16 Aug 2018 00:17:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=LYK8ndVH; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389264AbeHPKOA (ORCPT + 5 others); Thu, 16 Aug 2018 06:14:00 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:17013 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389266AbeHPKOA (ORCPT ); Thu, 16 Aug 2018 06:14:00 -0400 Received: from grover.tkatk1.zaq.ne.jp (zaqdadce369.zaq.ne.jp [218.220.227.105]) (authenticated) by conuserg-09.nifty.com with ESMTP id w7G7Gu2H008336; Thu, 16 Aug 2018 16:16:57 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com w7G7Gu2H008336 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1534403818; bh=iOqa3MVJTgThLO3R5ogXzqteEtZmxKIA0o0Ba20+3BE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LYK8ndVH21aRXG+Djr6wVXZqA0wJ+g5MjBzytd2eka71FgWaJQvz2eufYzZM41zJi 4+UnNaTey7QAYCDiQvyhzHu2JEvtkfq62OP8xQyvfd8vIWlxULR+N6KuY8w9AHuACY yRSRLkkCVjs6eZFvgXsTy/rWX88BZcJNeYpfjq+mhtFXeRXu1rkO/KZn2MbYggX/NY r+LNwX9A5/2/jJe0QQIJ/tGm6y8n7T7fkZgW5S+NaophUe23QzoKzRfiMrTdp4m5hF QMZSDe2X6TJojwOzwVUyEzjdZD5lwiV587I1jfo2jzE4GCUqQpgdi4XjGT0cbwjpxE evx5CHTcwTAvg== X-Nifty-SrcIP: [218.220.227.105] From: Masahiro Yamada To: linux-mmc@vger.kernel.org, Wolfram Sang Cc: Masami Hiramatsu , Jassi Brar , Ulf Hansson , linux-renesas-soc@vger.kernel.org, Masahiro Yamada Subject: [PATCH v2 1/7] mmc: tmio: replace tmio_mmc_clk_stop() calls with tmio_mmc_set_clock() Date: Thu, 16 Aug 2018 16:16:33 +0900 Message-Id: <1534403799-10594-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> References: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org tmio_mmc_clk_stop(host) is equivalent to tmio_mmc_set_clock(host, 0). This replacement is needed for the next commit. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mmc/host/tmio_mmc_core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.7.4 Reviewed-by: Wolfram Sang diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c index 3cb554c..991b340 100644 --- a/drivers/mmc/host/tmio_mmc_core.c +++ b/drivers/mmc/host/tmio_mmc_core.c @@ -1032,7 +1032,7 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) switch (ios->power_mode) { case MMC_POWER_OFF: tmio_mmc_power_off(host); - tmio_mmc_clk_stop(host); + tmio_mmc_set_clock(host, 0); break; case MMC_POWER_UP: tmio_mmc_power_on(host, ios->vdd); @@ -1269,7 +1269,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) if (pdata->flags & TMIO_MMC_SDIO_IRQ) _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; - tmio_mmc_clk_stop(_host); + tmio_mmc_set_clock(_host, 0); tmio_mmc_reset(_host); _host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK); @@ -1353,7 +1353,7 @@ int tmio_mmc_host_runtime_suspend(struct device *dev) tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL); if (host->clk_cache) - tmio_mmc_clk_stop(host); + tmio_mmc_set_clock(host, 0); tmio_mmc_clk_disable(host); From patchwork Thu Aug 16 07:16:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 144320 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1729340ljj; Thu, 16 Aug 2018 00:17:36 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxeuebXf02b7BZtcgqCptrdni/1FSq7cevX/IDgcjkMqQ9KTIibXErC7+nMDL25fumkdrYV X-Received: by 2002:a17:902:e005:: with SMTP id ca5-v6mr27550421plb.224.1534403856775; Thu, 16 Aug 2018 00:17:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534403856; cv=none; d=google.com; s=arc-20160816; b=jYWUdOfrYdzFbrzRwCAwrMLvNlCuFfKHm45VmdcbUbEV3UipVj9QTbisKto/KgOYu4 TCd6QLp88PiMNN8TQBKNAJPbkzPqr3cg+VZWZVu1h7gvSJjO4tsb/XgyRH1yMU4PIQUf +is/ojby5HgTuq7LVGFZWhmRBQH/VvCB84IipIxHviNa5NNg10xtNq2Ih3FhATTbz7+6 y2pTCj9SAd3dBwukIJiPvur78mOvITsrS5USuGXnf+5+p2/+EwTuRDgJdr0Khe6ROljE 6rHqs5xCTLbSUo6/dnlU4C4w2kxw8oJzQEBwnphMpl0ukWVbpjrkvI9NDPnSEZAII0MS erLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=tzun5EuwErborZ1t9+/tHU8skqOmSC5qct9W8SZQT40=; b=S7KR5XQDQaFe/chko+zWq05bJ7NGjUvq58GE4S1nRVDblAVXtaVS/BLTHUv/xbawHc D7/TwQUe5GVRiMYARfu3W0+m2Lyg9G07wyVVASvADiF+KBpWjHEa0HKmx1qZiJOFWZ5D dZWmT9evy9iU0BJP71+NcVp9ULx3LQvCQjHgl1pCnpDxq/NiJrrbCfhFJojM/6sJ16HR thfhrjcBCg0rdpUguKIuj9uCDlRI2OeLdOer6yeQWG8y/YoXPMGuApopBIRw6KSr89nb eFew/1YIKeiWUnRVhj+kDuAqlFjAFkLSdbSopP0Ylyu1KGHl5ZZryDFb9A641HRhS4KB gBCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=MSaqss2B; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f12-v6si24878828pgm.601.2018.08.16.00.17.36; Thu, 16 Aug 2018 00:17:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=MSaqss2B; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389123AbeHPKOC (ORCPT + 5 others); Thu, 16 Aug 2018 06:14:02 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:17049 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389265AbeHPKOB (ORCPT ); Thu, 16 Aug 2018 06:14:01 -0400 Received: from grover.tkatk1.zaq.ne.jp (zaqdadce369.zaq.ne.jp [218.220.227.105]) (authenticated) by conuserg-09.nifty.com with ESMTP id w7G7Gu2I008336; Thu, 16 Aug 2018 16:16:58 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com w7G7Gu2I008336 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1534403818; bh=tzun5EuwErborZ1t9+/tHU8skqOmSC5qct9W8SZQT40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MSaqss2BjWkSDIVG+DzUBB/w5QiA+oE7xuZJSGaDw/ytlosRr6f8ZG2iLvAkzGgng 3WvzQHd69e1KZMLKiH5cooY/LnFw2rGUo+wCvQA+pq/E6zlHrGXOze96wzhzOrqC7o lSR84w/ZOOQAmqKJUFPqO4StL/89oNzPVr9qQ67h0LL9B6PBdZuC47xz7Ben9GI2nf J8sfsb5UQhND/5N54BOLyvPCM8KLAbZW0m80bNp4rYli1afceyPcEz1dNmZGFURHgn kVMmVKdkbJmDnn1ACheFSeSYy0ajfBPNypwPLl296PT1C0BVJi4MN0V2F8y5gC+PO3 fzf4V0dHz4hgg== X-Nifty-SrcIP: [218.220.227.105] From: Masahiro Yamada To: linux-mmc@vger.kernel.org, Wolfram Sang Cc: Masami Hiramatsu , Jassi Brar , Ulf Hansson , linux-renesas-soc@vger.kernel.org, Masahiro Yamada Subject: [PATCH v2 2/7] mmc: tmio: move tmio_mmc_set_clock() to platform hook Date: Thu, 16 Aug 2018 16:16:34 +0900 Message-Id: <1534403799-10594-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> References: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org tmio_mmc_set_clock() is full of quirks because different SoC vendors extended this in different ways. The original IP defines the divisor range 1/2 ... 1/512. bit 7 is set: 1/512 bit 6 is set: 1/256 ... bit 0 is set: 1/4 all bits clear: 1/2 It is platform-dependent how to achieve the 1/1 clock. I guess the TMIO-MFD variant uses the clock selector outside of this IP, as far as I see tmio_core_mmc_clk_div() in drivers/mfd/tmio_core.c I guess bit[7:0]=0xff is Renesas-specific extension. Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer versions of UniPhier SoC variants use bit 16 for 1/1024. host->clk_update() is only used by the Renesas variants, whereas host->set_clk_div() is only used by the TMIO-MFD variants. To cope with this mess, promote tmio_mmc_set_clock() to a new platform hook ->set_clock(), and melt the old two hooks into it. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mmc/host/renesas_sdhi_core.c | 50 ++++++++++++++++++++++- drivers/mmc/host/tmio_mmc.c | 48 ++++++++++++++++++++++ drivers/mmc/host/tmio_mmc.h | 4 +- drivers/mmc/host/tmio_mmc_core.c | 79 ++++-------------------------------- 4 files changed, 105 insertions(+), 76 deletions(-) -- 2.7.4 Reviewed-by: Wolfram Sang diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index 45c015da..1f4c82e 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -155,6 +155,54 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, return ret == 0 ? best_freq : clk_get_rate(priv->clk); } +static void renesas_sdhi_clk_start(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + /* HW engineers overrode docs: no sleep needed on R-Car2+ */ + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) + usleep_range(10000, 11000); +} + +static void renesas_sdhi_clk_stop(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + /* HW engineers overrode docs: no sleep needed on R-Car2+ */ + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) + usleep_range(10000, 11000); +} + +static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, + unsigned int new_clock) +{ + u32 clk = 0, clock; + + if (new_clock == 0) { + renesas_sdhi_clk_stop(host); + return; + } + + clock = renesas_sdhi_clk_update(host, new_clock) / 512; + + for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) + clock <<= 1; + + /* 1/1 clock is option */ + if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) + clk |= 0xff; + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) + usleep_range(10000, 11000); + + renesas_sdhi_clk_start(host); +} + static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) { struct renesas_sdhi *priv = host_to_priv(host); @@ -530,8 +578,8 @@ int renesas_sdhi_probe(struct platform_device *pdev, host->write16_hook = renesas_sdhi_write16_hook; host->clk_enable = renesas_sdhi_clk_enable; - host->clk_update = renesas_sdhi_clk_update; host->clk_disable = renesas_sdhi_clk_disable; + host->set_clock = renesas_sdhi_set_clock; host->multi_io_quirk = renesas_sdhi_multi_io_quirk; host->dma_ops = dma_ops; diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c index 43a2ea5..b031a77 100644 --- a/drivers/mmc/host/tmio_mmc.c +++ b/drivers/mmc/host/tmio_mmc.c @@ -13,6 +13,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -23,6 +24,52 @@ #include "tmio_mmc.h" +static void tmio_mmc_clk_start(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + usleep_range(10000, 11000); + sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100); + usleep_range(10000, 11000); +} + +static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000); + usleep_range(10000, 11000); + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + usleep_range(10000, 11000); +} + +static void tmio_mmc_set_clock(struct tmio_mmc_host *host, + unsigned int new_clock) +{ + u32 clk = 0, clock; + + if (new_clock == 0) { + tmio_mmc_clk_stop(host); + return; + } + + clock = host->mmc->f_min; + + for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) + clock <<= 1; + + host->pdata->set_clk_div(host->pdev, (clk >> 22) & 1); + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); + usleep_range(10000, 11000); + + tmio_mmc_clk_start(host); +} + #ifdef CONFIG_PM_SLEEP static int tmio_mmc_suspend(struct device *dev) { @@ -100,6 +147,7 @@ static int tmio_mmc_probe(struct platform_device *pdev) /* SD control register space size is 0x200, 0x400 for bus_shift=1 */ host->bus_shift = resource_size(res) >> 10; + host->set_clock = tmio_mmc_set_clock; host->mmc->f_max = pdata->hclk; host->mmc->f_min = pdata->hclk / 512; diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h index e7d6513..e0aa3f9 100644 --- a/drivers/mmc/host/tmio_mmc.h +++ b/drivers/mmc/host/tmio_mmc.h @@ -132,7 +132,6 @@ struct tmio_mmc_host { /* Callbacks for clock / power control */ void (*set_pwr)(struct platform_device *host, int state); - void (*set_clk_div)(struct platform_device *host, int state); /* pio related stuff */ struct scatterlist *sg_ptr; @@ -169,10 +168,9 @@ struct tmio_mmc_host { /* Mandatory callback */ int (*clk_enable)(struct tmio_mmc_host *host); + void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock); /* Optional callbacks */ - unsigned int (*clk_update)(struct tmio_mmc_host *host, - unsigned int new_clock); void (*clk_disable)(struct tmio_mmc_host *host); int (*multi_io_quirk)(struct mmc_card *card, unsigned int direction, int blk_size); diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c index 991b340..74b8972 100644 --- a/drivers/mmc/host/tmio_mmc_core.c +++ b/drivers/mmc/host/tmio_mmc_core.c @@ -160,70 +160,6 @@ static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) } } -static void tmio_mmc_clk_start(struct tmio_mmc_host *host) -{ - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - /* HW engineers overrode docs: no sleep needed on R-Car2+ */ - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - usleep_range(10000, 11000); - - if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { - sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100); - usleep_range(10000, 11000); - } -} - -static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) -{ - if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { - sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000); - usleep_range(10000, 11000); - } - - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - /* HW engineers overrode docs: no sleep needed on R-Car2+ */ - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - usleep_range(10000, 11000); -} - -static void tmio_mmc_set_clock(struct tmio_mmc_host *host, - unsigned int new_clock) -{ - u32 clk = 0, clock; - - if (new_clock == 0) { - tmio_mmc_clk_stop(host); - return; - } - - if (host->clk_update) - clock = host->clk_update(host, new_clock) / 512; - else - clock = host->mmc->f_min; - - for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) - clock <<= 1; - - /* 1/1 clock is option */ - if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) - clk |= 0xff; - - if (host->set_clk_div) - host->set_clk_div(host->pdev, (clk >> 22) & 1); - - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - usleep_range(10000, 11000); - - tmio_mmc_clk_start(host); -} - static void tmio_mmc_reset(struct tmio_mmc_host *host) { /* FIXME - should we set stop clock reg here */ @@ -1032,15 +968,15 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) switch (ios->power_mode) { case MMC_POWER_OFF: tmio_mmc_power_off(host); - tmio_mmc_set_clock(host, 0); + host->set_clock(host, 0); break; case MMC_POWER_UP: tmio_mmc_power_on(host, ios->vdd); - tmio_mmc_set_clock(host, ios->clock); + host->set_clock(host, ios->clock); tmio_mmc_set_bus_width(host, ios->bus_width); break; case MMC_POWER_ON: - tmio_mmc_set_clock(host, ios->clock); + host->set_clock(host, ios->clock); tmio_mmc_set_bus_width(host, ios->bus_width); break; } @@ -1196,7 +1132,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) int ret; /* - * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from + * Check the sanity of mmc->f_min to prevent host->set_clock() from * looping forever... */ if (mmc->f_min == 0) @@ -1206,7 +1142,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) _host->write16_hook = NULL; _host->set_pwr = pdata->set_pwr; - _host->set_clk_div = pdata->set_clk_div; ret = tmio_mmc_init_ocr(_host); if (ret < 0) @@ -1269,7 +1204,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) if (pdata->flags & TMIO_MMC_SDIO_IRQ) _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; - tmio_mmc_set_clock(_host, 0); + _host->set_clock(_host, 0); tmio_mmc_reset(_host); _host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK); @@ -1353,7 +1288,7 @@ int tmio_mmc_host_runtime_suspend(struct device *dev) tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL); if (host->clk_cache) - tmio_mmc_set_clock(host, 0); + host->set_clock(host, 0); tmio_mmc_clk_disable(host); @@ -1374,7 +1309,7 @@ int tmio_mmc_host_runtime_resume(struct device *dev) tmio_mmc_clk_enable(host); if (host->clk_cache) - tmio_mmc_set_clock(host, host->clk_cache); + host->set_clock(host, host->clk_cache); if (host->native_hotplug) tmio_mmc_enable_mmc_irqs(host, From patchwork Thu Aug 16 07:16:35 2018 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id f12-v6si24878828pgm.601.2018.08.16.00.17.36; Thu, 16 Aug 2018 00:17:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=MaFvFiVF; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389273AbeHPKOB (ORCPT + 5 others); Thu, 16 Aug 2018 06:14:01 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:17026 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389123AbeHPKOB (ORCPT ); Thu, 16 Aug 2018 06:14:01 -0400 Received: from grover.tkatk1.zaq.ne.jp (zaqdadce369.zaq.ne.jp [218.220.227.105]) (authenticated) by conuserg-09.nifty.com with ESMTP id w7G7Gu2J008336; Thu, 16 Aug 2018 16:16:59 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com w7G7Gu2J008336 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1534403819; bh=gF5opo/Kiw7WOd87rkvMyhDeYTHftPlTR9SgPTml9ZU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MaFvFiVF2zskgPyaFWeAoQcyTNOogkNjRVlr3wCSeyfC93xln1OuvtY1ESCxoHFxu 6NqYOlnav6goGujRu6FM1fWKeqehKaP/j+veAcey2HYfs4eUMAX6wLZTZPho7RJkOa HzYPbXHIq8dx/HktLEccau5iNY+1sZ90JwtQFWl64WpOsjUehaJMfkE6QFAb5KhBVk en/vTFdciu/lanJkO+xRl0eL/dgFwoQo3lj6bQfQwZZqeBa0pt7MFoOKigRkUM+9sv YIq9qWHsfQcD4as/xc35Kj4yhS5T+HQI5L1OnVblcyVkq4GNl45kQlC1qHqA9NnMT8 sVzTiZ5NEVBMw== X-Nifty-SrcIP: [218.220.227.105] From: Masahiro Yamada To: linux-mmc@vger.kernel.org, Wolfram Sang Cc: Masami Hiramatsu , Jassi Brar , Ulf Hansson , linux-renesas-soc@vger.kernel.org, Masahiro Yamada Subject: [PATCH v2 3/7] dt-bindings: mmc: add DT binding for UniPhier SD/eMMC controller Date: Thu, 16 Aug 2018 16:16:35 +0900 Message-Id: <1534403799-10594-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> References: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This SD/eMMC controller is used for UniPhier SoC family. Signed-off-by: Masahiro Yamada Reviewed-by: Rob Herring --- Changes in v2: - Rename compatible "socionext,uniphier-sd-v3.1b" to "socionext,uniphier-sd-v3.1.1" .../devicetree/bindings/mmc/uniphier-sd.txt | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/uniphier-sd.txt -- 2.7.4 Acked-by: Wolfram Sang diff --git a/Documentation/devicetree/bindings/mmc/uniphier-sd.txt b/Documentation/devicetree/bindings/mmc/uniphier-sd.txt new file mode 100644 index 0000000..e1d6587 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/uniphier-sd.txt @@ -0,0 +1,55 @@ +UniPhier SD/eMMC controller + +Required properties: +- compatible: should be one of the following: + "socionext,uniphier-sd-v2.91" - IP version 2.91 + "socionext,uniphier-sd-v3.1" - IP version 3.1 + "socionext,uniphier-sd-v3.1.1" - IP version 3.1.1 +- reg: offset and length of the register set for the device. +- interrupts: a single interrupt specifier. +- clocks: a single clock specifier of the controller clock. +- reset-names: should contain the following: + "host" - mandatory for all versions + "bridge" - should exist only for "socionext,uniphier-sd-v2.91" + "hw" - should exist if eMMC hw reset line is available +- resets: a list of reset specifiers, corresponding to the reset-names + +Optional properties: +- pinctrl-names: if present, should contain the following: + "default" - should exist for all instances + "uhs" - should exist for SD instance with UHS support +- pinctrl-0: pin control state for the default mode +- pinctrl-1: pin control state for the UHS mode +- dma-names: should be "rx-tx" if present. + This property can exist only for "socionext,uniphier-sd-v2.91". +- dmas: a single DMA channel specifier + This property can exist only for "socionext,uniphier-sd-v2.91". +- bus-width: see mmc.txt +- cap-sd-highspeed: see mmc.txt +- cap-mmc-highspeed: see mmc.txt +- sd-uhs-sdr12: see mmc.txt +- sd-uhs-sdr25: see mmc.txt +- sd-uhs-sdr50: see mmc.txt +- cap-mmc-hw-reset: should exist if reset-names contains "hw". see mmc.txt +- non-removable: see mmc.txt + +Example: + + sd: sdhc@5a400000 { + compatible = "socionext,uniphier-sd-v2.91"; + reg = <0x5a400000 0x200>; + interrupts = <0 76 4>; + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_uhs>; + clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + }; From patchwork Thu Aug 16 07:16:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 144318 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1729304ljj; Thu, 16 Aug 2018 00:17:35 -0700 (PDT) X-Google-Smtp-Source: AA+uWPwJKiAHCkHZdR9pn1eCxTpq43L9NqxioLAqHf2h9X742Cz91o5JrSOGwWaa/dHr7z8CqKeI X-Received: by 2002:a62:b20c:: with SMTP id x12-v6mr31359456pfe.64.1534403854916; Thu, 16 Aug 2018 00:17:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534403854; cv=none; d=google.com; s=arc-20160816; b=jSMVRPAgBK1qBOvBSNrm3YTiIcTPIr9MXZIG5wi6KYUekXP78KRNxRoWZlliBZ2qXv BEd4dMrG/IO0OoVmBfzcus6DvbsaErEkUH/Of6xcLRWxZtFJvnzT6LOdRXIKZoGRy7ow q0uzLLLgkDBQzQ65LGvQm12x4jCw2MIDdN+AqJ+sIMKU6N/+IFgXgqMJYxuzLHPRq6tB LCOQncSgM+VBQhApynoh5tbkuiPXD4JZlQHQHCL2rvacBbCfqmLwQLUwOIpTTYFDGvha 7o9PStDKUCMnfXOFfE8k5gwKOjt6qjuKwey0VoesrCJGWnH5eYqDEXD32V/DklsFJAuD WJBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=in4Z6aAmTryvo34PxV9F4zDP0hVa6o7foIUKY4Yf9pk=; b=Kllyphn4VyDjD8hV4kNp9N5g0YQCY7+YouY/ZvkD2D6uU6f+jzC1drvRMP/9iKbZ6e b14fBOB973jWXhs2ZpHKxVaUa6Up2aE3X8mZHVZ85GnlIbTnGtt2biKqb9QFAY+ya4LC GOYdDcsWS0oRJomShaa00Gz6lAUqvbAiSO0YFKOpLwMPltZRiQWXEtUVIOkdF9bdfYHA kOnCPx1mbX925RypeiB3u0e88JV2JcghQrZq4cAo6uW/M5nrEs1b8pJ4H3E/uN1jJxsg rwaqAFYxTxPGKUNNkfb9M7sbJyO4qbF/9DdwaXixjN1AZYqEIcZ2I0gTlVXych+hLF2G Vezg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=DNe7Y2F6; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f12-v6si24878828pgm.601.2018.08.16.00.17.34; Thu, 16 Aug 2018 00:17:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=DNe7Y2F6; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389271AbeHPKOA (ORCPT + 5 others); Thu, 16 Aug 2018 06:14:00 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:16940 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeHPKOA (ORCPT ); Thu, 16 Aug 2018 06:14:00 -0400 Received: from grover.tkatk1.zaq.ne.jp (zaqdadce369.zaq.ne.jp [218.220.227.105]) (authenticated) by conuserg-09.nifty.com with ESMTP id w7G7Gu2K008336; Thu, 16 Aug 2018 16:16:59 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com w7G7Gu2K008336 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1534403820; bh=in4Z6aAmTryvo34PxV9F4zDP0hVa6o7foIUKY4Yf9pk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DNe7Y2F6gxePvR0mvM2kyisuqmJ/RMjl3O23w1iOgAT3JNeMK7nCbt1Hfh2sRGjXH jaHoLby+fIFw5eFvHTrVWqZcuUgQmAx0IGPb70NSEdFwrhQRk0NwpFZoebdTVnpO68 WpWnHVhYTb5VOnqfQV+X0JYmaikcsnwT0weCXs2elx1m1D2JwieBZhpilTQaFHWZms Ou8gWXieAd5xHAE/tHnUnUlM9x+xyJ5Lq1T+JEbA/DX+GJwRxbSzgnCNDlxgZ6nv93 xA/AsmsqFhBaOELNyhVQ7oxNpittSmC705d6ZZfuJsKaChN5ETdptI98aZgpX6TYlb vpN+guN7u8iaQ== X-Nifty-SrcIP: [218.220.227.105] From: Masahiro Yamada To: linux-mmc@vger.kernel.org, Wolfram Sang Cc: Masami Hiramatsu , Jassi Brar , Ulf Hansson , linux-renesas-soc@vger.kernel.org, Masahiro Yamada Subject: [PATCH v2 4/7] mmc: uniphier-sd: add UniPhier SD/eMMC controller driver Date: Thu, 16 Aug 2018 16:16:36 +0900 Message-Id: <1534403799-10594-5-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> References: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Here is another TMIO MMC variant found in Socionext UniPhier SoCs. As commit b6147490e6aa ("mmc: tmio: split core functionality, DMA and MFD glue") said, these MMC controllers use the IP from Panasonic. However, the MMC controller in the TMIO (Toshiba Mobile IO) MFD chip was the first upstreamed user of this IP. The common driver code for this IP is now called 'tmio-mmc-core' in Linux although it is a historical misnomer. Anyway, this driver select's MMC_TMIO_CORE to borrow the common code from tmio-mmc-core.c Older UniPhier SoCs (LD4, Pro4, sLD8) support the external DMA engine like renesas_sdhi_sys_dmac.c. The difference is UniPhier SoCs use a single DMA channel whereas Renesas chips request separate channels for RX and TX. Newer UniPhier SoCs (Pro5 and later) support the internal DMA engine like renesas_sdhi_internal_dmac.c The register map is almost the same, so I guess Renesas and Socionext use the same internal DMA hardware. The main difference is, the register offsets are doubled for Renesas. Renesas Socionext SDHI UniPhier DM_CM_DTRAN_MODE 0x820 0x410 DM_CM_DTRAN_CTRL 0x828 0x414 DM_CM_RST 0x830 0x418 DM_CM_INFO1 0x840 0x420 DM_CM_INFO1_MASK 0x848 0x424 DM_CM_INFO2 0x850 0x428 DM_CM_INFO2_MASK 0x858 0x42c DM_DTRAN_ADDR 0x880 0x440 DM_DTRAN_ADDREX --- 0x444 This comes from the difference of host->bus_shift; 2 for Renesas SoCs, and 1 for UniPhier SoCs. Also, the datasheet for UniPhier SoCs defines DM_DTRAN_ADDR and DM_DTRAN_ADDREX as two separate registers. It could be possible to factor out the DMA common code by introducing some hooks to cope with platform quirks, but this patch does not touch that for now. Signed-off-by: Masahiro Yamada --- Changes in v2: - Rename compatible "socionext,uniphier-sd-v3.1b" to "socionext,uniphier-sd-v3.1.1" - Use ->callback_result hook instead of deprecated ->callback MAINTAINERS | 1 + drivers/mmc/host/Kconfig | 10 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/uniphier-sd.c | 695 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 707 insertions(+) create mode 100644 drivers/mmc/host/uniphier-sd.c -- 2.7.4 Acked-by: Wolfram Sang diff --git a/MAINTAINERS b/MAINTAINERS index 3d08725..e293d44 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2163,6 +2163,7 @@ F: drivers/clk/uniphier/ F: drivers/gpio/gpio-uniphier.c F: drivers/i2c/busses/i2c-uniphier* F: drivers/irqchip/irq-uniphier-aidet.c +F: drivers/mmc/host/uniphier-sd.c F: drivers/pinctrl/uniphier/ F: drivers/reset/reset-uniphier.c F: drivers/tty/serial/8250/8250_uniphier.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 4a692e8..9df2de6 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -619,6 +619,16 @@ config MMC_SDHI_INTERNAL_DMAC using on-chip bus mastering. This supports the controllers found in arm64 based SoCs. +config MMC_UNIPHIER + tristate "UniPhier SD/eMMC Host Controller support" + depends on ARCH_UNIPHIER || COMPILE_TEST + depends on OF + select MMC_TMIO_CORE + help + This provides support for the SD/eMMC controller found in + UniPhier SoCs. The eMMC variant of this controller is used + only for 32-bit SoCs. + config MMC_CB710 tristate "ENE CB710 MMC/SD Interface support" depends on PCI diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 85dc132..363d7df 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MMC_TMIO_CORE) += tmio_mmc_core.o obj-$(CONFIG_MMC_SDHI) += renesas_sdhi_core.o obj-$(CONFIG_MMC_SDHI_SYS_DMAC) += renesas_sdhi_sys_dmac.o obj-$(CONFIG_MMC_SDHI_INTERNAL_DMAC) += renesas_sdhi_internal_dmac.o +obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o obj-$(CONFIG_MMC_CB710) += cb710-mmc.o obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o octeon-mmc-objs := cavium.o cavium-octeon.o diff --git a/drivers/mmc/host/uniphier-sd.c b/drivers/mmc/host/uniphier-sd.c new file mode 100644 index 0000000..8a29a8b --- /dev/null +++ b/drivers/mmc/host/uniphier-sd.c @@ -0,0 +1,695 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2017-2018 Socionext Inc. +// Author: Masahiro Yamada + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tmio_mmc.h" + +#define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16) +#define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10) +#define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop + +#define UNIPHIER_SD_CC_EXT_MODE 0x1b0 +#define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1) + +#define UNIPHIER_SD_HOST_MODE 0x1c8 + +#define UNIPHIER_SD_VOLT 0x1e4 +#define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0) +#define UNIPHIER_SD_VOLT_OFF 0 +#define UNIPHIER_SD_VOLT_330 1 // 3.3V signal +#define UNIPHIER_SD_VOLT_180 2 // 1.8V signal + +#define UNIPHIER_SD_DMA_MODE 0x410 +#define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16) +#define UNIPHIER_SD_DMA_MODE_DIR_TO_DEV 0 +#define UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1 +#define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4) +#define UNIPHIER_SD_DMA_MODE_WIDTH_8 0 +#define UNIPHIER_SD_DMA_MODE_WIDTH_16 1 +#define UNIPHIER_SD_DMA_MODE_WIDTH_32 2 +#define UNIPHIER_SD_DMA_MODE_WIDTH_64 3 +#define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed +#define UNIPHIER_SD_DMA_CTL 0x414 +#define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared) +#define UNIPHIER_SD_DMA_RST 0x418 +#define UNIPHIER_SD_DMA_RST_CH1 BIT(9) +#define UNIPHIER_SD_DMA_RST_CH0 BIT(8) +#define UNIPHIER_SD_DMA_ADDR_L 0x440 +#define UNIPHIER_SD_DMA_ADDR_H 0x444 + +/* + * IP is extended to support various features: built-in DMA engine, + * 1/1024 divisor, etc. + */ +#define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0) +/* RX channel of the built-in DMA controller is broken (Pro5) */ +#define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1) + +struct uniphier_sd_priv { + struct tmio_mmc_data tmio_data; + struct pinctrl *pinctrl; + struct pinctrl_state *pinstate_default; + struct pinctrl_state *pinstate_uhs; + struct clk *clk; + struct reset_control *rst; + struct reset_control *rst_br; + struct reset_control *rst_hw; + struct dma_chan *chan; + enum dma_data_direction dma_dir; + unsigned long clk_rate; + unsigned long caps; +}; + +static void *uniphier_sd_priv(struct tmio_mmc_host *host) +{ + return container_of(host->pdata, struct uniphier_sd_priv, tmio_data); +} + +static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable) +{ + sd_ctrl_write16(host, CTL_DMA_ENABLE, DMA_ENABLE_DMASDRW); +} + +/* external DMA engine */ +static void uniphier_sd_external_dma_issue(unsigned long arg) +{ + struct tmio_mmc_host *host = (void *)arg; + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + + uniphier_sd_dma_endisable(host, 1); + dma_async_issue_pending(priv->chan); +} + +static void uniphier_sd_external_dma_callback(void *param, + const struct dmaengine_result *result) +{ + struct tmio_mmc_host *host = param; + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + unsigned long flags; + + dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, + priv->dma_dir); + + spin_lock_irqsave(&host->lock, flags); + + /* + * When the external DMA engine is enabled, strangely enough, the + * DATAEND flag can be asserted even if the DMA engine has not been + * kicked yet. Enable the TMIO_STAT_DATAEND interrupt only after we + * make sure the DMA engine finish the transfer, i.e. in its callback. + */ + tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); + spin_unlock_irqrestore(&host->lock, flags); +} + +static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host, + struct mmc_data *data) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + enum dma_transfer_direction dma_tx_dir; + struct dma_async_tx_descriptor *desc; + dma_cookie_t cookie; + int sg_len; + + if (!priv->chan) + goto force_pio; + + if (data->flags & MMC_DATA_READ) { + priv->dma_dir = DMA_FROM_DEVICE; + dma_tx_dir = DMA_DEV_TO_MEM; + } else { + priv->dma_dir = DMA_TO_DEVICE; + dma_tx_dir = DMA_MEM_TO_DEV; + } + + sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, + priv->dma_dir); + if (sg_len == 0) + goto force_pio; + + desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len, + dma_tx_dir, DMA_CTRL_ACK); + if (!desc) + goto unmap_sg; + + desc->callback_result = uniphier_sd_external_dma_callback; + desc->callback_param = host; + + cookie = dmaengine_submit(desc); + if (cookie < 0) + goto unmap_sg; + + return; + +unmap_sg: + dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, + priv->dma_dir); +force_pio: + host->force_pio = true; + uniphier_sd_dma_endisable(host, 0); +} + +static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host, + bool enable) +{ +} + +static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host, + struct tmio_mmc_data *pdata) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + struct dma_chan *chan; + + chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx"); + if (IS_ERR(chan)) { + dev_warn(mmc_dev(host->mmc), + "failed to request DMA channel. falling back to PIO\n"); + return; /* just use PIO even for -EPROBE_DEFER */ + } + + /* this driver uses a single channel for both RX an TX */ + priv->chan = chan; + host->chan_rx = chan; + host->chan_tx = chan; + + tasklet_init(&host->dma_issue, uniphier_sd_external_dma_issue, + (unsigned long)host); +} + +static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + + if (priv->chan) + dma_release_channel(priv->chan); +} + +static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + + uniphier_sd_dma_endisable(host, 0); + + if (priv->chan) + dmaengine_terminate_sync(priv->chan); +} + +static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + + dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, + priv->dma_dir); + + uniphier_sd_dma_endisable(host, 0); + + tmio_mmc_do_data_irq(host); +} + +static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = { + .start = uniphier_sd_external_dma_start, + .enable = uniphier_sd_external_dma_enable, + .request = uniphier_sd_external_dma_request, + .release = uniphier_sd_external_dma_release, + .abort = uniphier_sd_external_dma_abort, + .dataend = uniphier_sd_external_dma_dataend, +}; + +static void uniphier_sd_internal_dma_issue(unsigned long arg) +{ + struct tmio_mmc_host *host = (void *)arg; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); + spin_unlock_irqrestore(&host->lock, flags); + + uniphier_sd_dma_endisable(host, 1); + writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL); +} + +static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host, + struct mmc_data *data) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + struct scatterlist *sg = host->sg_ptr; + dma_addr_t dma_addr; + unsigned int dma_mode_dir; + u32 dma_mode; + int sg_len; + + if (WARN_ON(host->sg_len != 1)) + goto force_pio; + + if (!IS_ALIGNED(sg->offset, 8)) + goto force_pio; + + if (data->flags & MMC_DATA_READ) { + priv->dma_dir = DMA_FROM_DEVICE; + dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV; + } else { + priv->dma_dir = DMA_TO_DEVICE; + dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV; + } + + sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir); + if (sg_len == 0) + goto force_pio; + + dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir); + dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK, + UNIPHIER_SD_DMA_MODE_WIDTH_64); + dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC; + + writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE); + + dma_addr = sg_dma_address(data->sg); + writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L); + writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H); + + return; +force_pio: + host->force_pio = true; + uniphier_sd_dma_endisable(host, 0); +} + +static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host, + bool enable) +{ +} + +static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host, + struct tmio_mmc_data *pdata) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + + /* + * Due to a hardware bug, Pro5 cannot use DMA for RX. + * We can still use DMA for TX, but PIO for RX. + */ + if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX)) + host->chan_rx = (void *)0xdeadbeaf; + + host->chan_tx = (void *)0xdeadbeaf; + + tasklet_init(&host->dma_issue, uniphier_sd_internal_dma_issue, + (unsigned long)host); +} + +static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host) +{ + /* Each value is set to zero to assume "disabling" each DMA */ + host->chan_rx = NULL; + host->chan_tx = NULL; +} + +static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host) +{ + u32 tmp; + + uniphier_sd_dma_endisable(host, 0); + + tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST); + tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0); + writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST); + + tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0; + writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST); +} + +static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + + uniphier_sd_dma_endisable(host, 0); + dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir); + + tmio_mmc_do_data_irq(host); +} + +static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = { + .start = uniphier_sd_internal_dma_start, + .enable = uniphier_sd_internal_dma_enable, + .request = uniphier_sd_internal_dma_request, + .release = uniphier_sd_internal_dma_release, + .abort = uniphier_sd_internal_dma_abort, + .dataend = uniphier_sd_internal_dma_dataend, +}; + +static int uniphier_sd_clk_enable(struct tmio_mmc_host *host) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + struct mmc_host *mmc = host->mmc; + int ret; + + ret = clk_prepare_enable(priv->clk); + if (ret) + return ret; + + ret = clk_set_rate(priv->clk, ULONG_MAX); + if (ret) + goto disable_clk; + + priv->clk_rate = clk_get_rate(priv->clk); + + /* If max-frequency property is set, use it. */ + if (!mmc->f_max) + mmc->f_max = priv->clk_rate; + + /* + * 1/512 is the finest divisor in the original IP. Newer versions + * also supports 1/1024 divisor. (UniPhier-specific extension) + */ + if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) + mmc->f_min = priv->clk_rate / 1024; + else + mmc->f_min = priv->clk_rate / 512; + + ret = reset_control_deassert(priv->rst); + if (ret) + goto disable_clk; + + ret = reset_control_deassert(priv->rst_br); + if (ret) + goto assert_rst; + + return 0; + +assert_rst: + reset_control_assert(priv->rst); +disable_clk: + clk_disable_unprepare(priv->clk); + + return ret; +} + +static void uniphier_sd_clk_disable(struct tmio_mmc_host *host) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + + reset_control_assert(priv->rst_br); + reset_control_assert(priv->rst); + clk_disable_unprepare(priv->clk); +} + +static void uniphier_sd_hw_reset(struct tmio_mmc_host *host) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + + reset_control_assert(priv->rst_hw); + /* For eMMC, minimum is 1us but give it 9us for good measure */ + udelay(9); + reset_control_deassert(priv->rst_hw); + /* For eMMC, minimum is 200us but give it 300us for good measure */ + usleep_range(300, 1000); +} + +static void uniphier_sd_set_clock(struct tmio_mmc_host *host, + unsigned int clock) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + unsigned long divisor; + u32 tmp; + + tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); + + /* stop the clock before changing its rate to avoid a glitch signal */ + tmp &= ~CLK_CTL_SCLKEN; + writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); + + if (clock == 0) + return; + + tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024; + tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1; + tmp &= ~CLK_CTL_DIV_MASK; + + divisor = priv->clk_rate / clock; + + /* + * In the original IP, bit[7:0] represents the divisor. + * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 + * + * The IP does not define a way to achieve 1/1. For UniPhier variants, + * bit10 is used for 1/1. Newer versions of UniPhier variants use + * bit16 for 1/1024. + */ + if (divisor <= 1) + tmp |= UNIPHIER_SD_CLK_CTL_DIV1; + else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512) + tmp |= UNIPHIER_SD_CLK_CTL_DIV1024; + else + tmp |= roundup_pow_of_two(divisor) >> 2; + + writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); + + tmp |= CLK_CTL_SCLKEN; + writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); +} + +static void uniphier_sd_host_init(struct tmio_mmc_host *host) +{ + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + u32 val; + + /* + * Connected to 32bit AXI. + * This register holds settings for SoC-specific internal bus + * connection. What is worse, the register spec was changed, + * breaking the backward compatibility. Write an appropriate + * value depending on a flag associated with a compatible string. + */ + if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) + val = 0x00000101; + else + val = 0x00000000; + + writel(val, host->ctl + UNIPHIER_SD_HOST_MODE); + + val = 0; + /* + * If supported, the controller can automatically + * enable/disable the clock line to the card. + */ + if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) + val |= UNIPHIER_SD_CLKCTL_OFFEN; + + writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); +} + +static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct tmio_mmc_host *host = mmc_priv(mmc); + struct uniphier_sd_priv *priv = uniphier_sd_priv(host); + struct pinctrl_state *pinstate; + u32 val, tmp; + + switch (ios->signal_voltage) { + case MMC_SIGNAL_VOLTAGE_330: + val = UNIPHIER_SD_VOLT_330; + pinstate = priv->pinstate_default; + break; + case MMC_SIGNAL_VOLTAGE_180: + val = UNIPHIER_SD_VOLT_180; + pinstate = priv->pinstate_uhs; + break; + default: + return -ENOTSUPP; + } + + tmp = readl(host->ctl + UNIPHIER_SD_VOLT); + tmp &= ~UNIPHIER_SD_VOLT_MASK; + tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val); + writel(tmp, host->ctl + UNIPHIER_SD_VOLT); + + pinctrl_select_state(priv->pinctrl, pinstate); + + return 0; +} + +static int uniphier_sd_uhs_init(struct tmio_mmc_host *host, + struct uniphier_sd_priv *priv) +{ + priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc)); + if (IS_ERR(priv->pinctrl)) + return PTR_ERR(priv->pinctrl); + + priv->pinstate_default = pinctrl_lookup_state(priv->pinctrl, + PINCTRL_STATE_DEFAULT); + if (IS_ERR(priv->pinstate_default)) + return PTR_ERR(priv->pinstate_default); + + priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs"); + if (IS_ERR(priv->pinstate_uhs)) + return PTR_ERR(priv->pinstate_uhs); + + host->ops.start_signal_voltage_switch = + uniphier_sd_start_signal_voltage_switch; + + return 0; +} + +static int uniphier_sd_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct uniphier_sd_priv *priv; + struct tmio_mmc_data *tmio_data; + struct tmio_mmc_host *host; + int irq, ret; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "failed to get IRQ number"); + return irq; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->caps = (unsigned long)of_device_get_match_data(dev); + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get clock\n"); + return PTR_ERR(priv->clk); + } + + priv->rst = devm_reset_control_get_shared(dev, "host"); + if (IS_ERR(priv->rst)) { + dev_err(dev, "failed to get host reset\n"); + return PTR_ERR(priv->rst); + } + + /* old version has one more reset */ + if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) { + priv->rst_br = devm_reset_control_get_shared(dev, "bridge"); + if (IS_ERR(priv->rst_br)) { + dev_err(dev, "failed to get bridge reset\n"); + return PTR_ERR(priv->rst_br); + } + } + + tmio_data = &priv->tmio_data; + tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT; + + host = tmio_mmc_host_alloc(pdev, tmio_data); + if (IS_ERR(host)) + return PTR_ERR(host); + + if (host->mmc->caps & MMC_CAP_HW_RESET) { + priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw"); + if (IS_ERR(priv->rst_hw)) { + dev_err(dev, "failed to get hw reset\n"); + ret = PTR_ERR(priv->rst_hw); + goto free_host; + } + host->hw_reset = uniphier_sd_hw_reset; + } + + if (host->mmc->caps & MMC_CAP_UHS) { + ret = uniphier_sd_uhs_init(host, priv); + if (ret) { + dev_warn(dev, + "failed to setup UHS (error %d). Disabling UHS.", + ret); + host->mmc->caps &= ~MMC_CAP_UHS; + } + } + + ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED, + dev_name(dev), host); + if (ret) + goto free_host; + + if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) + host->dma_ops = &uniphier_sd_internal_dma_ops; + else + host->dma_ops = &uniphier_sd_external_dma_ops; + + host->bus_shift = 1; + host->clk_enable = uniphier_sd_clk_enable; + host->clk_disable = uniphier_sd_clk_disable; + host->set_clock = uniphier_sd_set_clock; + + ret = uniphier_sd_clk_enable(host); + if (ret) + goto free_host; + + uniphier_sd_host_init(host); + + tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; + if (host->mmc->caps & MMC_CAP_UHS) + tmio_data->ocr_mask |= MMC_VDD_165_195; + + tmio_data->max_segs = 1; + tmio_data->max_blk_count = U16_MAX; + + ret = tmio_mmc_host_probe(host); + if (ret) + goto free_host; + + return 0; + +free_host: + tmio_mmc_host_free(host); + + return ret; +} + +static int uniphier_sd_remove(struct platform_device *pdev) +{ + struct tmio_mmc_host *host = platform_get_drvdata(pdev); + + tmio_mmc_host_remove(host); + uniphier_sd_clk_disable(host); + + return 0; +} + +static const struct of_device_id uniphier_sd_match[] = { + { + .compatible = "socionext,uniphier-sd-v2.91", + }, + { + .compatible = "socionext,uniphier-sd-v3.1", + .data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP | + UNIPHIER_SD_CAP_BROKEN_DMA_RX), + }, + { + .compatible = "socionext,uniphier-sd-v3.1.1", + .data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, uniphier_sd_match); + +static struct platform_driver uniphier_sd_driver = { + .probe = uniphier_sd_probe, + .remove = uniphier_sd_remove, + .driver = { + .name = "uniphier-sd", + .of_match_table = uniphier_sd_match, + }, +}; +module_platform_driver(uniphier_sd_driver); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver"); +MODULE_LICENSE("GPL v2"); From patchwork Thu Aug 16 07:16:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 144323 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1729537ljj; Thu, 16 Aug 2018 00:17:51 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzzDcIA4cSJhBp3YqEtn6w7sePG8LNxT4vXwqIRo9z1BrNljx3lqjdpiPZNC5m8Kjywxxai X-Received: by 2002:a17:902:8541:: with SMTP id d1-v6mr28132509plo.81.1534403871562; Thu, 16 Aug 2018 00:17:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534403871; cv=none; d=google.com; s=arc-20160816; b=Jp8TpU4KltCl4MIGCCpTDnxMDM4hXhZx6BLgiCl0/G2F8X3prurV9sv08NeQOuKZak YKPR6HHdk+4yrBBUCZPsfy00OEikI6vDUojkewcA0oiYC1Qv0vCKGaB5gA55bPspsQ6a UVMoLu1t4XcQxlqtx6VpFmPxboKkZWEMYmQGezgE2bium+MJ9GYIsTxbp26CklHgTHCp WHKGQEcvN3mPLofXulkNbWKI5Puw41sdH4+f2Ha+UDCArTBYyYaZMZduOwCiBEi2Ngwu PaLo4cgqR+iACvnJnlrFGXrXFo+AFVTTU6yAAkreSf0J5Pfxyf9wpSQlZ1u3eRABCncr D0nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=1THgspRs7J/CvA6Et2CW6NHJzt0aZosTZKkkdPhTrGM=; b=RKkqAgDLNHb+oWmnyQj7KuOzrQ0aksfdxu9CwcFV9lbcttiixbAzizjbW9+a2H7Qxc Yx5/4ybQsN4Rj8oYoBCMoeoFfs8rpdCW7LNri7HIunRA1CfALd1jvjeCn4Hpa/C3GV3E 6OzoRLNa286e8q+VyWEbIELwoauOgB7q6/Asudyhrf5ewEw5JD2Yi1tg8+vj664Ho7w6 WooKl3Oj+7itpxfWkIb/SlasKvc3ElTZow+uWlEe4gr1b3w6knFKywL8IT0r/JZafmz9 EhqxQMEFiaWIDwfJp//SYyjt52yChzy5qjaa36+VffQU4+PWbIpTa3MXM79IGFc3oZTB lyog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=cQvIca4v; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f12-v6si24878828pgm.601.2018.08.16.00.17.51; Thu, 16 Aug 2018 00:17:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=cQvIca4v; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389280AbeHPKOQ (ORCPT + 5 others); Thu, 16 Aug 2018 06:14:16 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:17415 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389276AbeHPKOQ (ORCPT ); Thu, 16 Aug 2018 06:14:16 -0400 Received: from grover.tkatk1.zaq.ne.jp (zaqdadce369.zaq.ne.jp [218.220.227.105]) (authenticated) by conuserg-09.nifty.com with ESMTP id w7G7Gu2L008336; Thu, 16 Aug 2018 16:17:00 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com w7G7Gu2L008336 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1534403821; bh=1THgspRs7J/CvA6Et2CW6NHJzt0aZosTZKkkdPhTrGM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cQvIca4v7hwpQVxEnHCMZDWV4G28jhe1CUW1iT9HMCuVrbSXsZfZN4zzoVEmhj7/q YXSq1TID0vNdkCUqeninQA2UGdyZNLQjahpl6j1MVHo2nNpo1kJPgzYEwRuEaRpbFa c2MDOvZE0d3AvBFxG+E0HoOVQrjsh3RI1bC/Zdje3tgJwN/XyNiPSHoAyNRA5Vvo+W 9x5Vat/lk6qbR/pMPPM/yr10eeyvmAmpHCzRMGJ8gf61m4gLdqaCLJL/M7brfn0Jv/ gVaTYNvZ74tnlT0sGLl0E6Im6aOdqbIvOUixpuzzY5M17QWf5/ChwyvKAWNT162ePc b4oKF+j6RLH3Q== X-Nifty-SrcIP: [218.220.227.105] From: Masahiro Yamada To: linux-mmc@vger.kernel.org, Wolfram Sang Cc: Masami Hiramatsu , Jassi Brar , Ulf Hansson , linux-renesas-soc@vger.kernel.org, Masahiro Yamada Subject: [PATCH v2 5/7] mmc: renesas_sdhi: merge clk_{start, stop} functions to set_clock Date: Thu, 16 Aug 2018 16:16:37 +0900 Message-Id: <1534403799-10594-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> References: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org renesas_sdhi_clk_start() and renesas_sdhi_clk_stop() are now only called from renesas_sdhi_set_clock(). Merge them. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mmc/host/renesas_sdhi_core.c | 39 +++++++++++------------------------- 1 file changed, 12 insertions(+), 27 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index 1f4c82e..a15fb2e 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -155,35 +155,16 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, return ret == 0 ? best_freq : clk_get_rate(priv->clk); } -static void renesas_sdhi_clk_start(struct tmio_mmc_host *host) -{ - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - /* HW engineers overrode docs: no sleep needed on R-Car2+ */ - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - usleep_range(10000, 11000); -} - -static void renesas_sdhi_clk_stop(struct tmio_mmc_host *host) -{ - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - /* HW engineers overrode docs: no sleep needed on R-Car2+ */ - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - usleep_range(10000, 11000); -} - static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, unsigned int new_clock) { u32 clk = 0, clock; - if (new_clock == 0) { - renesas_sdhi_clk_stop(host); - return; - } + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + if (new_clock == 0) + goto out; clock = renesas_sdhi_clk_update(host, new_clock) / 512; @@ -194,13 +175,17 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) clk |= 0xff; - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) usleep_range(10000, 11000); - renesas_sdhi_clk_start(host); + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + +out: + /* HW engineers overrode docs: no sleep needed on R-Car2+ */ + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) + usleep_range(10000, 11000); } static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) From patchwork Thu Aug 16 07:16:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 144321 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1729514ljj; Thu, 16 Aug 2018 00:17:50 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyp0Npb5ujsho9h9hV/Sx6sljiL3MGkZ/dpoiM+ZFmW+C6kRjfEwUCrFAK/WWU/C5VdAHSd X-Received: by 2002:a63:d20e:: with SMTP id a14-v6mr27898523pgg.226.1534403869975; Thu, 16 Aug 2018 00:17:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534403869; cv=none; d=google.com; s=arc-20160816; b=U3UwaYWxdskEMpczdY/X6C+u9GA5nyS1iAIpyq+Rzf1SAhqTWrx5NJRNW/whvipEoI GAkWfjyyhjClDZ6fkR/Heh/Kq+htrzbwAp/Uuew5bysB9OGFPyvFQTjvDygSM+j3DZYp 3npTp/xlsMyQfdx4Jn+8gAXlqaLEhsNY24wJC3PWfF+OPbQjZjUaljuf1rwTY333F7av mQ19W9RoRBuclPdqavrasJQMBaqq6+3v+I3nB7q9ocKQ8d7JdkkWrMpzzCXLy6qSYE7u Xi9nAIXDMlRbkCgv7ySXE3uk3rd6twfILWbv4SpUwdmj81fLZPkTCGw+TvfGP0AGJKBF oBmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=dZTlH7sBCcuqFoGzvHUAD435gAWPXVV9fA5VEQ/IoJk=; b=du5X/Ny9IV8cqyWQZGZ1K2EyuCoTLVpmWNiP2NgBR9VCwDojJMN9jEdHVFOwKMATqT 2C3KXn9QMkGGK1YQPpKYO1nidltzVZP1hCR9MaCg1k4XMiO3xVCt/zBVw+X5yDJEDpxX PgI3JgMEacVY30ZHk31pwR9UG7glPg1QdR4cRiUFtRQ7w/aOkhoe95f191hejtU475Su BHcmZ//iwT6BbuYSStBW92CTL5OGR2onSxNBwKTQ4NXOJlcLAzl3Omt3Pd2Zej4fmGPc B24FIV2Y35fwiCbbytOURpXdGE+wbXwW9dJJHc8cUpw89E/6PhZfceLEO2pnIXNItmLt 5vjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=2GYSYrXx; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f12-v6si24878828pgm.601.2018.08.16.00.17.49; Thu, 16 Aug 2018 00:17:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=2GYSYrXx; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389278AbeHPKOP (ORCPT + 5 others); Thu, 16 Aug 2018 06:14:15 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:17394 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389265AbeHPKOP (ORCPT ); Thu, 16 Aug 2018 06:14:15 -0400 Received: from grover.tkatk1.zaq.ne.jp (zaqdadce369.zaq.ne.jp [218.220.227.105]) (authenticated) by conuserg-09.nifty.com with ESMTP id w7G7Gu2M008336; Thu, 16 Aug 2018 16:17:01 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com w7G7Gu2M008336 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1534403822; bh=dZTlH7sBCcuqFoGzvHUAD435gAWPXVV9fA5VEQ/IoJk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=2GYSYrXxDR3t0Mhfe3/pmvL7WJTfFkRJU4+suVIUESv0pqyxKqVNRHT+IjE64dpja 1dYxj88/Niso07iWIbMiZ98WmalcpbM39S3l02oF7UIk/PDD/uki3yrH9FtrE7REai eEiRt96Psv53nw8pFxOMGZzGlKpgiGewLHXnQNHmeOmXdm1nNQIE3X68jIf/lYapsX VnPoSjD3xDSi/PxfM/Ia5gOQ2qcBftSzjlGCeN0uu/g94hfkkG4tj2CNzRsX4gsnaC GOMoy+Ob3CdHjblhwHb3IKI90tdvxcc8W9W1Zl5eby4FBKXFLrFYGxwSqyB7wD7k8S HzbwAHj/vshIg== X-Nifty-SrcIP: [218.220.227.105] From: Masahiro Yamada To: linux-mmc@vger.kernel.org, Wolfram Sang Cc: Masami Hiramatsu , Jassi Brar , Ulf Hansson , linux-renesas-soc@vger.kernel.org, Masahiro Yamada Subject: [PATCH v2 6/7] mmc: renesas_sdhi: refactor CLK_CTL bit calculation Date: Thu, 16 Aug 2018 16:16:38 +0900 Message-Id: <1534403799-10594-7-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> References: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) clock <<= 1; ... is too tricky, hence I replaced with roundup_pow_of_two(divisor) >> 2 '(clk >> 22) & 0x1' is the bit test for the 1/1 divisor, but it is not clear. 'divisor <= 1' is easier to understand. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mmc/host/renesas_sdhi_core.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index a15fb2e..98391e9 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -158,7 +158,8 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, unsigned int new_clock) { - u32 clk = 0, clock; + unsigned int clock, divisor; + u32 clk = 0; sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); @@ -166,14 +167,18 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, if (new_clock == 0) goto out; - clock = renesas_sdhi_clk_update(host, new_clock) / 512; + clock = renesas_sdhi_clk_update(host, new_clock); - for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) - clock <<= 1; + divisor = clock / new_clock; - /* 1/1 clock is option */ - if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) - clk |= 0xff; + /* + * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 + * all bits set: 1/1 (Renesas-specific extension?) + */ + if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && divisor <= 1) + clk = 0xff; + else + clk = roundup_pow_of_two(divisor) >> 2; sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) From patchwork Thu Aug 16 07:16:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 144322 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1729525ljj; Thu, 16 Aug 2018 00:17:50 -0700 (PDT) X-Google-Smtp-Source: AA+uWPwjgTCfCEUN3TH0snFWElVq/PkiyOXjh1A2WK63XSdVv2owPGu+4clP8JGmg9tA2zbYGnOB X-Received: by 2002:a17:902:7793:: with SMTP id o19-v6mr28185336pll.306.1534403870658; Thu, 16 Aug 2018 00:17:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534403870; cv=none; d=google.com; s=arc-20160816; b=hrjcepS83IyuD8431SKKPveXT3z8sC5Q3V5824Yr+Xdxf7zCmdA/GJrKLkS4mzwhaf gLattJCfEYyNjNfK1fSgGroDfb3uUrZE0Z0m8cqZhaph2hqKkDlBAwaYnJ/xBgnxTZAw PgFOC1QkXZsFfbraH4VDzW6N5KgdQrl2s/Cl1iLIENdFOGe3qfR36nSvUatJ+jLnQS7b JOOYRFqxmc4qFYm4IfwgkR18FdHHuYnCMMeuDWLzP88eIOqj/XdV0kTXV1bcCGyLuqJ4 luWrvA+ZkjuqmeFLnmc02z2++ZSEnSlW/96SgnDxEHnbSeb/YzbR1QEa3FkkPp+ApzU7 cMOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=Yzpwtd3BlQ9HcQbHX4J5Wqq0RNmvS0W30hL7Io/DvEE=; b=vC7QJ4f49KHaKDUcMKj7Uvqhj5UQ1bHwdIHSYe3Qxc/iiXNI468YQ5aUmC35eOxNOA iPqShuQnPnqH/xFhH4trkzxU7ph9lui7Mf71dVk7afMnn93qV/QlZuPJocsFEC22tv9C /kGG3nMsq2SCiN0RsO3ewSTH+FKjTeCDyQd9RSsXaWf4sbv9+jW610Z3aw+ZRY0FWQfj x9BBYqJ0mmbiyp7HcVJS8X3eGZi/TRX2wxzE/eutZSi5kgD3Ps8FlitS/vXPXUJK0IcK Ll4VxHMOOGe/l0+F1ylftixMuhoFMm1Q2hXbdrWh/PfxpKyvXHEc7ALhE4oolvRSU2V2 kcXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=sHR03fT0; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f12-v6si24878828pgm.601.2018.08.16.00.17.50; Thu, 16 Aug 2018 00:17:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=sHR03fT0; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389279AbeHPKOQ (ORCPT + 5 others); Thu, 16 Aug 2018 06:14:16 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:17406 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389275AbeHPKOP (ORCPT ); Thu, 16 Aug 2018 06:14:15 -0400 Received: from grover.tkatk1.zaq.ne.jp (zaqdadce369.zaq.ne.jp [218.220.227.105]) (authenticated) by conuserg-09.nifty.com with ESMTP id w7G7Gu2N008336; Thu, 16 Aug 2018 16:17:02 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com w7G7Gu2N008336 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1534403822; bh=Yzpwtd3BlQ9HcQbHX4J5Wqq0RNmvS0W30hL7Io/DvEE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sHR03fT0j4Qg1LvMOcw36yE0ivSm/ZzTUIckcwPjBsKt2KPG9hZ0+7/hpyNPWRXh2 GXODYuDOIzQlSxSnfGNi7gMpjsz1lNWDKIczN029Fmvy1MqySnLbfv4jRV+Bzwdky+ HkzzUaov0ja7nMos2fKjvARja8XsFvnhXx2xip6ONCrl0yWiLVpB/7HS1HrkFjUv+u 9ARRz1si8j+PixeeOioOLKc3/ogN6ghDH6lAcbNp+xGUmG8kaOR2O/nfAAcR0KIlrn iqDDryxqglQ4CLjTIQqswQQDME5d2/jpcJLPxiBagDu49hyN7I0YI2EtREdRe/3y8Z 9sv+qZSdYdziA== X-Nifty-SrcIP: [218.220.227.105] From: Masahiro Yamada To: linux-mmc@vger.kernel.org, Wolfram Sang Cc: Masami Hiramatsu , Jassi Brar , Ulf Hansson , linux-renesas-soc@vger.kernel.org, Masahiro Yamada Subject: [PATCH v2 7/7] mmc: tmio: refactor CLK_CTL bit calculation Date: Thu, 16 Aug 2018 16:16:39 +0900 Message-Id: <1534403799-10594-8-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> References: <1534403799-10594-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) clock <<= 1; ... is too tricky, hence I replaced with roundup_pow_of_two(divisor) >> 2 '(clk >> 22) & 0x1' is the bit test for the 1/1 divisor, but it is not clear. 'divisor <= 1' is easier to understand. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mmc/host/tmio_mmc.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c index b031a77..e04c322 100644 --- a/drivers/mmc/host/tmio_mmc.c +++ b/drivers/mmc/host/tmio_mmc.c @@ -48,19 +48,27 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) static void tmio_mmc_set_clock(struct tmio_mmc_host *host, unsigned int new_clock) { - u32 clk = 0, clock; + unsigned int clock, divisor; + u32 clk = 0; + int clk_sel; if (new_clock == 0) { tmio_mmc_clk_stop(host); return; } - clock = host->mmc->f_min; + divisor = host->pdata->hclk / new_clock; - for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) - clock <<= 1; + if (divisor <= 1) { + clk_sel = 1; + clk = 0; + } else { + clk_sel = 0; + /* bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 */ + clk = roundup_pow_of_two(divisor) >> 2; + } - host->pdata->set_clk_div(host->pdev, (clk >> 22) & 1); + host->pdata->set_clk_div(host->pdev, clk_sel); sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));