From patchwork Fri Jul 2 10:40:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 469505 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1251094jao; Fri, 2 Jul 2021 03:40:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwsqTbOkPh4mf/gsgV0SsbhqFGRqGotG+2ftQdyDZaBB1jEHwfLVJkSLliwaSIt6K2QRhyG X-Received: by 2002:a05:6102:409:: with SMTP id d9mr5174259vsq.48.1625222448951; Fri, 02 Jul 2021 03:40:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625222448; cv=none; d=google.com; s=arc-20160816; b=onb8L6N3MhJwEXdSq8RlvmU5W3/0vPjxkKPewmI9703/Z2gRvHrYN6t60/9tYz9hhg LcVb8BrEA4vJiP6RNg2Vzk6EmIMnC7aFv9eAZCsP2rqOIBxqCDOUpJYcggmlY08drICq 78lpLNRUX15oRgjN+lhoCMtMaGO9Ia9v0GYN5kPhMyVKvhurVnio9vn8zZJRCvihs3bd h4VBuE3T6e1kdMWpqSxMYu2D9gy0HOsZUfNg068FdVPEf3rZsevD6Gu4QPCl7sPmYVX2 byf4QT04MwyNf7Pg564AbbznAN5kps+/LHb0fSV5q72Z05jUjbtH+mUicYSEgSeYJi7G wj+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hMxqgRMRaEeAuAomNzQfVfuioKmuSQPXmbHQvftFpp4=; b=WiebY+I88KUo9FJ7RRKg9qGBEDlO4o65Y+3A9/1zxmCr7EcGf1I0yXn1YXjd/zMKNa y86du+4FFD3fp0upevrgdOSMRs0tCXmupoBMS3ZziGxmR7hdicyvYrW08TThQ45hczG3 hlzAr8aWxYhmqFAhH8S18Y203zDtM14LCdIpW9xOJn2nsIBX6mvb8p+lq+Z9YlWA/wkM D9ZPSYertE70gbcCazJrwAVVgWaAMI+2Z0iOGO/tp3KuCOXZu+VdJCA/K5ZFZmksyccn 4ksha5cqYSRlnl8mIKWkwJ806ptPRiiYhTTUoKsQOoSlNBR8wCqEHJ4s5wwP+usaDYly lqig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=glOzzCDp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 94si2346319uac.93.2021.07.02.03.40.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 02 Jul 2021 03:40:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=glOzzCDp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lzGbI-0004cr-AT for patch@linaro.org; Fri, 02 Jul 2021 06:40:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lzGav-0004aw-Hg for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:25 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:43609) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lzGat-0006YK-Cz for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:24 -0400 Received: by mail-wm1-x32f.google.com with SMTP id q18-20020a1ce9120000b02901f259f3a250so6054625wmc.2 for ; Fri, 02 Jul 2021 03:40:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hMxqgRMRaEeAuAomNzQfVfuioKmuSQPXmbHQvftFpp4=; b=glOzzCDpuBPmTjQb5ZHwS0fOGxVVg4IovFuV0otzdc5FAwLn3JNAEZfp4bBWi9FV1m D7SHC0qoVvS955HPIl+ZQeoHbGVSheVpetyPyU34RnkENNqcI4pvh9RVknh2r4GWho0A sUtdHGtwhevjXBeWSBQSfqYk6RUACkiukpwkvNqVyGjuSm6ppBE72b4vBHbblBr6ikYy ModlY6X9ahXFv+CX/PaQ8Sz8QifMdq3DLGq0yJ1z0l6DSe0c2U/YmqEB0amzeQMfO6+2 xO7to8Kh/LqcabtyQrn0P2opQ0sEQCfRcnI+aq9GVIiLMDfpkvsI1Y+7/HtvUB5BVdUv bHiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hMxqgRMRaEeAuAomNzQfVfuioKmuSQPXmbHQvftFpp4=; b=idtZ4VmoroddiPH8ECjXcrSkkYpEaoxBMfJct849DMkyuGwnxfojV0UgQt/sYQrTml KV++AgvTYbbqicYofC3R+EKakFxHKGSbvwxIkFvFUW1/zGS/wu5B1Uq0ytim8DfML2g/ 9a4KEVf6vebgMhDLokRclib425UJGExSJ2YP+NguhPv/IqUwLvkDoH8Mh+5WmdBNo36X 3u+Kr2NxvHW4c5o4sV9AvUov76iBuNSbVH3+U13SZq6WI9ROImDZqtHQSSq/Q+90XsXd a80fblb9524dCCvY4SjdiqMVG1KfwFSRroK4rl62V213UrkjjuzOAICkAPTSagR+9GXv /3RQ== X-Gm-Message-State: AOAM530dITjxpT/bAkUf1ZnAOqUzcYosEFTvfZWiA+U2u4D/YMVYo62V e/bNGXVPdVw0rdwHMa7oYLDjAg== X-Received: by 2002:a7b:cb91:: with SMTP id m17mr15561780wmi.26.1625222421543; Fri, 02 Jul 2021 03:40:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/11] hw/gpio/gpio_pwr: use shutdown function for reboot Date: Fri, 2 Jul 2021 11:40:08 +0100 Message-Id: <20210702104018.19881-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Maxim Uvarov qemu has 2 type of functions: shutdown and reboot. Shutdown function has to be used for machine shutdown. Otherwise we cause a reset with a bogus "cause" value, when we intended a shutdown. Signed-off-by: Maxim Uvarov Reviewed-by: Peter Maydell Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org [PMM: tweaked commit message] Signed-off-by: Peter Maydell --- hw/gpio/gpio_pwr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c index 7714fa0dc4d..dbaf1c70c88 100644 --- a/hw/gpio/gpio_pwr.c +++ b/hw/gpio/gpio_pwr.c @@ -43,7 +43,7 @@ static void gpio_pwr_reset(void *opaque, int n, int level) static void gpio_pwr_shutdown(void *opaque, int n, int level) { if (level) { - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); } } From patchwork Fri Jul 2 10:40:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 469506 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1251405jao; Fri, 2 Jul 2021 03:41:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxno+z+qM0D3A3UXrcBu0QTxDREfiPpigbez7pGO6js+wGQo5OlTNAkDHOVJNuE2HW4bLfu X-Received: by 2002:a67:c786:: with SMTP id t6mr5791964vsk.40.1625222476810; Fri, 02 Jul 2021 03:41:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625222476; cv=none; d=google.com; s=arc-20160816; b=zCpTzDAoEAylYPbb8UiEqCL2kGxleDmDOhpyqb4LrEIpoeyLOuOMLLs/44EbF677we +AVn6QSmddZkvTl9eeokuJIzMIbp9l8d2JOlG7eVE88aLpXGdNv/PHZeB9pgmWZ+BIXp 42qyfeldortom8odDF4SurHCnCcEB9SLLrWul8M7B20RolGDzWGUmm42FTE4haIxRNks sxUwLQcguFi8GA4OM4CJ+TjjgZKTvHE2zsVs/M2Z41FoJRphLKi0Uk95QWpnNLgBW27+ EwLDWAuz23qWrn6/ZQ+ggO1D947R+p5aakrIwZHYwyNXWs0RdijDrl5cwlpanqZA944w MX1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cyVR+RM9P0Fu8J9agxc+syCsAuN2LmIMWIgCF4vgRTg=; b=wiDS45tdyrYM8v4r9Ayg+M/3r8ipCAdYe7z4me/ewNzDUGIUkxf+XVkNKXRceoooxV oOFbCfbBvtAm8Kvw7SZSVWDg1armXGxj/B+hJLPL5du2J5tuGiyyu+PRVxJGOTXSwjUC lfneuPGvmyisp9bAApztzf+Bxv3WYxImni2mlUzWW6rMP/hG4/AiKoSwKVRg4JVP7ZvU b9nXCHggCjTjR3bASjbwZ/reLzLq1+/Q6lIMC+LqPz243Rm4UjJ+7kg46aYgAO8XyJFJ QfQmNhBIDPUEmY60fKL8CLJxgxib0C5rY9Z8Lg8UFRblO1ZJd92peTHZ/y1K1vNw43zE VTXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sdDsSJM3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/11] hw/gpio/pl061: Convert DPRINTF to tracepoints Date: Fri, 2 Jul 2021 11:40:09 +0100 Message-Id: <20210702104018.19881-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the use of the DPRINTF debug macro in the PL061 model to use tracepoints. Signed-off-by: Peter Maydell --- hw/gpio/pl061.c | 27 +++++++++------------------ hw/gpio/trace-events | 6 ++++++ 2 files changed, 15 insertions(+), 18 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index e72e77572a0..a6ace88895d 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -15,19 +15,7 @@ #include "qemu/log.h" #include "qemu/module.h" #include "qom/object.h" - -//#define DEBUG_PL061 1 - -#ifdef DEBUG_PL061 -#define DPRINTF(fmt, ...) \ -do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) -#define BADF(fmt, ...) \ -do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) -#else -#define DPRINTF(fmt, ...) do {} while(0) -#define BADF(fmt, ...) \ -do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) -#endif +#include "trace.h" static const uint8_t pl061_id[12] = { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; @@ -107,7 +95,7 @@ static void pl061_update(PL061State *s) uint8_t out; int i; - DPRINTF("dir = %d, data = %d\n", s->dir, s->data); + trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data); /* Outputs float high. */ /* FIXME: This is board dependent. */ @@ -118,8 +106,9 @@ static void pl061_update(PL061State *s) for (i = 0; i < N_GPIOS; i++) { mask = 1 << i; if (changed & mask) { - DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); - qemu_set_irq(s->out[i], (out & mask) != 0); + int level = (out & mask) != 0; + trace_pl061_set_output(DEVICE(s)->canonical_path, i, level); + qemu_set_irq(s->out[i], level); } } } @@ -131,7 +120,8 @@ static void pl061_update(PL061State *s) for (i = 0; i < N_GPIOS; i++) { mask = 1 << i; if (changed & mask) { - DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0); + trace_pl061_input_change(DEVICE(s)->canonical_path, i, + (s->data & mask) != 0); if (!(s->isense & mask)) { /* Edge interrupt */ @@ -150,7 +140,8 @@ static void pl061_update(PL061State *s) /* Level interrupt */ s->istate |= ~(s->data ^ s->iev) & s->isense; - DPRINTF("istate = %02X\n", s->istate); + trace_pl061_update_istate(DEVICE(s)->canonical_path, + s->istate, s->im, (s->istate & s->im) != 0); qemu_set_irq(s->irq, (s->istate & s->im) != 0); } diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index f0b664158e2..48ccbb183cc 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -13,6 +13,12 @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 +# pl061.c +pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x" +pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d" +pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d" +pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" + # sifive_gpio.c sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 From patchwork Fri Jul 2 10:40:10 2021 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/11] hw/gpio/pl061: Clean up read/write offset handling logic Date: Fri, 2 Jul 2021 11:40:10 +0100 Message-Id: <20210702104018.19881-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the pl061_read() and pl061_write() functions handle offsets using a combination of three if() statements and a switch(). Clean this up to use just a switch, using case ranges. This requires that instead of catching accesses to the luminary-only registers on a stock PL061 via a check on s->rsvd_start we use an "is this luminary?" check in the cases for each luminary-only register. Signed-off-by: Peter Maydell --- hw/gpio/pl061.c | 106 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 81 insertions(+), 25 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index a6ace88895d..0f5d12e6d5a 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -55,7 +55,6 @@ struct PL061State { qemu_irq irq; qemu_irq out[N_GPIOS]; const unsigned char *id; - uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */ }; static const VMStateDescription vmstate_pl061 = { @@ -151,16 +150,9 @@ static uint64_t pl061_read(void *opaque, hwaddr offset, { PL061State *s = (PL061State *)opaque; - if (offset < 0x400) { - return s->data & (offset >> 2); - } - if (offset >= s->rsvd_start && offset <= 0xfcc) { - goto err_out; - } - if (offset >= 0xfd0 && offset < 0x1000) { - return s->id[(offset - 0xfd0) >> 2]; - } switch (offset) { + case 0x0 ... 0x3fc: /* Data */ + return s->data & (offset >> 2); case 0x400: /* Direction */ return s->dir; case 0x404: /* Interrupt sense */ @@ -178,33 +170,70 @@ static uint64_t pl061_read(void *opaque, hwaddr offset, case 0x420: /* Alternate function select */ return s->afsel; case 0x500: /* 2mA drive */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } return s->dr2r; case 0x504: /* 4mA drive */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } return s->dr4r; case 0x508: /* 8mA drive */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } return s->dr8r; case 0x50c: /* Open drain */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } return s->odr; case 0x510: /* Pull-up */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } return s->pur; case 0x514: /* Pull-down */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } return s->pdr; case 0x518: /* Slew rate control */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } return s->slr; case 0x51c: /* Digital enable */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } return s->den; case 0x520: /* Lock */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } return s->locked; case 0x524: /* Commit */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } return s->cr; case 0x528: /* Analog mode select */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } return s->amsel; + case 0x52c ... 0xfcc: /* Reserved */ + goto bad_offset; + case 0xfd0 ... 0xffc: /* ID registers */ + return s->id[(offset - 0xfd0) >> 2]; default: + bad_offset: + qemu_log_mask(LOG_GUEST_ERROR, + "pl061_read: Bad offset %x\n", (int)offset); break; } -err_out: - qemu_log_mask(LOG_GUEST_ERROR, - "pl061_read: Bad offset %x\n", (int)offset); return 0; } @@ -214,16 +243,12 @@ static void pl061_write(void *opaque, hwaddr offset, PL061State *s = (PL061State *)opaque; uint8_t mask; - if (offset < 0x400) { + switch (offset) { + case 0 ... 0x3fc: mask = (offset >> 2) & s->dir; s->data = (s->data & ~mask) | (value & mask); pl061_update(s); return; - } - if (offset >= s->rsvd_start) { - goto err_out; - } - switch (offset) { case 0x400: /* Direction */ s->dir = value & 0xff; break; @@ -247,47 +272,80 @@ static void pl061_write(void *opaque, hwaddr offset, s->afsel = (s->afsel & ~mask) | (value & mask); break; case 0x500: /* 2mA drive */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } s->dr2r = value & 0xff; break; case 0x504: /* 4mA drive */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } s->dr4r = value & 0xff; break; case 0x508: /* 8mA drive */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } s->dr8r = value & 0xff; break; case 0x50c: /* Open drain */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } s->odr = value & 0xff; break; case 0x510: /* Pull-up */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } s->pur = value & 0xff; break; case 0x514: /* Pull-down */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } s->pdr = value & 0xff; break; case 0x518: /* Slew rate control */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } s->slr = value & 0xff; break; case 0x51c: /* Digital enable */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } s->den = value & 0xff; break; case 0x520: /* Lock */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } s->locked = (value != 0xacce551); break; case 0x524: /* Commit */ + if (s->id != pl061_id_luminary) { + goto bad_offset; + } if (!s->locked) s->cr = value & 0xff; break; case 0x528: + if (s->id != pl061_id_luminary) { + goto bad_offset; + } s->amsel = value & 0xff; break; default: - goto err_out; + bad_offset: + qemu_log_mask(LOG_GUEST_ERROR, + "pl061_write: Bad offset %x\n", (int)offset); + return; } pl061_update(s); return; -err_out: - qemu_log_mask(LOG_GUEST_ERROR, - "pl061_write: Bad offset %x\n", (int)offset); } static void pl061_reset(DeviceState *dev) @@ -343,7 +401,6 @@ static void pl061_luminary_init(Object *obj) PL061State *s = PL061(obj); s->id = pl061_id_luminary; - s->rsvd_start = 0x52c; } static void pl061_init(Object *obj) @@ -353,7 +410,6 @@ static void pl061_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); s->id = pl061_id; - s->rsvd_start = 0x424; memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); sysbus_init_mmio(sbd, &s->iomem); From patchwork Fri Jul 2 10:40:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 469507 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1251868jao; Fri, 2 Jul 2021 03:41:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyIO+9tgdVCj5CYZTHrv3swNuYO07khYGOb2EMnoXwi7+y/F9wXUMSp/l2tGTBBdoU972XS X-Received: by 2002:a05:6130:384:: with SMTP id az4mr5804151uab.50.1625222518191; Fri, 02 Jul 2021 03:41:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625222518; cv=none; d=google.com; s=arc-20160816; b=B1GzwCskexe6NF/wRxXRTroRxqltVsI4tb9HpQSjEpL9VlIr79lHd7C8VtMm8/CsF0 PRU6HDVW+Xi3+g+FYtvYMjoUHN0/ceEYRSZbUHa5iBd4Nk7VlKlt8CdoDx6DCDDMyRMB yBZIh5QYn7dniuKHvjqUayAyFEb48qzB2F+fNhcum/Vu5rKbNV5+vkZwxr/uC+gxrxeI fhd3QDdnZVkFBUMPr+uyWJQ+2P/FHvecz+g2b71Zj/rRQ+XtHQcH9CcjZfdcrHRUEa0E bDR8Wnh7mclpO5EO6/oV9bCvaVYZJGiOcwts/690TrYrB8yJAQw1bg7febYXglppU+iL WNjA== ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/11] hw/gpio/pl061: Add tracepoints for register read and write Date: Fri, 2 Jul 2021 11:40:11 +0100 Message-Id: <20210702104018.19881-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add tracepoints for reads and writes to the PL061 registers. This requires restructuring pl061_read() to only return after the tracepoint, rather than having lots of early-returns. Signed-off-by: Peter Maydell --- hw/gpio/pl061.c | 70 ++++++++++++++++++++++++++++++-------------- hw/gpio/trace-events | 2 ++ 2 files changed, 50 insertions(+), 22 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 0f5d12e6d5a..f3b80c7776f 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -149,92 +149,116 @@ static uint64_t pl061_read(void *opaque, hwaddr offset, unsigned size) { PL061State *s = (PL061State *)opaque; + uint64_t r = 0; switch (offset) { case 0x0 ... 0x3fc: /* Data */ - return s->data & (offset >> 2); + r = s->data & (offset >> 2); + break; case 0x400: /* Direction */ - return s->dir; + r = s->dir; + break; case 0x404: /* Interrupt sense */ - return s->isense; + r = s->isense; + break; case 0x408: /* Interrupt both edges */ - return s->ibe; + r = s->ibe; + break; case 0x40c: /* Interrupt event */ - return s->iev; + r = s->iev; + break; case 0x410: /* Interrupt mask */ - return s->im; + r = s->im; + break; case 0x414: /* Raw interrupt status */ - return s->istate; + r = s->istate; + break; case 0x418: /* Masked interrupt status */ - return s->istate & s->im; + r = s->istate & s->im; + break; case 0x420: /* Alternate function select */ - return s->afsel; + r = s->afsel; + break; case 0x500: /* 2mA drive */ if (s->id != pl061_id_luminary) { goto bad_offset; } - return s->dr2r; + r = s->dr2r; + break; case 0x504: /* 4mA drive */ if (s->id != pl061_id_luminary) { goto bad_offset; } - return s->dr4r; + r = s->dr4r; + break; case 0x508: /* 8mA drive */ if (s->id != pl061_id_luminary) { goto bad_offset; } - return s->dr8r; + r = s->dr8r; + break; case 0x50c: /* Open drain */ if (s->id != pl061_id_luminary) { goto bad_offset; } - return s->odr; + r = s->odr; + break; case 0x510: /* Pull-up */ if (s->id != pl061_id_luminary) { goto bad_offset; } - return s->pur; + r = s->pur; + break; case 0x514: /* Pull-down */ if (s->id != pl061_id_luminary) { goto bad_offset; } - return s->pdr; + r = s->pdr; + break; case 0x518: /* Slew rate control */ if (s->id != pl061_id_luminary) { goto bad_offset; } - return s->slr; + r = s->slr; + break; case 0x51c: /* Digital enable */ if (s->id != pl061_id_luminary) { goto bad_offset; } - return s->den; + r = s->den; + break; case 0x520: /* Lock */ if (s->id != pl061_id_luminary) { goto bad_offset; } - return s->locked; + r = s->locked; + break; case 0x524: /* Commit */ if (s->id != pl061_id_luminary) { goto bad_offset; } - return s->cr; + r = s->cr; + break; case 0x528: /* Analog mode select */ if (s->id != pl061_id_luminary) { goto bad_offset; } - return s->amsel; + r = s->amsel; + break; case 0x52c ... 0xfcc: /* Reserved */ goto bad_offset; case 0xfd0 ... 0xffc: /* ID registers */ - return s->id[(offset - 0xfd0) >> 2]; + r = s->id[(offset - 0xfd0) >> 2]; + break; default: bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "pl061_read: Bad offset %x\n", (int)offset); break; } - return 0; + + trace_pl061_read(DEVICE(s)->canonical_path, offset, r); + return r; } static void pl061_write(void *opaque, hwaddr offset, @@ -243,6 +267,8 @@ static void pl061_write(void *opaque, hwaddr offset, PL061State *s = (PL061State *)opaque; uint8_t mask; + trace_pl061_write(DEVICE(s)->canonical_path, offset, value); + switch (offset) { case 0 ... 0x3fc: mask = (offset >> 2) & s->dir; diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index 48ccbb183cc..442be9406f5 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -18,6 +18,8 @@ pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIOD pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d" pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d" pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" +pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64 +pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64 # sifive_gpio.c sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 From patchwork Fri Jul 2 10:40:12 2021 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/11] hw/gpio/pl061: Document the interface of this device Date: Fri, 2 Jul 2021 11:40:12 +0100 Message-Id: <20210702104018.19881-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a comment documenting the "QEMU interface" of this device: which MMIO regions, IRQ lines, GPIO lines, etc it exposes. Signed-off-by: Peter Maydell --- hw/gpio/pl061.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index f3b80c7776f..06a1b82a503 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -6,6 +6,13 @@ * Written by Paul Brook * * This code is licensed under the GPL. + * + * QEMU interface: + * + sysbus MMIO region 0: the device registers + * + sysbus IRQ: the GPIOINTR interrupt line + * + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines + * + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as + * outputs */ #include "qemu/osdep.h" From patchwork Fri Jul 2 10:40:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 469513 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1256126jao; Fri, 2 Jul 2021 03:48:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz3dNnwDATOx3cTz+24jHvklY7RO1m5MemvqJWvv0lreNOvXySObvYXj7+ljB64+TZoWf2f X-Received: by 2002:a37:997:: with SMTP id 145mr4836407qkj.243.1625222881500; Fri, 02 Jul 2021 03:48:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625222881; cv=none; d=google.com; s=arc-20160816; b=W/t28XQGQ9lg/IGONQVtoaOJeMJFrnbtHeMlU0iPlrS1Q30mNumh8fpx0SkY7wxg29 eXkADIr1FUP6xLTw0yCdhFFjWkb7JVBtQqpaYWML3KrP6RjgGzuMygp0mpTIITaFVXJW 0FRvLj3K/MAFIG95T2N8llx0WCq3gxtase1ZCehbvQzlQQahSGQC3u0AWDVA/3wWfql5 tAtFcNeqc8xPaRkvCjdaYvPwtjOFkcmWsnEqmk7JVbiuypm6QLCPfxnpXn1xEO0C+oPM M2c8EsepTd6lqTi4STocwR8DMdtd7zt0pH6LdV/7DHGeP9awXEBygDSTPzK0gpqFAGPl j88A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CnOCqrZmWUxfwjKjUalVZwOU/ZbiNiTaO6KmtADP/mk=; b=R5lr2rOorYFG6wKyb1FG+cxXcqpRu4V5uU0DIvxWkiA94fCeLQFpNnJbvsENjSsSGh 05k8ZY8wepiJjaHjC0Wa6s7KlwJ3qlAj5w5iDuLKUtUgeuxsBsFVx8wWSHxqZYNn4br5 JRzJ9J9s5yVZRIsL/BLzdeQIYI2V8KTcDhqK6HeOUFqrTB0wZoHG7Y5svieaV3wmdx0v tcrClQHVMCWyqIRDypdjsMb53CxtrlmZNMqH9Hx8rWzUvf9hJOhBFIl4R9onW9PCUJeX 1K1pfHlJPBfbSTfj0iBDcHhCzU6qrw2+aunwZUo7mygO5P9F4/JEPiRgdIJ0lUbLioJ3 mfhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bg5ipmEd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z22si1944591qtn.103.2021.07.02.03.48.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 02 Jul 2021 03:48:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bg5ipmEd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45218 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lzGiG-00085L-SL for patch@linaro.org; Fri, 02 Jul 2021 06:48:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59874) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lzGb3-0004mn-VD for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:34 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:36466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lzGax-0006d9-84 for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:33 -0400 Received: by mail-wm1-x32a.google.com with SMTP id m41-20020a05600c3b29b02901dcd3733f24so8761235wms.1 for ; Fri, 02 Jul 2021 03:40:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CnOCqrZmWUxfwjKjUalVZwOU/ZbiNiTaO6KmtADP/mk=; b=Bg5ipmEdn5wI/Damf0iQdqGhk40VGHkKnPgiZnflIo/pVz7CwVq9eEGs9CvdScXgz3 My0PlJ0HHbIIR1sRg/Neran4WFC1D9++tqU1+RyGud4nshhJVLgchVJjHqrUVZI9dqpZ WgBBIaLCFiVu1b2juv5mNDinxbx6eu1cqWeqBtnwKaZ850eVwdrHqAM1qOYufiEMymBh ovchTKpEHcb4kiWIxQ+0ujHQu39a9JgzKKZIBAG0ZGAzb1RHpFLzamXXJbqFyirLDsqn BZLMyup+4g1zUSMyisbA0ysAmOU8tk/Yv5nFHkbZ6el4wi/ZnjDGkBnVuyiDwHhOR8wN fxJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CnOCqrZmWUxfwjKjUalVZwOU/ZbiNiTaO6KmtADP/mk=; b=NraJGfCq+4oEa9JDpxqtut1v8YyGbgAhQHTPhvx50OvlHQlE/NUtqlbwqGBREXX/NF 8RdCLEANOFLLalBUZG/ZAgmFKjqOBxw6rwpHXmu8x0Wx1laI4NN910eeCAFq3kFRUXE2 5nQKlxAbYnXewKpWbQIuBbh+cgIDwT8LSXraGpeqqWUzuYQsxnaQGfsuu2HwJeaxCQhs shkDs+VdMJM+lK85+WXZCohlGoCLq+bXQBz/4y8wbJikusdT3lkoh7bQ4HifTnmabkL3 q8BKTBqv13UurwJBZxQCPZEfRR1HpWSPw93AlXoGs6XjuDcQRx/KEIsDde5EWgjkptqS 2MAw== X-Gm-Message-State: AOAM531y5bHH8EfVn0Yq4uIpzRWBW+Os+V4d2xExF/iQDBPJWWoYQLFF Vsgyk3BM5vJTe3qlKhptYKzzP/lglyYWtKqP X-Received: by 2002:a05:600c:296:: with SMTP id 22mr15229146wmk.17.1625222425235; Fri, 02 Jul 2021 03:40:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/11] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers Date: Fri, 2 Jul 2021 11:40:13 +0100 Message-Id: <20210702104018.19881-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR which lets the guest configure whether the GPIO lines are pull-up, pull-down, or truly floating. Instead of assuming all lines are pulled high, honour the PUR and PDR registers. For the plain PL061, continue to assume that lines have an external pull-up resistor, as we did before. The stellaris board actually relies on this behaviour -- the CD line of the ssd0323 display device is connected to GPIO output C7, and it is only because of a different bug which we're about to fix that we weren't incorrectly driving this line high on reset and putting the ssd0323 into data mode. Signed-off-by: Peter Maydell --- hw/gpio/pl061.c | 58 +++++++++++++++++++++++++++++++++++++++++--- hw/gpio/trace-events | 2 +- 2 files changed, 55 insertions(+), 5 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 06a1b82a503..44bed56fef0 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -94,18 +94,68 @@ static const VMStateDescription vmstate_pl061 = { } }; +static uint8_t pl061_floating(PL061State *s) +{ + /* + * Return mask of bits which correspond to pins configured as inputs + * and which are floating (neither pulled up to 1 nor down to 0). + */ + uint8_t floating; + + if (s->id == pl061_id_luminary) { + /* + * If both PUR and PDR bits are clear, there is neither a pullup + * nor a pulldown in place, and the output truly floats. + */ + floating = ~(s->pur | s->pdr); + } else { + /* Assume outputs are pulled high. FIXME: this is board dependent. */ + floating = 0; + } + return floating & ~s->dir; +} + +static uint8_t pl061_pullups(PL061State *s) +{ + /* + * Return mask of bits which correspond to pins configured as inputs + * and which are pulled up to 1. + */ + uint8_t pullups; + + if (s->id == pl061_id_luminary) { + /* + * The Luminary variant of the PL061 has an extra registers which + * the guest can use to configure whether lines should be pullup + * or pulldown. + */ + pullups = s->pur; + } else { + /* Assume outputs are pulled high. FIXME: this is board dependent. */ + pullups = 0xff; + } + return pullups & ~s->dir; +} + static void pl061_update(PL061State *s) { uint8_t changed; uint8_t mask; uint8_t out; int i; + uint8_t pullups = pl061_pullups(s); + uint8_t floating = pl061_floating(s); - trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data); + trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data, + pullups, floating); - /* Outputs float high. */ - /* FIXME: This is board dependent. */ - out = (s->data & s->dir) | ~s->dir; + /* + * Pins configured as output are driven from the data register; + * otherwise if they're pulled up they're 1, and if they're floating + * then we give them the same value they had previously, so we don't + * report any change to the other end. + */ + out = (s->data & s->dir) | pullups | (s->old_out_data & floating); changed = s->old_out_data ^ out; if (changed) { s->old_out_data = out; diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index 442be9406f5..eb5fb4701c6 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -14,7 +14,7 @@ nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 # pl061.c -pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x" +pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x" pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d" pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d" pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" From patchwork Fri Jul 2 10:40:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 469511 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1255155jao; Fri, 2 Jul 2021 03:46:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzCBMlbagn2uDKhDo1HiyeGb6zpoW1bVLNQ1aCzjWqG0FwiFWksbXKLL1p06W8l5/C1rCD0 X-Received: by 2002:ac8:7b42:: with SMTP id m2mr3021193qtu.225.1625222801589; Fri, 02 Jul 2021 03:46:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625222801; cv=none; d=google.com; s=arc-20160816; b=pN8ZIGa9zv7iniHMrDD2W+NGtgGtUckS7+vQbV/a2rMr90JDp/NXKV7ptFteLcKvZ0 PS5WAfy0LPeDG0DnkFW53jAtJNQMTPpET6jwUY17DdHe5MvtQSq3CzY/CvOFxrALoogx 80CO9if1zWSI6ewlDkLw7+xlaE0MKhGCfYcfeXIAYpAG6hjdmFQS6aSB7N5P00rw+mEX a3cZnaDtZ/BWQj2BtBVDv/nc9+O+uMGa8GTFhThKVYQJbXykZxScuzabcvpZaJBHCQFa mkmiRxWCNG3Y0SYVKArHKSLZIQ7oxhFCWTuf9+7iH0WCtcvvYjO6Hn/uanBudy9qNkhu DWow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OHxj/xUOSn5B7Ujk/a1aY2KoAO5Tcc5/XFJvO0oLWf4=; b=TrfbSj/U+NnDlLhZ1Z6uijXDqcop+CYo9hxSm4H+TVc8H7mKYOj8YIpTwcMsnRNWrD MLqhc8ieqrf7qXyKP9dj7X8WUZ2eVd9AztS1enPRv6HTJ4e8yqeqDhjZNG84rDXZ1ABL YeOPMAtwesbYDhTLtUDIlWlhEVFVzjAO0o6Vdd0lRbxUQFbGP6sAc4seyIWU5y+0H8Dc gJZIsDA9podTARfCWHaDC1uZg+ljeRZX/xqoIyUPg1g/Zp00WE73ApuvNQ/5GsX4HE/S fSaeyqAb3HqUt8JOLC3L0GuIQIj6AQ2QwkGEKkw3ULG9w+L8UTCMMDbnUsRwiQ8iMMR5 PCuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pKfNGLE8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/11] hw/gpio/pl061: Make pullup/pulldown of outputs configurable Date: Fri, 2 Jul 2021 11:40:14 +0100 Message-Id: <20210702104018.19881-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The PL061 GPIO does not itself include pullup or pulldown resistors to set the value of a GPIO line treated as an output when it is configured as an input (ie when the PL061 itself is not driving it). In real hardware it is up to the board to add suitable pullups or pulldowns. Currently our implementation hardwires this to "outputs pulled high", which is correct for some boards (eg the realview ones: see figure 3-29 in the "RealView Platform Baseboard for ARM926EJ-S User Guide" DUI0224I), but wrong for others. In particular, the wiring in the 'virt' board and the gpio-pwr device assumes that wires should be pulled low, because otherwise the pull-to-high will trigger a shutdown or reset action. (The only reason this doesn't happen immediately on startup is due to another bug in the PL061, where we don't assert the GPIOs to the correct value on reset, but will do so as soon as the guest touches a register and pl061_update() gets called.) Add properties to the pl061 so the board can configure whether it wants GPIO lines to have pullup, pulldown, or neither. Signed-off-by: Peter Maydell --- hw/gpio/pl061.c | 51 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 44bed56fef0..bb496a19ade 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -13,12 +13,28 @@ * + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines * + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as * outputs + * + QOM property "pullups": an integer defining whether non-floating lines + * configured as inputs should be pulled up to logical 1 (ie whether in + * real hardware they have a pullup resistor on the line out of the PL061). + * This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should + * be pulled high, bit 1 configures line 1, and so on. The default is 0xff, + * indicating that all GPIO lines are pulled up to logical 1. + * + QOM property "pulldowns": an integer defining whether non-floating lines + * configured as inputs should be pulled down to logical 0 (ie whether in + * real hardware they have a pulldown resistor on the line out of the PL061). + * This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should + * be pulled low, bit 1 configures line 1, and so on. The default is 0x0. + * It is an error to set a bit in both "pullups" and "pulldowns". If a bit + * is 0 in both, then the line is considered to be floating, and it will + * not have qemu_set_irq() called on it when it is configured as an input. */ #include "qemu/osdep.h" #include "hw/irq.h" #include "hw/sysbus.h" +#include "hw/qdev-properties.h" #include "migration/vmstate.h" +#include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" #include "qom/object.h" @@ -62,6 +78,9 @@ struct PL061State { qemu_irq irq; qemu_irq out[N_GPIOS]; const unsigned char *id; + /* Properties, for non-Luminary PL061 */ + uint32_t pullups; + uint32_t pulldowns; }; static const VMStateDescription vmstate_pl061 = { @@ -109,8 +128,7 @@ static uint8_t pl061_floating(PL061State *s) */ floating = ~(s->pur | s->pdr); } else { - /* Assume outputs are pulled high. FIXME: this is board dependent. */ - floating = 0; + floating = ~(s->pullups | s->pulldowns); } return floating & ~s->dir; } @@ -131,8 +149,7 @@ static uint8_t pl061_pullups(PL061State *s) */ pullups = s->pur; } else { - /* Assume outputs are pulled high. FIXME: this is board dependent. */ - pullups = 0xff; + pullups = s->pullups; } return pullups & ~s->dir; } @@ -501,12 +518,38 @@ static void pl061_init(Object *obj) qdev_init_gpio_out(dev, s->out, N_GPIOS); } +static void pl061_realize(DeviceState *dev, Error **errp) +{ + PL061State *s = PL061(dev); + + if (s->pullups > 0xff) { + error_setg(errp, "pullups property must be between 0 and 0xff"); + return; + } + if (s->pulldowns > 0xff) { + error_setg(errp, "pulldowns property must be between 0 and 0xff"); + return; + } + if (s->pullups & s->pulldowns) { + error_setg(errp, "no bit may be set both in pullups and pulldowns"); + return; + } +} + +static Property pl061_props[] = { + DEFINE_PROP_UINT32("pullups", PL061State, pullups, 0xff), + DEFINE_PROP_UINT32("pulldowns", PL061State, pulldowns, 0x0), + DEFINE_PROP_END_OF_LIST() +}; + static void pl061_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->vmsd = &vmstate_pl061; dc->reset = &pl061_reset; + dc->realize = pl061_realize; + device_class_set_props(dc, pl061_props); } static const TypeInfo pl061_info = { From patchwork Fri Jul 2 10:40:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 469515 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1257586jao; Fri, 2 Jul 2021 03:50:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwrlYW4BnfQEl+r6SuK4EJqCGXd7fQwU2rstOaHwMTFoQQUX3CI9kiAiw88pZjfBw2obsVx X-Received: by 2002:ac8:7251:: with SMTP id l17mr4481997qtp.336.1625223011530; Fri, 02 Jul 2021 03:50:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625223011; cv=none; d=google.com; s=arc-20160816; b=GGqGiWwB9sH9NUzsMjSLwbtfUb58Hqy770bdXHjSKd94f7SUHoraiCzHtwG4gD1lHN sfvnhal2OG9KJXzbOqTfij1K1bEvUCFbXE5l1MMjRU3QbXfrfT/YQzwCAm3QIRFHoUx+ E1/QyJcAUdyLH71DiqrZJp2MoSPz0Z0wiWrC1J0qbfPIXPRmwg4ntFJ9JaU9uMPnG54w 3u30Xq2FV9iVBXnS365ddZOZsx2yTlgMS3+vPkyWISiAvfwInGQ+c113w/R8H/UZjd+/ 1vxGpTxW1m70MFchWbmryRhVI1LYzg4hIqzlNNvafzjDcFrb96cCqQLd1fl8Orszeu4c edaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DIGZ1OnFIqnIhBTRUfPjwDd5CcBHiyNlzbgBPSbVdrw=; b=i0inCqTP0IzvwjAytOz1hp6wwBVMf/Dojq/jx4dRIklWvQBlidDMzdLC8mGZ3zMUc7 bhSe1dUEymLKXgGaaG9OvR3iDK7yhG7/gaQCV9k+ERgFFeyB7zjWtEyiS3wzL94NaCE6 KokG2noo3NmQrHlTD7glTtBo1qZkM5d/UnqCCZhIqmOzSH5Owg3HgZOwUXXK+LeDjevX JErAlMav8E1zbjbXHJrORgvhYpFHlVAXDbRvhpSegU5Si0rCGTU1GSC+7b+ggAtYqqck 8XiJWfMGh3Rtsz+wTKtA4Xl0eK+oBA1ZyjCFDswL2YbDusTnop4K/tJXYipLQn3Fm9/L 0y7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IpqWMlIu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/11] hw/arm/virt: Make PL061 GPIO lines pulled low, not high Date: Fri, 2 Jul 2021 11:40:15 +0100 Message-Id: <20210702104018.19881-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For the virt board we have two PL061 devices -- one for NonSecure which is inputs only, and one for Secure which is outputs only. For the former, we don't care whether its outputs are pulled low or high when the line is configured as an input, because we don't connect them. For the latter, we do care, because we wire the lines up to the gpio-pwr device, which assumes that level 1 means "do the action" and 1 means "do nothing". For consistency in case we add more outputs in future, configure both PL061s to pull GPIO lines down to 0. Reported-by: Maxim Uvarov Signed-off-by: Peter Maydell --- hw/arm/virt.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4b96f060140..93ab9d21ea0 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -895,6 +895,9 @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio, MachineState *ms = MACHINE(vms); pl061_dev = qdev_new("pl061"); + /* Pull lines down to 0 if not driven by the PL061 */ + qdev_prop_set_uint32(pl061_dev, "pullups", 0); + qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); s = SYS_BUS_DEVICE(pl061_dev); sysbus_realize_and_unref(s, &error_fatal); memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); From patchwork Fri Jul 2 10:40:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 469510 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1253345jao; Fri, 2 Jul 2021 03:44:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy9HG5zhLCqZeN27La0hei7KfoOAgclqVixUo7xWsPts5uFASeZMV5yzDSX/ZOsS8DHkJKZ X-Received: by 2002:a25:bc0e:: with SMTP id i14mr5827854ybh.324.1625222651458; Fri, 02 Jul 2021 03:44:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625222651; cv=none; d=google.com; s=arc-20160816; b=CtUkgODwpJklZPv3i/VJOVmvBakUBgLY5pagYLTHCLRW4ak5sjDkG3NNrePG5NTWk3 FoU2OewRu5XH1utElMZRLdG/VPgR1DYUdglCezHcSZNhhImWbMIcce8OjBeCtuLwBllE XM/XroWK74NEC4LwLUojxsNlRpMO0cJfDBdrtoga0e8QKpRhyB962iuDsL4IDfIj/OXf 4QRBYYhIy5yZwA2jqgx3o+E124pfZjTpaSGeBJgNUm7smvcUxr5RRtaKNPzV1eDSiDKh YiwVQqmkaJIT4J+gOI+KF0W3/NUvvWbN7PtEFWaUQHubePAW3Ig2kJcpndlcX41KH5kZ YoRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=L7U6W9EH1FihHhwpCAtDoJvA3yxH/uDVM+98Ig5Lyfk=; b=GTFJ6bldexlOztnhvmryZjTgCSJEKbNCqrZOHpWdAufKsP1uka8n6foxUzsnGCwTxB ynfDCZWilCB4zroJ+lV1gfLdMHlexCro3iucU3jQpVVxZjZWjUy5wJOLrFJt261qIm3x y3XaqAqq152v9/3ddU5RxPTO2gAPitiR4H1n0SkmPO8/joFeQzyEHIs3+n7WcbLUPiKT Eurbht8TXiDCWHuscYce0MOl6b3GmK4/BKjueDFbrBq5du5zkBPweWzIijszc85Hfnni I5LhF9jeyG6ewZQVR8Mt8V2XHap8ckL4HBcqxlBfn2PWdhRRTz5oLsPH4d0p2Kr8D++z VBUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bq6gKAWv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:27 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/11] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset Date: Fri, 2 Jul 2021 11:40:16 +0100 Message-Id: <20210702104018.19881-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The PL061 comes out of reset with all its lines configured as input, which means they might need to be pulled to 0 or 1 depending on the 'pullups' and 'pulldowns' properties. Currently we do not assert these lines on reset; they will only be set whenever the guest first touches a register that triggers a call to pl061_update(). Convert the device to three-phase reset so we have a place where we can safely call qemu_set_irq() to set the floating lines to their correct values. Signed-off-by: Peter Maydell --- hw/gpio/pl061.c | 29 +++++++++++++++++++++++++---- hw/gpio/trace-events | 1 + 2 files changed, 26 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index bb496a19ade..8d12b2d6b97 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -448,13 +448,14 @@ static void pl061_write(void *opaque, hwaddr offset, return; } -static void pl061_reset(DeviceState *dev) +static void pl061_enter_reset(Object *obj, ResetType type) { - PL061State *s = PL061(dev); + PL061State *s = PL061(obj); + + trace_pl061_reset(DEVICE(s)->canonical_path); /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ s->data = 0; - s->old_out_data = 0; s->old_in_data = 0; s->dir = 0; s->isense = 0; @@ -476,6 +477,24 @@ static void pl061_reset(DeviceState *dev) s->amsel = 0; } +static void pl061_hold_reset(Object *obj) +{ + PL061State *s = PL061(obj); + int i, level; + uint8_t floating = pl061_floating(s); + uint8_t pullups = pl061_pullups(s); + + for (i = 0; i < N_GPIOS; i++) { + if (extract32(floating, i, 1)) { + continue; + } + level = extract32(pullups, i, 1); + trace_pl061_set_output(DEVICE(s)->canonical_path, i, level); + qemu_set_irq(s->out[i], level); + } + s->old_out_data = pullups; +} + static void pl061_set_irq(void * opaque, int irq, int level) { PL061State *s = (PL061State *)opaque; @@ -545,11 +564,13 @@ static Property pl061_props[] = { static void pl061_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); dc->vmsd = &vmstate_pl061; - dc->reset = &pl061_reset; dc->realize = pl061_realize; device_class_set_props(dc, pl061_props); + rc->phases.enter = pl061_enter_reset; + rc->phases.hold = pl061_hold_reset; } static const TypeInfo pl061_info = { diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index eb5fb4701c6..1dab99c5604 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -20,6 +20,7 @@ pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64 pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64 +pl061_reset(const char *id) "%s reset" # sifive_gpio.c sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 From patchwork Fri Jul 2 10:40:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 469514 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1257429jao; Fri, 2 Jul 2021 03:49:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxs8cvpfJUNKD0WkWonVSprw3dJDcvPOTtaBaT0ZXvZ1K7k4dTreRXw/PjWV4l9uraw1J5v X-Received: by 2002:a37:678d:: with SMTP id b135mr3666924qkc.17.1625222998565; Fri, 02 Jul 2021 03:49:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625222998; cv=none; d=google.com; s=arc-20160816; b=DSeVAVHou6jBl6mdj9tQHAv71LzMHnrZrBJzpHJIDnwAlDfwriVPsBL4s7neaI43Ap uZJStxQ3gHKjoiFRySiFOeXOCpkyUWKv7lyyu+8HWFiXEdK205F+eNYsCIZyMEQBHqjm kQ3pikk7UHHpD7bCUmWHwAKOkqsa4rjJKDiXNTOE6ye5mVAz6eT1zp3fGouMoYJIgq6f Mt/6Hqp6dtZgwmjmSus0gq9Oc481MNiVwHAi+XzZoJrCjzslaNu8Xt4Bn5ZsUoDaokoe dHF17PfLNXLekW+vwhjvS9itdPgssYd10GtH+AJVCZ2XWAmwRtWizBSzTH/jwMr65Y6A awRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pPs0EK8qhWJ7QET2DXUmT74qvqEztx/Rozsf7xNVhPY=; b=VlTxS0z2VKZKb8aAX8UHmEHoIVJz6jGfoAQuLqAClhjX1OG0VBE6gQSBlVBd2hY1V/ LRtjYfk9IP8ZYvK7xO1to6uQlWuP1uNBX0wTBZtM7GADctSli4LzyEn5g3H+i3hY2ULG vXKFmUTonsNscnuOAnLJumSOhUzEqvxyAs1QXqDrnV267lZsKizMCuJIcmZ+Kb+0MxX7 rva1vpyKFv9pgLIN//Q6rXNJ2Wyvgi8xZ5TC1WvUA8GOnocVWJtmBUv1lnyCVHTHcgHc 0HtZvOpHPpmlPijzwdiZD6aeZe2mUtdelJBWNPeu6uk1nRQacHF7UwwhxZA62SnoW+UL DLPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QNlW6bmC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/11] hw/gpio/pl061: Document a shortcoming in our implementation Date: Fri, 2 Jul 2021 11:40:17 +0100 Message-Id: <20210702104018.19881-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The Luminary PL061s in the Stellaris LM3S9695 don't all have the same reset value for GPIOPUR. We can get away with not letting the board configure the PUR reset value because we don't actually wire anything up to the lines which should reset to pull-up. Add a comment noting this omission. Signed-off-by: Peter Maydell --- Not worth actually fixing, but I wanted a note since I spotted this while I was reading the datasheet anyway. --- hw/gpio/pl061.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 8d12b2d6b97..2cb3a231b43 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -455,6 +455,15 @@ static void pl061_enter_reset(Object *obj, ResetType type) trace_pl061_reset(DEVICE(s)->canonical_path); /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ + + /* + * FIXME: For the LM3S6965, not all of the PL061 instances have the + * same reset values for GPIOPUR, GPIOAFSEL and GPIODEN, so in theory + * we should allow the board to configure these via properties. + * In practice, we don't wire anything up to the affected GPIO lines + * (PB7, PC0, PC1, PC2, PC3 -- they're used for JTAG), so we can + * get away with this inaccuracy. + */ s->data = 0; s->old_in_data = 0; s->dir = 0; From patchwork Fri Jul 2 10:40:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 469516 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1258861jao; Fri, 2 Jul 2021 03:52:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzuDj4BQfw8jjq5nQODUgyLGfrsR04BflR24iJSrge2WDGFmHskhqH/hGaGIrq27R8GQ7yg X-Received: by 2002:a05:6102:949:: with SMTP id a9mr5591190vsi.54.1625223125691; Fri, 02 Jul 2021 03:52:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625223125; cv=none; d=google.com; s=arc-20160816; b=JdrITplDSkdkLLyBAgcAQsnKd7nS44xoGeB6Aao+tAQC1VZvwZylsXVYu+9ADL78rx hisLWxWYUDriyXbMOWnxhcsKWil/AL1tzHSnccPKkg6407jCoWVDlHhvbeEcKDgKebM/ cgPoEUkOy1Z/fR0r5HCTICCEFvUccId9JkN03fUcTWESAICM3G/de0vlCk8eFvhkAL/a Wg0L5nWVtBcYrSt8tagTpirtxHLOYNSu5S2e7qX07pKjQ4shgd50e3OcIIZBWaag+ojs 7NaMpa0riTeYR7a+wTcTAV3w54uilISKwUCQRxqteHEbUpdZmGu3siqDaxAJPcEpUbOc elTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4BANoWgI0RjhipvmntovUAzoJsSWS5FJsfiHUg00m54=; b=EfPsqZ/SxvGFmpnh0KyFChjH7f2ZkGKWciBRGs3M+tp78qwDh0UYzvGaPKe3taT6CE wIaB0Ytfx1J8L6ltf5kkKh8/4XwFgEC+ogUcV2CNDT+5DdLdvXsfU6ZaJox9b91jEQe8 JvrPF9mjphhhjQCBgmxex/shFfh11qwC2UUHyOl+/3RCjwoKcRerJvHIWewPxTndLnls 9qIyXgP589mtsRtPpHoQcd3xBXiZo2V64RbSrVcKGCKO1cTXPUWGvsTFU4I63bZp+4lg Kb1hCS9J/KXqfexET1I+Os9CTZlYh4VRlTBWojL0HaRx7sN7kZVeyoW3ImlhXmxtArQS bDGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QksazumL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/11] hw/arm/stellaris: Expand comment about handling of OLED chipselect Date: Fri, 2 Jul 2021 11:40:18 +0100 Message-Id: <20210702104018.19881-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The stellaris board doesn't emulate the handling of the OLED chipselect line correctly. Expand the comment describing this, including a sketch of the theoretical correct way to do it. Signed-off-by: Peter Maydell --- Given the stellaris board is old and not very useful these days, I didn't think it worth the effort of actually implementing the correct behaviour, but I wanted to record what I figured out from various data sheets while I was looking at PL061 stuff... --- hw/arm/stellaris.c | 56 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 8b4dab9b79f..ad48cf26058 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1453,13 +1453,67 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) DeviceState *sddev; DeviceState *ssddev; - /* Some boards have both an OLED controller and SD card connected to + /* + * Some boards have both an OLED controller and SD card connected to * the same SSI port, with the SD card chip select connected to a * GPIO pin. Technically the OLED chip select is connected to the * SSI Fss pin. We do not bother emulating that as both devices * should never be selected simultaneously, and our OLED controller * ignores stray 0xff commands that occur when deselecting the SD * card. + * + * The h/w wiring is: + * - GPIO pin D0 is wired to the active-low SD card chip select + * - GPIO pin A3 is wired to the active-low OLED chip select + * - The SoC wiring of the PL061 "auxiliary function" for A3 is + * SSI0Fss ("frame signal"), which is an output from the SoC's + * SSI controller. The SSI controller takes SSI0Fss low when it + * transmits a frame, so it can work as a chip-select signal. + * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx + * (the OLED never sends data to the CPU, so no wiring needed) + * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx + * and the OLED display-data-in + * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED + * serial-clock input + * So a guest that wants to use the OLED can configure the PL061 + * to make pins A2, A3, A5 aux-function, so they are connected + * directly to the SSI controller. When the SSI controller sends + * data it asserts SSI0Fss which selects the OLED. + * A guest that wants to use the SD card configures A2, A4 and A5 + * as aux-function, but leaves A3 as a software-controlled GPIO + * line. It asserts the SD card chip-select by using the PL061 + * to control pin D0, and lets the SSI controller handle Clk, Tx + * and Rx. (The SSI controller asserts Fss during tx cycles as + * usual, but because A3 is not set to aux-function this is not + * forwarded to the OLED, and so the OLED stays unselected.) + * + * The QEMU implementation instead is: + * - GPIO pin D0 is wired to the active-low SD card chip select, + * and also to the OLED chip-select which is implemented + * as *active-high* + * - SSI controller signals go to the devices regardless of + * whether the guest programs A2, A4, A5 as aux-function or not + * + * The problem with this implementation is if the guest doesn't + * care about the SD card and only uses the OLED. In that case it + * may choose never to do anything with D0 (leaving it in its + * default floating state, which reliably leaves the card disabled + * because an SD card has a pullup on CS within the card itself), + * and only set up A2, A3, A5. This for us would mean the OLED + * never gets the chip-select assert it needs. We work around + * this with a manual raise of D0 here (despite board creation + * code being the wrong place to raise IRQ lines) to put the OLED + * into an initially selected state. + * + * In theory the right way to model this would be: + * - Implement aux-function support in the PL061, with an + * extra set of AFIN and AFOUT GPIO lines (set up so that + * if a GPIO line is in auxfn mode the main GPIO in and out + * track the AFIN and AFOUT lines) + * - Wire the AFOUT for D0 up to either a line from the + * SSI controller that's pulled low around every transmit, + * or at least to an always-0 line here on the board + * - Make the ssd0323 OLED controller chipselect active-low */ bus = qdev_get_child_bus(dev, "ssi");