From patchwork Wed Aug 22 20:41:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 144852 Delivered-To: patch@linaro.org Received: by 2002:a2e:164a:0:0:0:0:0 with SMTP id 10-v6csp401483ljw; Wed, 22 Aug 2018 13:41:25 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxaqN/ak9DJDE5yRWJMjw+OPP+XD/udPqJn41hzuAkR5UIXx+XDV7VBKIcG80oToVAKuwXI X-Received: by 2002:a17:902:c6b:: with SMTP id 98-v6mr55451307pls.233.1534970485572; Wed, 22 Aug 2018 13:41:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534970485; cv=none; d=google.com; s=arc-20160816; b=CWkh79ufy0W+NU92TeoMxhjDGhec2wDuxWC/tiyfX3hEUNf4WhretezylxBLYZHaWS 96v7t4Ri9t9UP5wJJNo9ZS2n5sH+nBTqvPQvf8Jviobt01qrodAmrkkgdthYnidbOHKu tTO7eZqxdXTXBWoLfp8UC2XGVwFnocOUM4ypEPIdqSlUDN5KiDWdDITOJcaePgqWPPn9 /o2bMvzwWpK1rA/jW/l8zjZcj4yEbsFGF619ckwlVkR6xIwFtde/GTx8Wer9sb40yX7P 5gVbD/wEQkz2WQq6Ro+EPoKK9U0DpHQh72Xd0eGBLCgpup3TLmk5/dfk9p852a+n06VL TwmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=LFNwoKHWnAWrIGSswOfaA83EB0WZUvIJWxI4582V7zU=; b=RA/VPObaMpYoTKR+sBdjhiwlDt+77p6WmLlj0/WwPMm5XEKyroQ+W2OsIUUBoWQuko 3PZPU6H3oc0l/g8X4hWfZPTCSLpNnyXq+T0ao+XaXHuNB1kh0x+InAcFQ6I8R2z74ilq CBad/KdNTgVIeu6T21QTynFrQcFXEee/lluwDv7VBjziU6zB3+fWP8+Yfq6+/+ikqKSH Hk/qk/2iKVpMSPImsIfcsnhvCoPuP5OJS4/9Kc7md/h6AdSVdGQrbPAPWRXNmgFlex/V 2ThihrvTNmd7oQJBGhabALkEriPBlNdG0pvZJgNwDIy4p3QZNrU/mzMPtqPt+JegvYlB P33Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GVvhlFEz; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:20 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Arnd Bergmann , arm@kernel.org, Linus Walleij Subject: [PATCH 01/11] ARM/gpio: ep93xx: build standalone Date: Wed, 22 Aug 2018 22:41:01 +0200 Message-Id: <20180822204111.9581-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arnd Bergmann As a preparation for multiplatform support, this ensures that the ep93xx gpio driver can be built without any of the platform specific header files. We pass the IRQ numbers as a resource now, and use the virtual mmio base from the already existing resource, rather than relying on the hardwired virtual address from the header file. Some numbers are now hardcoded that came from macros in the past, but for all I can tell, the driver already relied on the specific values. Cc: arm@kernel.org Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij --- Arnd/other ARM SoC person: Please provide an ACK for this patch so I can merge it with the rest of the refactorings into the GPIO tree. --- arch/arm/mach-ep93xx/core.c | 9 +++++++ drivers/gpio/gpio-ep93xx.c | 48 ++++++++++++++++++------------------- 2 files changed, 32 insertions(+), 25 deletions(-) -- 2.17.1 Acked-by: Arnd Bergmann Acked-by: Olof Johansson diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 574dfdc527ed..b82b632789f7 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -141,6 +141,15 @@ EXPORT_SYMBOL_GPL(ep93xx_chip_revision); *************************************************************************/ static struct resource ep93xx_gpio_resource[] = { DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO3MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO4MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO5MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO6MUX), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX), }; static struct platform_device ep93xx_gpio_device = { diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 45d384039e9b..654525d6a9f1 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -22,11 +22,20 @@ /* FIXME: this is here for gpio_to_irq() - get rid of this! */ #include -#include -#include - #define irq_to_gpio(irq) ((irq) - gpio_to_irq(0)) +void __iomem *ep93xx_gpio_base; /* FIXME: put this into irq_data */ +#define EP93XX_GPIO_REG(x) (ep93xx_gpio_base + (x)) +#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) +#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) +#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) + +/* Maximum value for gpio line identifiers */ +#define EP93XX_GPIO_LINE_MAX 63 + +/* Maximum value for irq capable line identifiers */ +#define EP93XX_GPIO_LINE_MAX_IRQ 23 + struct ep93xx_gpio { void __iomem *mmio_base; struct gpio_chip gc[8]; @@ -87,7 +96,7 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) status = readb(EP93XX_GPIO_A_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { - int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i; + int gpio_irq = gpio_to_irq(0) + i; generic_handle_irq(gpio_irq); } } @@ -95,7 +104,7 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) status = readb(EP93XX_GPIO_B_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { - int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i; + int gpio_irq = gpio_to_irq(8) + i; generic_handle_irq(gpio_irq); } } @@ -110,7 +119,7 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) */ unsigned int irq = irq_desc_get_irq(desc); int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ - int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx; + int gpio_irq = gpio_to_irq(16) + port_f_idx; generic_handle_irq(gpio_irq); } @@ -228,9 +237,10 @@ static struct irq_chip ep93xx_gpio_irq_chip = { .irq_set_type = ep93xx_gpio_irq_type, }; -static void ep93xx_gpio_init_irq(void) +static void ep93xx_gpio_init_irq(struct platform_device *pdev) { int gpio_irq; + int i; for (gpio_irq = gpio_to_irq(0); gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { @@ -239,24 +249,11 @@ static void ep93xx_gpio_init_irq(void) irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); } - irq_set_chained_handler(IRQ_EP93XX_GPIO_AB, + irq_set_chained_handler(platform_get_irq(pdev, 0), ep93xx_gpio_ab_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX, - ep93xx_gpio_f_irq_handler); - irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX, - ep93xx_gpio_f_irq_handler); + for (i = 1; i <= 8; i++) + irq_set_chained_handler(platform_get_irq(pdev, i), + ep93xx_gpio_f_irq_handler); } @@ -362,6 +359,7 @@ static int ep93xx_gpio_probe(struct platform_device *pdev) ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res); if (IS_ERR(ep93xx_gpio->mmio_base)) return PTR_ERR(ep93xx_gpio->mmio_base); + ep93xx_gpio_base = ep93xx_gpio->mmio_base; for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { struct gpio_chip *gc = &ep93xx_gpio->gc[i]; @@ -373,7 +371,7 @@ static int ep93xx_gpio_probe(struct platform_device *pdev) bank->label); } - ep93xx_gpio_init_irq(); + ep93xx_gpio_init_irq(pdev); return 0; } From patchwork Wed Aug 22 20:41:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 144853 Delivered-To: patch@linaro.org Received: by 2002:a2e:164a:0:0:0:0:0 with SMTP id 10-v6csp401499ljw; Wed, 22 Aug 2018 13:41:27 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzbN6KGabVaGNTDK/pX3Ty9nc6m50kUb88t0xO1iSBZ5JNNbxpZFhD0dWjkDyajAc0Duavw X-Received: by 2002:a63:af17:: with SMTP id w23-v6mr18771752pge.47.1534970486955; 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[209.132.180.67]) by mx.google.com with ESMTP id t23-v6si2559068pgi.301.2018.08.22.13.41.26; Wed, 22 Aug 2018 13:41:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bCsRGdoN; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727285AbeHWAHt (ORCPT + 5 others); Wed, 22 Aug 2018 20:07:49 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:43702 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727331AbeHWAHt (ORCPT ); Wed, 22 Aug 2018 20:07:49 -0400 Received: by mail-lj1-f193.google.com with SMTP id m84-v6so2429773lje.10 for ; Wed, 22 Aug 2018 13:41:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uh0WbNXotrGv/LOuuP8ez/+FvQdmMcnLT3xmPJQ17Cs=; b=bCsRGdoNmAZHbv2xavWhPkrDaToTMw99ukokLw2irfs8XKw+eKmM7l8BEauVyT0Lx7 ugYUhJct5IgrERSmvMQDWiCwjDekhJinkgfke7XEUiNdNRVoFMJi8Fvbc9Uf1Th35SfC W1Vzu8vjDS1Wzrqsrw8hSobAvPDOkAs8G5xUg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uh0WbNXotrGv/LOuuP8ez/+FvQdmMcnLT3xmPJQ17Cs=; b=ll2iuxmqNfgGdPGarksG/C9vShHLGLo7khWkhnEoyJLSzLTLJ/D27xMBLEPYNKxApW TllerivHnH2xdwPs5z+aKyQbHWiAdcPhgJfzE69U8jshtCK9+bdP/3HG9IGYfUlje9XP fHoQP7qnjQljzFvr1iI3M81GJbm+58QkRnlerF9NCvN/8uEfPdYCH9VDeUX9ziImeTXu uvLaoO18LfNAjtNy/Zr/tBgVw8SG6gLVrfc07tWUpEp9Z+g92OnR8qeX2sKYtVxCwAqz F0XgzY8DPy4d54xBPvBEwRPEXBqqkEBZskEI/cNJyRTgUG/3WK76/yUADA2tChgoCt55 /axQ== X-Gm-Message-State: AOUpUlGxrR6hHiNuY4jqWBP6bAk3a9JpVaR9O5Qxnjl6/7a5sq1iHt1C 1dDNF2QA6+DMvp29ViQL17Nphx8Z1nYVCA== X-Received: by 2002:a2e:534e:: with SMTP id t14-v6mr30103840ljd.26.1534970484301; Wed, 22 Aug 2018 13:41:24 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:23 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 02/11] gpio: ep93xx: Cut down variable names Date: Wed, 22 Aug 2018 22:41:02 +0200 Message-Id: <20180822204111.9581-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In order to clean up the driver I need to cut a few trees, sorry, variable names, so I can see the forest, sorry driver properly. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) -- 2.17.1 Tested-by: Alexander Sverdlin diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 654525d6a9f1..3bfd0e46f7ed 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -37,7 +37,7 @@ void __iomem *ep93xx_gpio_base; /* FIXME: put this into irq_data */ #define EP93XX_GPIO_LINE_MAX_IRQ 23 struct ep93xx_gpio { - void __iomem *mmio_base; + void __iomem *base; struct gpio_chip gc[8]; }; @@ -323,10 +323,10 @@ static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) } static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, - void __iomem *mmio_base, struct ep93xx_gpio_bank *bank) + void __iomem *base, struct ep93xx_gpio_bank *bank) { - void __iomem *data = mmio_base + bank->data; - void __iomem *dir = mmio_base + bank->dir; + void __iomem *data = base + bank->data; + void __iomem *dir = base + bank->dir; int err; err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0); @@ -346,27 +346,27 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, static int ep93xx_gpio_probe(struct platform_device *pdev) { - struct ep93xx_gpio *ep93xx_gpio; + struct ep93xx_gpio *epg; struct resource *res; int i; struct device *dev = &pdev->dev; - ep93xx_gpio = devm_kzalloc(dev, sizeof(struct ep93xx_gpio), GFP_KERNEL); - if (!ep93xx_gpio) + epg = devm_kzalloc(dev, sizeof(*epg), GFP_KERNEL); + if (!epg) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ep93xx_gpio->mmio_base)) - return PTR_ERR(ep93xx_gpio->mmio_base); - ep93xx_gpio_base = ep93xx_gpio->mmio_base; + epg->base = devm_ioremap_resource(dev, res); + if (IS_ERR(epg->base)) + return PTR_ERR(epg->base); + ep93xx_gpio_base = epg->base; for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { - struct gpio_chip *gc = &ep93xx_gpio->gc[i]; + struct gpio_chip *gc = &epg->gc[i]; struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; if (ep93xx_gpio_add_bank(gc, &pdev->dev, - ep93xx_gpio->mmio_base, bank)) + epg->base, bank)) dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", bank->label); } From patchwork Wed Aug 22 20:41:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 144854 Delivered-To: patch@linaro.org Received: by 2002:a2e:164a:0:0:0:0:0 with SMTP id 10-v6csp401534ljw; Wed, 22 Aug 2018 13:41:30 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyVKS/cPdDb4VBi678uzXIu1+zywKKLRy7v/ytHYrSlJ/b3mSavswjv+/mPWeabeSR6WBDz X-Received: by 2002:a65:6102:: with SMTP id z2-v6mr53247585pgu.46.1534970489811; Wed, 22 Aug 2018 13:41:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534970489; cv=none; d=google.com; s=arc-20160816; b=D3U4ff8is3KY9vcgBjE0LBcpH2vBDI3QfT7aX4CMTWAAtRzNADTI2iOeNcZIWlB+gW rfA4WUKEqSzW0scGiIJxDreA2+MKJnWr8NHc2Uw+/JSI36bC9Hz24q1vwAUl06bDmScR LtRFJMloJGtRqspqcIS7C4ApD1bSJ7wqyqnYFBwT5u6FLTo8EaCtw8PSQCAf6F5wBtDl scSYWbp84oiG5B60ZHQpRBNetzA1F5l90jnZX59PZU8gaJYwQfSTSy+OOdsSzpALZ2zr qn42zJA4ZfDE9AjHFtt9n0XQm0Z8hcS3M56jpEwFNeKjOSG5ZdjoUtLw/KC4yqYPajI2 NF2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=O6WuP8qwseI7NYdNvQzo28H1LrcQOeUzubYHV0pnHVE=; b=wvjA2b4Q+3HzKjQnzO2WsXBLFj2vT2Ts2awABcUV8cJu6zTF10vpNS1pfe0BFcvE7F ntjJa7nTY+Ys/5nXszvZw6H9eCWOkwGAKg49KwoGCf5VoSGJYZ+o+0SbqLKmVaKkYnFY xazYcUXzOc0fRDzi6s2aSStZGALXGCXT7L9ccpOkuyduQr7zHP1iiHyawoTFr+WsCL9I uYoMr4APCG4iO3UqFfjpSpwlQPyjsrBpLE7moKu4KxkHqKP0uLOU+uH2br9UTri1UqX6 b7DPs3tnBkyPaNObnSuRZ8pSWXnfqhgLfMOIt8hc3Xg/aoPhjqih3LYNAsQnATo9K2Af XPDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="CQGW/1tq"; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:26 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 03/11] gpio: ep93xx: Switch to SPDX license tag Date: Wed, 22 Aug 2018 22:41:03 +0200 Message-Id: <20180822204111.9581-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The subject says it all. Cut down on boilerplate. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 3bfd0e46f7ed..3822d11e90ac 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Generic EP93xx GPIO handling * @@ -6,10 +7,6 @@ * * Based on code originally from: * linux/arch/arm/mach-ep93xx/core.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include From patchwork Wed Aug 22 20:41:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 144855 Delivered-To: patch@linaro.org Received: by 2002:a2e:164a:0:0:0:0:0 with SMTP id 10-v6csp401574ljw; Wed, 22 Aug 2018 13:41:33 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzLm+BsidEYmLvt1LzBtuH2lH7323ab6BSruW17bvUI7BngehE+dudsPDEOcWa3dX3XbcL4 X-Received: by 2002:a63:e40d:: with SMTP id a13-v6mr52428527pgi.289.1534970493061; Wed, 22 Aug 2018 13:41:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534970493; cv=none; d=google.com; s=arc-20160816; b=ZB3A1ft6id3fswt7f+Zgpf7DiG3wsHev+YqvRJcLOFru8tv/56VvwguLYK4WuvML/n pFxJZ34X/J/+nTTDZnhipOFN809xmwrJxs1Jxo9Y01j/Pl+ecTCgV9l1T7q0vFPrZAx/ 1sjbTwDi6fT1yM6ugQyYmm7li0x1ZNCo7yAZXJPPS98db/DoisyVAH/DNAswfrRUnUTU c3ic/4Aa0B69nQKmOM32lcKNVpDCog74vdR8gHGp63BOdT7TBfMpyNXJnT0hoc6HwNOd My7uLvRKyw7XiOyxZJgDwzQSf588PQmylINmKftKYLBE/uuo+eWRpg5x8nSoMVhInSHy t2Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=CNNg5YSFxUgNMgU8iF4QVIUBRAAvk8zwjvj3+dqCUUU=; b=O2fvRvQFNAFLA18dpgzhY+6A6zXeTj2P5covrG9hELG+goOhza9B3gmIKcSc4YePap uDhYILy96EdLU0+Imr2+rEx1PI7e6SN8bcxyDF+0NHhZMCuK9KqF0yQu7tZ+rCNDuKfG GuBCfJBTVwwc1dnE84sVQaK6xNBi9NgMI6Fdq+mllz38TWPsqgFODj13p9pT/Wa/ZczE SSx6lHaAAVtwjYcPSTyMqBA5x+zc28SON5j+JcewC51l7jxweurbrHk9nwB5jNKArPrK 6ixcF0VYT0ZB88TOvVtD/NXm4GY1rlm1LLupmGKvsMmKJUmJhKTE0GDWvWklw1lw/En4 aPfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EPke5zQ+; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:28 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 04/11] gpio: ep93xx: Pass around struct gpio_chip Date: Wed, 22 Aug 2018 22:41:04 +0200 Message-Id: <20180822204111.9581-5-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Instead of using a global variable, pass around the struct gpio_chip * pointer and dereference to the state container struct ep93xx_gpio as needed, like all other drivers do. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 111 ++++++++++++++++++++++++------------- 1 file changed, 73 insertions(+), 38 deletions(-) -- 2.17.1 diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 3822d11e90ac..379f2573f794 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -21,11 +21,9 @@ #define irq_to_gpio(irq) ((irq) - gpio_to_irq(0)) -void __iomem *ep93xx_gpio_base; /* FIXME: put this into irq_data */ -#define EP93XX_GPIO_REG(x) (ep93xx_gpio_base + (x)) -#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) -#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) -#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) +#define EP93XX_GPIO_F_INT_STATUS 0x5c +#define EP93XX_GPIO_A_INT_STATUS 0xa0 +#define EP93XX_GPIO_B_INT_STATUS 0xbc /* Maximum value for gpio line identifiers */ #define EP93XX_GPIO_LINE_MAX 63 @@ -54,23 +52,24 @@ static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; -static void ep93xx_gpio_update_int_params(unsigned port) +static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port) { BUG_ON(port > 2); - writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port])); + writeb_relaxed(0, epg->base + int_en_register_offset[port]); writeb_relaxed(gpio_int_type2[port], - EP93XX_GPIO_REG(int_type2_register_offset[port])); + epg->base + int_type2_register_offset[port]); writeb_relaxed(gpio_int_type1[port], - EP93XX_GPIO_REG(int_type1_register_offset[port])); + epg->base + int_type1_register_offset[port]); writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], - EP93XX_GPIO_REG(int_en_register_offset[port])); + epg->base + int_en_register_offset[port]); } -static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable) +static void ep93xx_gpio_int_debounce(struct ep93xx_gpio *epg, + unsigned int irq, bool enable) { int line = irq_to_gpio(irq); int port = line >> 3; @@ -82,15 +81,17 @@ static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable) gpio_int_debounce[port] &= ~port_mask; writeb(gpio_int_debounce[port], - EP93XX_GPIO_REG(int_debounce_register_offset[port])); + epg->base + int_debounce_register_offset[port]); } static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) { + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); unsigned char status; int i; - status = readb(EP93XX_GPIO_A_INT_STATUS); + status = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { int gpio_irq = gpio_to_irq(0) + i; @@ -98,7 +99,7 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) } } - status = readb(EP93XX_GPIO_B_INT_STATUS); + status = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { int gpio_irq = gpio_to_irq(8) + i; @@ -123,20 +124,24 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) static void ep93xx_gpio_irq_ack(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); int line = irq_to_gpio(d->irq); int port = line >> 3; int port_mask = 1 << (line & 7); if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { gpio_int_type2[port] ^= port_mask; /* switch edge direction */ - ep93xx_gpio_update_int_params(port); + ep93xx_gpio_update_int_params(epg, port); } - writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); + writeb(port_mask, epg->base + eoi_register_offset[port]); } static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); int line = irq_to_gpio(d->irq); int port = line >> 3; int port_mask = 1 << (line & 7); @@ -145,27 +150,31 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) gpio_int_type2[port] ^= port_mask; /* switch edge direction */ gpio_int_unmasked[port] &= ~port_mask; - ep93xx_gpio_update_int_params(port); + ep93xx_gpio_update_int_params(epg, port); - writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); + writeb(port_mask, epg->base + eoi_register_offset[port]); } static void ep93xx_gpio_irq_mask(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); int line = irq_to_gpio(d->irq); int port = line >> 3; gpio_int_unmasked[port] &= ~(1 << (line & 7)); - ep93xx_gpio_update_int_params(port); + ep93xx_gpio_update_int_params(epg, port); } static void ep93xx_gpio_irq_unmask(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); int line = irq_to_gpio(d->irq); int port = line >> 3; gpio_int_unmasked[port] |= 1 << (line & 7); - ep93xx_gpio_update_int_params(port); + ep93xx_gpio_update_int_params(epg, port); } /* @@ -175,6 +184,8 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) */ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); const int gpio = irq_to_gpio(d->irq); const int port = gpio >> 3; const int port_mask = 1 << (gpio & 7); @@ -220,7 +231,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) gpio_int_enabled[port] |= port_mask; - ep93xx_gpio_update_int_params(port); + ep93xx_gpio_update_int_params(epg, port); return 0; } @@ -234,23 +245,47 @@ static struct irq_chip ep93xx_gpio_irq_chip = { .irq_set_type = ep93xx_gpio_irq_type, }; -static void ep93xx_gpio_init_irq(struct platform_device *pdev) +static void ep93xx_gpio_init_irq(struct platform_device *pdev, + struct ep93xx_gpio *epg) { int gpio_irq; int i; + /* The A bank */ for (gpio_irq = gpio_to_irq(0); - gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { + gpio_irq < gpio_to_irq(8); + gpio_irq++) { + irq_set_chip_data(gpio_irq, &epg->gc[0]); + irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, + handle_level_irq); + irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + } + /* The B bank */ + for (gpio_irq = gpio_to_irq(8); + gpio_irq < gpio_to_irq(16); + gpio_irq++) { + irq_set_chip_data(gpio_irq, &epg->gc[1]); + irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, + handle_level_irq); + irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + } + /* The F bank */ + for (gpio_irq = gpio_to_irq(16); + gpio_irq < gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); + gpio_irq++) { + irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, handle_level_irq); irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); } - irq_set_chained_handler(platform_get_irq(pdev, 0), - ep93xx_gpio_ab_irq_handler); + irq_set_chained_handler_and_data(platform_get_irq(pdev, 0), + ep93xx_gpio_ab_irq_handler, + &epg->gc[0]); for (i = 1; i <= 8; i++) - irq_set_chained_handler(platform_get_irq(pdev, i), - ep93xx_gpio_f_irq_handler); + irq_set_chained_handler_and_data(platform_get_irq(pdev, i), + ep93xx_gpio_f_irq_handler, + &epg->gc[i]); } @@ -285,10 +320,11 @@ static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false), }; -static int ep93xx_gpio_set_config(struct gpio_chip *chip, unsigned offset, +static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, unsigned long config) { - int gpio = chip->base + offset; + struct ep93xx_gpio *epg = gpiochip_get_data(gc); + int gpio = gc->base + offset; int irq = gpio_to_irq(gpio); u32 debounce; @@ -299,7 +335,7 @@ static int ep93xx_gpio_set_config(struct gpio_chip *chip, unsigned offset, return -EINVAL; debounce = pinconf_to_config_argument(config); - ep93xx_gpio_int_debounce(irq, debounce ? true : false); + ep93xx_gpio_int_debounce(epg, irq, debounce ? true : false); return 0; } @@ -320,10 +356,11 @@ static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) } static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, - void __iomem *base, struct ep93xx_gpio_bank *bank) + struct ep93xx_gpio *epg, + struct ep93xx_gpio_bank *bank) { - void __iomem *data = base + bank->data; - void __iomem *dir = base + bank->dir; + void __iomem *data = epg->base + bank->data; + void __iomem *dir = epg->base + bank->dir; int err; err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0); @@ -338,7 +375,7 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, gc->to_irq = ep93xx_gpio_to_irq; } - return devm_gpiochip_add_data(dev, gc, NULL); + return devm_gpiochip_add_data(dev, gc, epg); } static int ep93xx_gpio_probe(struct platform_device *pdev) @@ -356,19 +393,17 @@ static int ep93xx_gpio_probe(struct platform_device *pdev) epg->base = devm_ioremap_resource(dev, res); if (IS_ERR(epg->base)) return PTR_ERR(epg->base); - ep93xx_gpio_base = epg->base; for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { struct gpio_chip *gc = &epg->gc[i]; struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; - if (ep93xx_gpio_add_bank(gc, &pdev->dev, - epg->base, bank)) + if (ep93xx_gpio_add_bank(gc, &pdev->dev, epg, bank)) dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", bank->label); } - ep93xx_gpio_init_irq(pdev); + ep93xx_gpio_init_irq(pdev, epg); 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:30 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 05/11] gpio: ep93xx: Rename has_debounce to has_irq Date: Wed, 22 Aug 2018 22:41:05 +0200 Message-Id: <20180822204111.9581-6-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This is closer to what the variable (per bank) actually means. We have the .gpio_to_irq() hook registered only when this is true. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 379f2573f794..a81d1e796912 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -297,25 +297,25 @@ struct ep93xx_gpio_bank { int data; int dir; int base; - bool has_debounce; + bool has_irq; }; -#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \ +#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq) \ { \ .label = _label, \ .data = _data, \ .dir = _dir, \ .base = _base, \ - .has_debounce = _debounce, \ + .has_irq = _has_irq, \ } static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), - EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), + EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), /* Bank A has 8 IRQs */ + EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), /* Bank B has 8 IRQs */ EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false), EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false), EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false), - EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), + EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), /* Bank F has 8 IRQs */ EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false), EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false), }; @@ -370,7 +370,7 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, gc->label = bank->label; gc->base = bank->base; - if (bank->has_debounce) { + if (bank->has_irq) { gc->set_config = ep93xx_gpio_set_config; gc->to_irq = ep93xx_gpio_to_irq; } From patchwork Wed Aug 22 20:41:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 144857 Delivered-To: patch@linaro.org Received: by 2002:a2e:164a:0:0:0:0:0 with SMTP id 10-v6csp401611ljw; Wed, 22 Aug 2018 13:41:37 -0700 (PDT) X-Google-Smtp-Source: AA+uWPwvHPGOkMyFne5nQYR7f57Y7DxW3d8OWSZqxZVubpag9cWMvpznauOWQq4MuwXH5bx9NrZ7 X-Received: by 2002:a63:d916:: with SMTP id r22-v6mr52898629pgg.381.1534970497079; Wed, 22 Aug 2018 13:41:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534970497; cv=none; d=google.com; s=arc-20160816; b=pGwbA+jIB7dhphX5ID8X7mvqhqVqMSivOiUJmz6KOzXv13/sDJCqwgBYLOyUEEU+bY KF9fV8tRw1h62oAAeS1HqGIGB5o/hb2U5MgsTEExjt/QdMOspBYK5sU5BqIzpvzKIx2V tPVjKAzjuE3Jkw3s6AIIvy/AQ6ASPcyGd3AunqWaGnIgRRCAFGsBd7pEqArKgS764NJj SRcuTzRMErzE7dD3+tGj9H/VZn+vYH82lDMB34DLG0hZ7vrIhFRp/jmCp8T+cjuNqjU0 W8uD5ji3XhLZzb3bXAfg/qgluvrrCY84ppVqogmlz6WV/KXFWkM1Fkql+y9iApGKNpxR WIBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=+UwefDXh4P3wfTzsSfvtpWRGxLEovImVzBLhuTW/X0U=; b=xt+heaqotAsnP1qWybk0LzDui9Rp6r09xjvsjYJY48gj6tWsxAFA23e8Pp1fhF5gBa C0OgfMwgjNYwT84d5INxqhxWcmZlKZcKYWHTfJoO3PSGRr0xLhsaDnORNmNQnF2M+zK3 pC+wn40dwtGgg82ZpjpVyKzK0kr/2d8ETDE/SC/pygupNOYH3WPBvszVPwhO7lqh+dmw cEaPisznocCPYs5+nzvls3LSezUZmATI28fyNTBcGu/iPi9sL0uNUM7l1sWrBfI5nFxg 8j2E8hTG0illzcnr1BPhc6o0ai/fMfUD0uJNu3buoBfmgIei4KvDHUjXSdK6+Ylvg0iS z8mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UdBy42H8; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:33 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 06/11] gpio: ep93xx: Properly call the chained IRQ handler Date: Wed, 22 Aug 2018 22:41:06 +0200 Message-Id: <20180822204111.9581-7-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The chained irq handler should call chained_irq_enter() and chained_irq_exit() before/after handling the chained IRQ. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.1 diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index a81d1e796912..ce7e88df9cc5 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -88,9 +88,12 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct ep93xx_gpio *epg = gpiochip_get_data(gc); + struct irq_chip *irqchip = irq_desc_get_chip(desc); unsigned char status; int i; + chained_irq_enter(irqchip, desc); + status = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { @@ -106,6 +109,8 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) generic_handle_irq(gpio_irq); } } + + chained_irq_exit(irqchip, desc); } static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) @@ -115,11 +120,14 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) * * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) */ + struct irq_chip *irqchip = irq_desc_get_chip(desc); unsigned int irq = irq_desc_get_irq(desc); int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ int gpio_irq = gpio_to_irq(16) + port_f_idx; + chained_irq_enter(irqchip, desc); generic_handle_irq(gpio_irq); + chained_irq_exit(irqchip, desc); } static void ep93xx_gpio_irq_ack(struct irq_data *d) From patchwork Wed Aug 22 20:41:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 144858 Delivered-To: patch@linaro.org Received: by 2002:a2e:164a:0:0:0:0:0 with SMTP id 10-v6csp401637ljw; Wed, 22 Aug 2018 13:41:39 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxTBPWvNI74QF+dF4gxWeeJotq7EnQ109TRCFy3rYB+HGtFFMnu+48X1YGhadi7Vg7uD4Ec X-Received: by 2002:a62:d113:: with SMTP id z19-v6mr58812439pfg.98.1534970499435; Wed, 22 Aug 2018 13:41:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534970499; cv=none; d=google.com; s=arc-20160816; b=GcE3UUXUFAqnxEq2x+lU5rwY2JmAXPa1uITDVwMeSf1wEc5vHfiJzfpDUw8FFxVxHV Ib1KK/GMEUbK4shNWQ/sGo54oHAhsVgArWUvPqwa2+oEVICYNCSj+DkWlBIhRYrCS1TH yFGLw9oZBGC8ZWPCgZ2UC3/YZlIZQj03sd2uNt3OBG2gmrSToUn/h5zZQb971AeA2swS JwGWmw5qCX3a134e8MGGtoNCKp5TwXHDbxhXDivNfOYf6hPjqyM9JMbSd8jUCXeoJBJA qCyJgINoszlgq45Oj7ngji548fZrU9S4Ym0lLMkiqZ7amCwhwMF2AICOOtWXy6IIrY1S BRLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=AhUgbQTMYNb/DXLEkmtHE8Vl0sdfXM4cpGNlHdpUM0M=; b=sfsOIW9kwT0TZ5wIja5ZkBZ2RA23Y/CZxg8OQnWGwrvLuk0XC/q2s48iYRpIltvv5X FJYOZpcmAwOC8Poyo1IaYWgCWHou1iqXiiQVwfEc63Q76d0OcaFuL7r0KuLMhLuMYPsg ECENIT68buk+bcMCgyG9MBbUxjo5haFR7rlmOHRDeZRS8YcwpVVK2dBzFyIa6yYNB5yR uCf7JUvAhBPTslxLIe2f6W2uW5qScmxd2AVmgaE5aXZS/la+lO0/wzzlevMgiHvBqBC8 SS0y9lwkTug4Qd/NDo9CI7x/KQXTZwmgKfhugqQLmOXHAE5Kb67SzRsAksLST61gVaiI vQqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b+pdPFNF; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:35 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 07/11] gpio: ep93xx: Do not pingpong irq numbers Date: Wed, 22 Aug 2018 22:41:07 +0200 Message-Id: <20180822204111.9581-8-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org For setting debounce config we want to write an offset in a per-gpiochip register, and we know which gpiochip we are on. Instead of a roundtrip over the IRQ number, figure out what port we are on for this GPIO chip, then index to the right register and write the value. This adds the ep93xx_gpio_port() that finds the port index from a struct gpio_chip * that we can later exploit to simplify more code. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index ce7e88df9cc5..3b235b25c028 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -68,12 +68,29 @@ static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port epg->base + int_en_register_offset[port]); } -static void ep93xx_gpio_int_debounce(struct ep93xx_gpio *epg, - unsigned int irq, bool enable) +static int ep93xx_gpio_port(struct gpio_chip *gc) { - int line = irq_to_gpio(irq); - int port = line >> 3; - int port_mask = 1 << (line & 7); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); + int port = 0; + + while (gc != &epg->gc[port] && port < sizeof(epg->gc)) + port++; + + /* This should not happen but is there as a last safeguard */ + if (gc != &epg->gc[port]) { + pr_crit("can't find the GPIO port\n"); + return 0; + } + + return port; +} + +static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, + unsigned int offset, bool enable) +{ + struct ep93xx_gpio *epg = gpiochip_get_data(gc); + int port = ep93xx_gpio_port(gc); + int port_mask = BIT(offset); if (enable) gpio_int_debounce[port] |= port_mask; @@ -331,19 +348,13 @@ static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, unsigned long config) { - struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int gpio = gc->base + offset; - int irq = gpio_to_irq(gpio); u32 debounce; if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) return -ENOTSUPP; - if (irq < 0) - return -EINVAL; - debounce = pinconf_to_config_argument(config); - ep93xx_gpio_int_debounce(epg, irq, debounce ? true : false); + ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false); return 0; } From patchwork Wed Aug 22 20:41:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 144859 Delivered-To: patch@linaro.org Received: by 2002:a2e:164a:0:0:0:0:0 with SMTP id 10-v6csp401676ljw; Wed, 22 Aug 2018 13:41:42 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdb667bZV3HqRbijFfaecBk95sH7THWmyRkeqFNzDyFGVK4jnwPZ/8khPC9cg/o97brra0Uc X-Received: by 2002:a62:808c:: with SMTP id j134-v6mr8186747pfd.120.1534970502602; Wed, 22 Aug 2018 13:41:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534970502; cv=none; d=google.com; s=arc-20160816; b=H3yQ4Ly7tw4kHF5hRh5LY14U1h0aRJ/LGFvHBx07hv0DIzXzjKu4Jdtnx+HrpXAiDF EKbwB72SCkc0uTjILOihgXglpPFoGUupz/u0YRd+ZP63MyvAq6c4YF/wR4FH6vSA3ntA Zgey/IlMKcLXLF88dRPpfq5jwAVhhFJLFSmHz9jRQKO3yFX4LLK1Pw4lc+kW8IqrzlvT GqWejCZ3jk/JSIThJ5I0S3c+/icaAhDK58VBRabuAiNBtXiAY9xlsYOVRXRign3RChjx zWjPbHJqzqrhZEK/QaKYkm55dF+pzG1oDC3w45kWTlQbihg/cbcBRxWYBUR41Ha9+LTD wjxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=5jyCrEmH3jOgnJsJFUlr60/lZCJAbMRBBSgurEP30XM=; b=cK53o/xUfrvCdJaIRklnDHtw9LKOf6LnHgeUV1pztLBTb9+AsZbhFJHyffpvJ/2vmS 32/y3MHslzN0tHUQVO2e5oHFQHKeVxq5AOdO3tDPJbpioMYAawFg/nHa52Dcuug9YlL2 nD0whfB6Ypa0slLG0kTsgZNM2BGBf/E424/sgBPUEwr5oAel3YPjcsGkvgPNsyP8T5n2 W95WA0Dwb0NANaHOSlUranMFQsSyRE8ipGN11VawghT+2EBoWwxViFn9hVIqLpmqbPQJ zQ8A2XSuNQ3LgRt8Mjr3GbV1S2RzkmYMU5xjZfZs/4JIJxlFF8KCSiR+hfRDn2LQSRdv K4ww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TCMv3sVD; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:38 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 08/11] gpio: ep93xx: Use the hwirq and port Date: Wed, 22 Aug 2018 22:41:08 +0200 Message-Id: <20180822204111.9581-9-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In the IRQ-related functions, switch to using the hwirq and port number found from the current struct gpio_chip * As the lower 3 bits of the IRQ number is identical to the lower 3 bits of the GPIO number we can cut some corners. Call directly into the gpiochip to set up the direction and read the input instead of using the consumer API. This enabled us to cut the confusing irq_to_gpio() macro that is a remnant of the old generic GPIO API as well. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 33 ++++++++++++++------------------- 1 file changed, 14 insertions(+), 19 deletions(-) -- 2.17.1 diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 3b235b25c028..b2139ec43ce2 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -16,11 +16,10 @@ #include #include #include +#include /* FIXME: this is here for gpio_to_irq() - get rid of this! */ #include -#define irq_to_gpio(irq) ((irq) - gpio_to_irq(0)) - #define EP93XX_GPIO_F_INT_STATUS 0x5c #define EP93XX_GPIO_A_INT_STATUS 0xa0 #define EP93XX_GPIO_B_INT_STATUS 0xbc @@ -151,9 +150,8 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int line = irq_to_gpio(d->irq); - int port = line >> 3; - int port_mask = 1 << (line & 7); + int port = ep93xx_gpio_port(gc); + int port_mask = BIT(d->irq & 7); if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { gpio_int_type2[port] ^= port_mask; /* switch edge direction */ @@ -167,9 +165,8 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int line = irq_to_gpio(d->irq); - int port = line >> 3; - int port_mask = 1 << (line & 7); + int port = ep93xx_gpio_port(gc); + int port_mask = BIT(d->irq & 7); if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) gpio_int_type2[port] ^= port_mask; /* switch edge direction */ @@ -184,10 +181,9 @@ static void ep93xx_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int line = irq_to_gpio(d->irq); - int port = line >> 3; + int port = ep93xx_gpio_port(gc); - gpio_int_unmasked[port] &= ~(1 << (line & 7)); + gpio_int_unmasked[port] &= ~BIT(d->irq & 7); ep93xx_gpio_update_int_params(epg, port); } @@ -195,10 +191,9 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int line = irq_to_gpio(d->irq); - int port = line >> 3; + int port = ep93xx_gpio_port(gc); - gpio_int_unmasked[port] |= 1 << (line & 7); + gpio_int_unmasked[port] |= BIT(d->irq & 7); ep93xx_gpio_update_int_params(epg, port); } @@ -211,12 +206,12 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - const int gpio = irq_to_gpio(d->irq); - const int port = gpio >> 3; - const int port_mask = 1 << (gpio & 7); + int port = ep93xx_gpio_port(gc); + int offset = d->irq & 7; + int port_mask = BIT(offset); irq_flow_handler_t handler; - gpio_direction_input(gpio); + gc->direction_input(gc, offset); switch (type) { case IRQ_TYPE_EDGE_RISING: @@ -242,7 +237,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_BOTH: gpio_int_type1[port] |= port_mask; /* set initial polarity based on current input level */ - if (gpio_get_value(gpio)) + if (gc->get(gc, offset)) gpio_int_type2[port] &= ~port_mask; /* falling */ else gpio_int_type2[port] |= port_mask; /* rising */ From patchwork Wed Aug 22 20:41:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 144860 Delivered-To: patch@linaro.org Received: by 2002:a2e:164a:0:0:0:0:0 with SMTP id 10-v6csp401701ljw; Wed, 22 Aug 2018 13:41:45 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyJfX5HNIzQqP9Evx/bAMUZnNKbIK4By2gNrFKHvdFtt4q2Csfi2rerFNCLXMTMz1R4Pf0t X-Received: by 2002:a62:41d6:: with SMTP id g83-v6mr59232598pfd.219.1534970505259; Wed, 22 Aug 2018 13:41:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534970505; cv=none; d=google.com; s=arc-20160816; b=VD8QPm0UpKPmT8xFyGS62ZmXb38SalBRaZdU/ZlYbb/txpH0yLAQTDTiotR+9GC9+H WcQEwq/UZOXHlLu/8FHzNF2NnUjJigh1u6pwixO7flr4XtjroPy6cHDVJ6ZWT8ESQmsP uYFnA0WurtBtt6UGwylGsMn7K+a4OY/LZ2qEFrqRAnJBpJxiorybGKtrVbr/Fc9+FFSu TwaTTS/X3m/jcwzn0oUSuSubX2NFj1RmjZyDadrz4X8tlhJQB58tfv6ohxaFrscg18Ty 1zVSlq8Rn2NaLK+bOjqoa4twxtQ2kNX4sQm7vrtQKT3CCnjIk+iudJUqa8igzvAKe1RC o79A== ARC-Message-Signature: i=1; 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:41 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 09/11] gpio: ep93xx: Use for_each_set_bit() in IRQ handler Date: Wed, 22 Aug 2018 22:41:09 +0200 Message-Id: <20180822204111.9581-10-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This simplifies and standardizes the AB IRQ handler by using the for_each_set_bit() library function. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) -- 2.17.1 diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index b2139ec43ce2..1248d83f860b 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -105,25 +105,21 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct ep93xx_gpio *epg = gpiochip_get_data(gc); struct irq_chip *irqchip = irq_desc_get_chip(desc); - unsigned char status; - int i; + unsigned long stat; + int offset; chained_irq_enter(irqchip, desc); - status = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); - for (i = 0; i < 8; i++) { - if (status & (1 << i)) { - int gpio_irq = gpio_to_irq(0) + i; - generic_handle_irq(gpio_irq); - } + stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); + for_each_set_bit(offset, &stat, 8) { + int gpio_irq = gpio_to_irq(0) + offset; + generic_handle_irq(gpio_irq); } - status = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); - for (i = 0; i < 8; i++) { - if (status & (1 << i)) { - int gpio_irq = gpio_to_irq(8) + i; - generic_handle_irq(gpio_irq); - } + stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); + for_each_set_bit(offset, &stat, 8) { + int gpio_irq = gpio_to_irq(8) + offset; + generic_handle_irq(gpio_irq); } chained_irq_exit(irqchip, desc); From patchwork Wed Aug 22 20:41:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 144861 Delivered-To: patch@linaro.org Received: by 2002:a2e:164a:0:0:0:0:0 with SMTP id 10-v6csp401755ljw; Wed, 22 Aug 2018 13:41:49 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxlfobjDdR6wIAwmHWK78Vm1nHSLkpqKuXCrY8XRxY65EJFNOUYzYsYlrV49vsRv9F1QCx4 X-Received: by 2002:a17:902:6501:: with SMTP id b1-v6mr55648939plk.31.1534970508934; Wed, 22 Aug 2018 13:41:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534970508; cv=none; d=google.com; s=arc-20160816; b=ynO4qrydgkNXNsc0b3sKBfz4s1tdvFCAaaEK2tN3zeqmDUaTQ28Pj4rh6bUWBycovs 9mWT1kV0MTb9kLnj4+j2oobdVarRygdeeCOisBBQOETxvV/maXFq+B93QhLdnucP61lh 4yf57JQh0y+tc0Yu94p7c71YaR9ZwYwcKweLUO87wXkGzI+4qj/UhPZOvGlDd0arWVAB SCgrtr6mQn+7FHPt2fcjwwTKImOr7PsAbFLiAdi6yNd5XGr0bjlBBcI/U79hZOIp0mTq uyD9XdmuOoF8odDnIS6p2kJ1pVZr0a32PN8UqqomVw3xW5vgduQMpXK7vPrf+b0r6WhN 538g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=og9F5K3DV5Z4i7H1Ak0q8ntuvtl8V20+7qYiuklDr38=; b=WlzAXUKYvSuL7vcemJKH7EoteiyIeWxtRr7odsDuyQpREP2vaARYDZMhpTr9uG+7jU Y31zZgGd/hWDHFg8+lL0H4klsLqANVr9QeqRZK72lwotpr0KD0RcmnVfRHuTMX3hmV4U srnpR6ExfTEyE+cMRdkzPyYmkUS++jM7TR9qNuVT+Qm5+EzdUTNzJnxlte7a66uwAyYY agAam0vCbsoWE0TIspZoyv9Dk0Gwe6NKxtVCdkLSWs+lfsOCIt1vZq91wysawuAJrFG4 ObIYdWeyrFh0+qsJ2DXa9p6fRCFOo6qjkg04voMuYwhVta4pAc70JPz8ccQGUE7/kaI/ JoEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RhrllJJ+; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:44 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 10/11] gpio: ep93xx: Cut gpio_to_irq() usage Date: Wed, 22 Aug 2018 22:41:10 +0200 Message-Id: <20180822204111.9581-11-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This removes the callback into the gpiolib creating a circular call to convert between GPIO numbers and IRQs and pushes the whole business into the driver, just using an array of IRQ bases for the three IRQ capable ports. This way we get rid of including that no driver should include. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 48 +++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 1248d83f860b..d45d8ac3b525 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -17,8 +17,6 @@ #include #include #include -/* FIXME: this is here for gpio_to_irq() - get rid of this! */ -#include #define EP93XX_GPIO_F_INT_STATUS 0x5c #define EP93XX_GPIO_A_INT_STATUS 0xa0 @@ -30,6 +28,15 @@ /* Maximum value for irq capable line identifiers */ #define EP93XX_GPIO_LINE_MAX_IRQ 23 +/* + * IRQ numbers used by this driver is 64 ..87 + * + * Map GPIO A0..A7 (0..7) to irq 64..71, + * B0..B7 (7..15) to irq 72..79, and + * F0..F7 (16..24) to irq 80..87. + */ +static unsigned int ep93xx_gpio_irq_base[3] = { 64, 72, 80 }; + struct ep93xx_gpio { void __iomem *base; struct gpio_chip gc[8]; @@ -112,13 +119,13 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); for_each_set_bit(offset, &stat, 8) { - int gpio_irq = gpio_to_irq(0) + offset; + int gpio_irq = ep93xx_gpio_irq_base[0] + offset; generic_handle_irq(gpio_irq); } stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); for_each_set_bit(offset, &stat, 8) { - int gpio_irq = gpio_to_irq(8) + offset; + int gpio_irq = ep93xx_gpio_irq_base[1] + offset; generic_handle_irq(gpio_irq); } @@ -130,12 +137,12 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) /* * map discontiguous hw irq range to continuous sw irq range: * - * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) + * IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7} */ struct irq_chip *irqchip = irq_desc_get_chip(desc); unsigned int irq = irq_desc_get_irq(desc); int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ - int gpio_irq = gpio_to_irq(16) + port_f_idx; + int gpio_irq = ep93xx_gpio_irq_base[2] + port_f_idx; chained_irq_enter(irqchip, desc); generic_handle_irq(gpio_irq); @@ -268,27 +275,24 @@ static void ep93xx_gpio_init_irq(struct platform_device *pdev, int i; /* The A bank */ - for (gpio_irq = gpio_to_irq(0); - gpio_irq < gpio_to_irq(8); - gpio_irq++) { + for (i = 0; i < 8; i++) { + gpio_irq = ep93xx_gpio_irq_base[0] + i; irq_set_chip_data(gpio_irq, &epg->gc[0]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, handle_level_irq); irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); } /* The B bank */ - for (gpio_irq = gpio_to_irq(8); - gpio_irq < gpio_to_irq(16); - gpio_irq++) { + for (i = 0; i < 8; i++) { + gpio_irq = ep93xx_gpio_irq_base[1] + i; irq_set_chip_data(gpio_irq, &epg->gc[1]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, handle_level_irq); irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); } /* The F bank */ - for (gpio_irq = gpio_to_irq(16); - gpio_irq < gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); - gpio_irq++) { + for (i = 0; i < 8; i++) { + gpio_irq = ep93xx_gpio_irq_base[2] + i; irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, handle_level_irq); @@ -350,19 +354,15 @@ static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, return 0; } -/* - * Map GPIO A0..A7 (0..7) to irq 64..71, - * B0..B7 (7..15) to irq 72..79, and - * F0..F7 (16..24) to irq 80..87. - */ -static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +static int ep93xx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) { - int gpio = chip->base + offset; + int port = ep93xx_gpio_port(gc); - if (gpio > EP93XX_GPIO_LINE_MAX_IRQ) + /* Those are the ports supporting IRQ */ + if (port != 0 && port != 1 && port != 5) return -EINVAL; - return 64 + gpio; + return ep93xx_gpio_irq_base[port] + offset; } static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, From patchwork Wed Aug 22 20:41:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 144862 Delivered-To: patch@linaro.org Received: by 2002:a2e:164a:0:0:0:0:0 with SMTP id 10-v6csp401778ljw; Wed, 22 Aug 2018 13:41:51 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzFbxYxez7skEB4ORK0UzAqyI5aDn6lcS6vKyxRV7rogdW1ro5n6dGfvC94KKTgfCLSXzxL X-Received: by 2002:a63:af17:: with SMTP id w23-v6mr18772778pge.47.1534970511364; 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:46 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 11/11] gpio: ep93xx: Switch A and B to use GPIOLIB_IRQCHIP Date: Wed, 22 Aug 2018 22:41:11 +0200 Message-Id: <20180822204111.9581-12-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We can quite easily switch banks/ports A and B to use GPIOLIB_IRQCHIP which is code that will be more careful about handling interrupt descriptors and use a proper irqdomain for translating the IRQs. This cuts down some code in favor of using the implementation inside gpiolib. Signed-off-by: Linus Walleij --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-ep93xx.c | 95 ++++++++++++++++++++------------------ 2 files changed, 51 insertions(+), 45 deletions(-) -- 2.17.1 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 71c0ab46f216..afcd94613017 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -200,6 +200,7 @@ config GPIO_EP93XX def_bool y depends on ARCH_EP93XX select GPIO_GENERIC + select GPIOLIB_IRQCHIP config GPIO_EXAR tristate "Support for GPIO pins on XR17V352/354/358" diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index d45d8ac3b525..68a416fc3141 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -29,13 +29,10 @@ #define EP93XX_GPIO_LINE_MAX_IRQ 23 /* - * IRQ numbers used by this driver is 64 ..87 - * - * Map GPIO A0..A7 (0..7) to irq 64..71, - * B0..B7 (7..15) to irq 72..79, and - * F0..F7 (16..24) to irq 80..87. + * Static mapping of GPIO bank F IRQS: + * F0..F7 (16..24) to irq 80..87. */ -static unsigned int ep93xx_gpio_irq_base[3] = { 64, 72, 80 }; +#define EP93XX_GPIO_F_IRQ_BASE 80 struct ep93xx_gpio { void __iomem *base; @@ -117,17 +114,21 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) chained_irq_enter(irqchip, desc); + /* + * Dispatch the IRQs to the irqdomain of each A and B + * gpiochip irqdomains depending on what has fired. + * The tricky part is that the IRQ line is shared + * between bank A and B and each has their own gpiochip. + */ stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); - for_each_set_bit(offset, &stat, 8) { - int gpio_irq = ep93xx_gpio_irq_base[0] + offset; - generic_handle_irq(gpio_irq); - } + for_each_set_bit(offset, &stat, 8) + generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain, + offset)); stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); - for_each_set_bit(offset, &stat, 8) { - int gpio_irq = ep93xx_gpio_irq_base[1] + offset; - generic_handle_irq(gpio_irq); - } + for_each_set_bit(offset, &stat, 8) + generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain, + offset)); chained_irq_exit(irqchip, desc); } @@ -142,7 +143,7 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) struct irq_chip *irqchip = irq_desc_get_chip(desc); unsigned int irq = irq_desc_get_irq(desc); int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ - int gpio_irq = ep93xx_gpio_irq_base[2] + port_f_idx; + int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx; chained_irq_enter(irqchip, desc); generic_handle_irq(gpio_irq); @@ -268,44 +269,53 @@ static struct irq_chip ep93xx_gpio_irq_chip = { .irq_set_type = ep93xx_gpio_irq_type, }; -static void ep93xx_gpio_init_irq(struct platform_device *pdev, - struct ep93xx_gpio *epg) +static int ep93xx_gpio_init_irq(struct platform_device *pdev, + struct ep93xx_gpio *epg) { + int ab_parent_irq = platform_get_irq(pdev, 0); + struct device *dev = &pdev->dev; int gpio_irq; + int ret; int i; /* The A bank */ - for (i = 0; i < 8; i++) { - gpio_irq = ep93xx_gpio_irq_base[0] + i; - irq_set_chip_data(gpio_irq, &epg->gc[0]); - irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, - handle_level_irq); - irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + ret = gpiochip_irqchip_add(&epg->gc[0], &ep93xx_gpio_irq_chip, + 64, handle_level_irq, + IRQ_TYPE_NONE); + if (ret) { + dev_err(dev, "Could not add irqchip 0\n"); + return ret; } + gpiochip_set_chained_irqchip(&epg->gc[0], &ep93xx_gpio_irq_chip, + ab_parent_irq, + ep93xx_gpio_ab_irq_handler); + /* The B bank */ - for (i = 0; i < 8; i++) { - gpio_irq = ep93xx_gpio_irq_base[1] + i; - irq_set_chip_data(gpio_irq, &epg->gc[1]); - irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, - handle_level_irq); - irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + ret = gpiochip_irqchip_add(&epg->gc[1], &ep93xx_gpio_irq_chip, + 72, handle_level_irq, + IRQ_TYPE_NONE); + if (ret) { + dev_err(dev, "Could not add irqchip 1\n"); + return ret; } + gpiochip_set_chained_irqchip(&epg->gc[1], &ep93xx_gpio_irq_chip, + ab_parent_irq, + ep93xx_gpio_ab_irq_handler); + /* The F bank */ for (i = 0; i < 8; i++) { - gpio_irq = ep93xx_gpio_irq_base[2] + i; + gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i; irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, handle_level_irq); irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); } - irq_set_chained_handler_and_data(platform_get_irq(pdev, 0), - ep93xx_gpio_ab_irq_handler, - &epg->gc[0]); for (i = 1; i <= 8; i++) irq_set_chained_handler_and_data(platform_get_irq(pdev, i), ep93xx_gpio_f_irq_handler, &epg->gc[i]); + return 0; } @@ -354,15 +364,9 @@ static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, return 0; } -static int ep93xx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset) { - int port = ep93xx_gpio_port(gc); - - /* Those are the ports supporting IRQ */ - if (port != 0 && port != 1 && port != 5) - return -EINVAL; - - return ep93xx_gpio_irq_base[port] + offset; + return EP93XX_GPIO_F_IRQ_BASE + offset; } static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, @@ -380,10 +384,8 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, gc->label = bank->label; gc->base = bank->base; - if (bank->has_irq) { + if (bank->has_irq) gc->set_config = ep93xx_gpio_set_config; - gc->to_irq = ep93xx_gpio_to_irq; - } return devm_gpiochip_add_data(dev, gc, epg); } @@ -410,7 +412,10 @@ static int ep93xx_gpio_probe(struct platform_device *pdev) if (ep93xx_gpio_add_bank(gc, &pdev->dev, epg, bank)) dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", - bank->label); + bank->label); + /* Only bank F has especially funky IRQ handling */ + if (i == 5) + gc->to_irq = ep93xx_gpio_f_to_irq; } ep93xx_gpio_init_irq(pdev, epg);