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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id g3sm537368wrv.64.2021.07.07.18.06.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jul 2021 18:06:51 -0700 (PDT) From: Bryan O'Donoghue To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: dmitry.baryshkov@linaro.org, jonathan@marek.ca, robert.foss@linaro.org, bryan.odonoghue@linaro.org Subject: [PATCH 1/2] clk: qcom: camcc-sm8250: Fix absent mmcx regulator reference Date: Thu, 8 Jul 2021 02:08:38 +0100 Message-Id: <20210708010839.692242-2-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210708010839.692242-1-bryan.odonoghue@linaro.org> References: <20210708010839.692242-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The current implementation omits the necessary mmcx supply, which means if you are running the code for this block and a prior clock driver, like say the videocc hasn't run, then a reset will be generated the first time we touch these registers. Fixes: 5d66ca79b58c ("clk: qcom: Add camera clock controller driver for SM8250") Signed-off-by: Bryan O'Donoghue --- drivers/clk/qcom/camcc-sm8250.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.30.1 diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c index 439eaafdcc86..c51112546bfc 100644 --- a/drivers/clk/qcom/camcc-sm8250.c +++ b/drivers/clk/qcom/camcc-sm8250.c @@ -2212,6 +2212,7 @@ static struct gdsc bps_gdsc = { }, .flags = HW_CTRL | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, + .supply = "mmcx", }; static struct gdsc ipe_0_gdsc = { @@ -2221,6 +2222,7 @@ static struct gdsc ipe_0_gdsc = { }, .flags = HW_CTRL | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, + .supply = "mmcx", }; static struct gdsc sbi_gdsc = { @@ -2230,6 +2232,7 @@ static struct gdsc sbi_gdsc = { }, .flags = HW_CTRL | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, + .supply = "mmcx", }; static struct gdsc ife_0_gdsc = { @@ -2239,6 +2242,7 @@ static struct gdsc ife_0_gdsc = { }, .flags = POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, + .supply = "mmcx", }; static struct gdsc ife_1_gdsc = { @@ -2248,6 +2252,7 @@ static struct gdsc ife_1_gdsc = { }, .flags = POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, + .supply = "mmcx", }; static struct gdsc titan_top_gdsc = { @@ -2257,6 +2262,7 @@ static struct gdsc titan_top_gdsc = { }, .flags = POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, + .supply = "mmcx", }; static struct clk_regmap *cam_cc_sm8250_clocks[] = { From patchwork Thu Jul 8 01:08:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 471207 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6537027jao; Wed, 7 Jul 2021 18:07:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyukIxXjBMqptepWXWpQyEF3GxeZ6jWPDTA2h6i13LaaaBZKzKNNKRfCpfBXW09UYuHF8Y1 X-Received: by 2002:a05:6402:1655:: with SMTP id s21mr34297239edx.295.1625706422368; Wed, 07 Jul 2021 18:07:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625706422; cv=none; d=google.com; s=arc-20160816; b=IpnNbAcANwEDburNKxFpaDUCGN01p7jMEG3J3KcMJDkX5oypyzQZd6QE8MwdWySFqW g7KFmPBrdioMohzwy8+OdUmz0wRynsmMtC8RnVgSW7XrcgCFKiPVwohwU9VPzFcALRe3 7asm0xRg2B6wgeqly7RCZTMp9D6c2Zz24FYHHw3OHtUSelfTQK7RXYirsNb/+WHrhwh7 y3dS26XRnF1dX4pJRlSg0+u2sylXJcKQMcJsBO0FO9CBEvDyNniVrsON8NE0YI/f5WJj ErZQKUvkfRWsSdgcNyuveI3gcdUpnXV+nde8vkpZb2M8FU/Rjl3WgNRZVGqFoad0PEct CFRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=L18azrwFyoptGIEYIWz4nD01VfhinXc3JMH8ke/EdqU=; b=eYbPVPzHh5ewvOTKaCrbW7RemRXwvpheBBno5HesmG0JANChGR2hhxXnztH2mcEXdh 8i0oap/fYwTHIyYNHSZeTuLqyGsie+R8Fgv7EiNBMI8FdC7rUtzdGar0pmoTaQyVungZ taoPcmCSM8WdQB5i3RiJaGs1Xhpvuz1/3uX6IzgnjW21xJHhdMzu1f7QOXi4iDjDj/2q YxbjdfXeSLEfMx4NUJeBwdhq/2Q6gZaG5VfnaEX63SsYrFnDp7cLwWsA+0RfdA5/0WvR Q02kvADpLYzZJEQV8TWH9c/qHK6O65zcvECy1mVvUEe4rjP+51vGv6XvDng7TuCdgi0S Q3IQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zSlPWvWx; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id g3sm537368wrv.64.2021.07.07.18.06.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jul 2021 18:06:52 -0700 (PDT) From: Bryan O'Donoghue To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: dmitry.baryshkov@linaro.org, jonathan@marek.ca, robert.foss@linaro.org, bryan.odonoghue@linaro.org Subject: [PATCH 2/2] arm64: dts: qcom: sm8250: Add camcc DT node Date: Thu, 8 Jul 2021 02:08:39 +0100 Message-Id: <20210708010839.692242-3-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210708010839.692242-1-bryan.odonoghue@linaro.org> References: <20210708010839.692242-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the camcc DT node for the Camera Clock Controller on sm8250. Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.30.1 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4c0de12aaba6..7ac6ae50779c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -2369,6 +2370,19 @@ videocc: clock-controller@abf0000 { #power-domain-cells = <1>; }; + clock_camcc: clock-controller@ad00000 { + compatible = "qcom,sm8250-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; + mmcx-supply = <&mmcx_reg>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sdm845-mdss"; reg = <0 0x0ae00000 0 0x1000>;