From patchwork Fri Aug 24 09:20:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 144996 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1064945ljw; Fri, 24 Aug 2018 02:21:00 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZWG19/3cYzOEIRAbSoIZnK/czIs9aiB3sQHHUGcunCBYNfU7swF44ajM2ub7tWNVgUDVmI X-Received: by 2002:a17:902:4d45:: with SMTP id o5-v6mr902892plh.78.1535102460717; Fri, 24 Aug 2018 02:21:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535102460; cv=none; d=google.com; s=arc-20160816; b=zrnAMBoRmC+kK4q7g92IlffrqwXWMbNG2pRc6N0Ub0u3ly/EJDEvArz86BEKi5YXy1 qFQ3/3ofvJhCnwn2bmGd32JCtD9FbK65IDnnxMC4kW5Zbyzvz5QjQobXBBRQASgmNF9O 3sRDzMmLb6+6v4pDF5Vv+ypvAwdMDyWmqpcCXFbIn61DeFqRm+azxucslenE0gotLzCX 7a+untlwxa75c4F+JMVk+ybTY6Aj3sXmhSzNOxHFqVwyO1msdu9M8w0mKuWgXdLmmjvf PKHId5B91aXqgc8y9vXyGBaSSjlpx2JxW6JuAIicIbZQ77pSuAZMbB5g5qcCzTpf6V3X PsDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=vGFW0eksYTgAicHNEinOVTwkCq1QSfxHTkyhgrrD8X0=; b=Yi/dLLLJ/S2axrAmDSpVqxZAqfdh/jHJF6/ICkKRDZHxWsI+vvr1r2WVArGIGpaVAl Fb7m0RRnloZ+sY7JyRjf7680NKrQW67OsmZgusQDrXRoiAcIUyNv1lVIh27lke698wAf ctf1KJMg6Ceg7whkRADLH/9yJDTudyNHGnee4MPSN8RJFUqU9tWId5lAoDAYbHyn4Vmx YgQEUP1X7yu1v4R95hhK9919KgNPv75e3FInbsB4on8RfJgNPIZa18lGk0fGaiAw8kYs yTHFFKvUgLI98Jc7xhVRCGGwNt8UYnQLfByU1UiFKdWsT+sp3lxNEK28sZ5e/mi+YUMh qOoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cxqy8bF4; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x7-v6si5669010pgi.465.2018.08.24.02.21.00; Fri, 24 Aug 2018 02:21:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cxqy8bF4; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727621AbeHXMyp (ORCPT + 5 others); Fri, 24 Aug 2018 08:54:45 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:45866 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726776AbeHXMyp (ORCPT ); Fri, 24 Aug 2018 08:54:45 -0400 Received: by mail-pg1-f195.google.com with SMTP id m4-v6so3514691pgv.12 for ; Fri, 24 Aug 2018 02:20:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vGFW0eksYTgAicHNEinOVTwkCq1QSfxHTkyhgrrD8X0=; b=cxqy8bF4frF/YyPA7ZMy11XROdwuJUAytF1f546o4eP/E87a262731O8XyfvKfwWOU bV86wioiIhKP8hF1CTAfgDrUjHXdsFAUw5aeRCJBKJwjZPJn/zVBSAJxFsvbnzdtJIHq 5NgTJ77HP4yI5DukUy8XHZZeJoTP03agdCXnY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vGFW0eksYTgAicHNEinOVTwkCq1QSfxHTkyhgrrD8X0=; b=o6SYiVduiGHs11G+oifP/4aNWx/PJM4tRBpbYXFwu1zD97Re4zt84LhXoXOJ9DQBEd MbTT9VbuvWPndhCx9lwSnc7imbFCFzEfafyipW0wosLUUlvJgG05pDobhnd8p0y5gs+M CCPWzO52NhKbcbQIs73GzN6JIRfHtXTsPo3m8qjVbvjYGt815h7jEui9gsIsRbKd2u0Z Fpi3LW/xLx8rygGNKkvvp/yK+5ea8PKyOzwYgg75TvayuM8l40NUBgp7Rpw4TPs/2Bmo rl+3WAQAAs5N2tKvmIOBYRwCkbHN6q4RZIfQj4K9k7t8gUbWmB/Eelr98VSq44Gex2/g /PNw== X-Gm-Message-State: APzg51CnRPxdfDwhYDV2zjJ/AjgccoIkfRFSJ0BL5xS9/kkC/B897fdg Zpqbqw2Mszc/DTbj4zQ+Sxx+gA== X-Received: by 2002:a63:d946:: with SMTP id e6-v6mr910039pgj.24.1535102458765; Fri, 24 Aug 2018 02:20:58 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id g6-v6sm9520314pfb.11.2018.08.24.02.20.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Aug 2018 02:20:57 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V6 2/9] mmc: sdhci: Add sd host v4 mode Date: Fri, 24 Aug 2018 17:20:21 +0800 Message-Id: <1535102428-20332-3-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> References: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org For SD host controller version 4.00 or later ones, there're two modes of implementation - Version 3.00 compatible mode or Version 4 mode. This patch introduced an interface to enable v4 mode. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 29 +++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.h | 3 +++ 2 files changed, 32 insertions(+) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index f70135c..a50842c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -123,6 +123,29 @@ EXPORT_SYMBOL_GPL(sdhci_dumpregs); * * \*****************************************************************************/ +static void sdhci_do_enable_v4_mode(struct sdhci_host *host) +{ + u16 ctrl2; + + ctrl2 = sdhci_readb(host, SDHCI_HOST_CONTROL2); + if (ctrl2 & SDHCI_CTRL_V4_MODE) + return; + + ctrl2 |= SDHCI_CTRL_V4_MODE; + sdhci_writeb(host, ctrl2, SDHCI_HOST_CONTROL); +} + +/* + * This can be called before sdhci_add_host() by Vendor's host controller + * driver to enable v4 mode if supported. + */ +void sdhci_enable_v4_mode(struct sdhci_host *host) +{ + host->v4_mode = true; + sdhci_do_enable_v4_mode(host); +} +EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); + static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) { return cmd->data || cmd->flags & MMC_RSP_BUSY; @@ -252,6 +275,9 @@ static void sdhci_init(struct sdhci_host *host, int soft) else sdhci_do_reset(host, SDHCI_RESET_ALL); + if (host->v4_mode) + sdhci_do_enable_v4_mode(host); + sdhci_set_default_irqs(host); host->cqe_on = false; @@ -3371,6 +3397,9 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) sdhci_do_reset(host, SDHCI_RESET_ALL); + if (host->v4_mode) + sdhci_do_enable_v4_mode(host); + of_property_read_u64(mmc_dev(host->mmc)->of_node, "sdhci-caps-mask", &dt_caps_mask); of_property_read_u64(mmc_dev(host->mmc)->of_node, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 7ae95f8..131d869 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -184,6 +184,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -504,6 +505,7 @@ struct sdhci_host { bool preset_enabled; /* Preset is enabled */ bool pending_reset; /* Cmd/data reset is pending */ bool irq_wake_enabled; /* IRQ wakeup is enabled */ + bool v4_mode; /* Host Version 4 Enable */ struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ struct mmc_command *cmd; /* Current command */ @@ -751,5 +753,6 @@ bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, int *data_error); void sdhci_dumpregs(struct sdhci_host *host); +void sdhci_enable_v4_mode(struct sdhci_host *host); #endif /* __SDHCI_HW_H */ From patchwork Fri Aug 24 09:20:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 144997 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1065265ljw; Fri, 24 Aug 2018 02:21:26 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbRvR48fKOBwZJA6kPP8KRZJ5NA/uusFDV4Rgmzf6e2VxICQ99rA9AiL8fWei1VLuovp1ki X-Received: by 2002:a65:6243:: with SMTP id q3-v6mr868842pgv.273.1535102486582; Fri, 24 Aug 2018 02:21:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535102486; cv=none; d=google.com; s=arc-20160816; b=tmKCHQZO3Uomy1gS/5+qddWoKokLXi5homnrCEOpkGUL0qUv6ctsujeTsEbEpr9gN1 DJX+gww8qz2S8OS2lnSf0AHh7YN7aXSr7AmPZ/JvcgiTmUdmmHURcCZLporcyQQtQxc3 i1SaFZfdAqVPlzIlzC96oQa+SroEDiIWAk1+a/e72hVn0RKuE2kmrN1szlIPgBFL7dHk xN9JPSFrQdIucspfL6SEkY4EyX70la8ZqydzbXO1F/nhXpwMdoArPpCMRHkWVKKDdnpu DNGPWCyht71b8mcGXyXdEPy6OZV/0mmtp9HP4AaUyRdsVB3pCAKviFTVlCmVf8fHjWDx +zoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=VLyWTs4wkn6Lk1EZkxQq2kCYTxna3ww596giwJ8qsjk=; b=yv4SLThCoXaWVBXve73/3xVqw/XX//VMuJIi8q8r65leYu0Nd/s+3bKGNY51ybjaby h1iA2/sjczD8m+28EWBpF9Tb8nypdufUtvKf1loLL3lRWFr9txYXNcMcH7kymcPbyiWB zkClRfRBgy5we843ytf+7gaB4tx+MMQeb2BmM5iE+QexSsC7hIavi2vk1FHJfONvmNsn kSkrvHA7WeiuL1L+jfYSTI929CrdYliR0S7LcQcN6t1DcbcPxG8pZ5NUBJSPElp/Zhji VnFntruWiyY8xSdsTFUrE+yaAfjIWd0+MgdG+P1HpPI1GHnhbGhRFW0eVAC+wv7XjBHn PEsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eaSFFO0r; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c5-v6si6263210pgk.327.2018.08.24.02.21.26; Fri, 24 Aug 2018 02:21:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eaSFFO0r; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726770AbeHXMzL (ORCPT + 5 others); Fri, 24 Aug 2018 08:55:11 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:40875 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726407AbeHXMzK (ORCPT ); Fri, 24 Aug 2018 08:55:10 -0400 Received: by mail-pl1-f195.google.com with SMTP id s17-v6so848838plp.7 for ; Fri, 24 Aug 2018 02:21:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VLyWTs4wkn6Lk1EZkxQq2kCYTxna3ww596giwJ8qsjk=; b=eaSFFO0rjDeVblmfXrJh6DRbfNO94vDFPn62rsymhsBfMK7eMwJ4Mtzd7Qut8sn/c/ gtwc6jmiRkAe3iYjMptFUqsw7KpmBZOR31Fc8GBX4AVxuAYUJjKUF85eHtb3yD/io+4V H9D+YMhP+kY4utkm8/zLIc5B3CYzdl3VXlfMA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VLyWTs4wkn6Lk1EZkxQq2kCYTxna3ww596giwJ8qsjk=; b=WoH4s3cuzuXZWUdnncP5hiGg2+o20B2aSW18A5x16aV3A/t6ek3K3nb5g9SXqbk/S2 Qjr1GsXDzZbISA6+QbT546VckvSdkz1uITaJ5bp82l2dJetvuhtfavY0OUo6mqDBbz0+ GxsM2dIuFjU2NztbVU5+Usd1BHPxi8ZW0sYt2bzB7bowxxbFLmiy8HWY18Tw91dkn6gn L1GGdKP7PgRPOJgm3yfMhBMBy33hqPyNOLFEx8FogBNNWq3aON9xKmYvI125ofpctyUn W90F1eCMx9enIUeCwV2DWwPNEg4GdpZPB4JpUW4hWb2NDL4zbfiDlJ4MbwoKEGlLvhnn cp+w== X-Gm-Message-State: APzg51AEd1hMouuL8TV2Uro8RFsjy18SIbm0je5mWUMOFnxnXsXB7wdf f5FIR7+KZ8y30o+pIo6d+6kA7w== X-Received: by 2002:a17:902:4324:: with SMTP id i33-v6mr865592pld.43.1535102485071; Fri, 24 Aug 2018 02:21:25 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id g6-v6sm9520314pfb.11.2018.08.24.02.21.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Aug 2018 02:21:24 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V6 3/9] mmc: sdhci: Change SDMA address register for v4 mode Date: Fri, 24 Aug 2018 17:20:22 +0800 Message-Id: <1535102428-20332-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> References: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org According to the SD host controller specification version 4.10, when Host Version 4 is enabled, SDMA uses ADMA System Address register (05Fh-058h) instead of using SDMA System Address register to support both 32-bit and 64-bit addressing. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index a50842c..df283ca 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -727,7 +727,7 @@ static void sdhci_adma_table_post(struct sdhci_host *host, } } -static u32 sdhci_sdma_address(struct sdhci_host *host) +static dma_addr_t sdhci_sdma_address(struct sdhci_host *host) { if (host->bounce_buffer) return host->bounce_addr; @@ -735,6 +735,17 @@ static u32 sdhci_sdma_address(struct sdhci_host *host) return sg_dma_address(host->data->sg); } +static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr) +{ + if (host->v4_mode) { + sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS); + if (host->flags & SDHCI_USE_64_BIT_DMA) + sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI); + } else { + sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); + } +} + static unsigned int sdhci_target_timeout(struct sdhci_host *host, struct mmc_command *cmd, struct mmc_data *data) @@ -994,8 +1005,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) SDHCI_ADMA_ADDRESS_HI); } else { WARN_ON(sg_cnt != 1); - sdhci_writel(host, sdhci_sdma_address(host), - SDHCI_DMA_ADDRESS); + sdhci_set_sdma_addr(host, sdhci_sdma_address(host)); } } @@ -2823,7 +2833,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) * some controllers are faulty, don't trust them. */ if (intmask & SDHCI_INT_DMA_END) { - u32 dmastart, dmanow; + dma_addr_t dmastart, dmanow; dmastart = sdhci_sdma_address(host); dmanow = dmastart + host->data->bytes_xfered; @@ -2831,12 +2841,12 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) * Force update to the next DMA block boundary. */ dmanow = (dmanow & - ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + + ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + SDHCI_DEFAULT_BOUNDARY_SIZE; host->data->bytes_xfered = dmanow - dmastart; - DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n", - dmastart, host->data->bytes_xfered, dmanow); - sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); + DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n", + &dmastart, host->data->bytes_xfered, &dmanow); + sdhci_set_sdma_addr(host, dmanow); } if (intmask & SDHCI_INT_DATA_END) { @@ -3583,8 +3593,8 @@ int sdhci_setup_host(struct sdhci_host *host) } } - /* SDMA does not support 64-bit DMA */ - if (host->flags & SDHCI_USE_64_BIT_DMA) + /* SDMA does not support 64-bit DMA if v4 mode not set */ + if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode) host->flags &= ~SDHCI_USE_SDMA; if (host->flags & SDHCI_USE_ADMA) { From patchwork Fri Aug 24 09:20:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 144998 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1065359ljw; Fri, 24 Aug 2018 02:21:35 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYSTQAaAbW+050+U31sLfPdTO7BuhiDhKVEgNDN6/NALWk18NXIfdij5MT17fOPMP/iojRu X-Received: by 2002:a62:4bc6:: with SMTP id d67-v6mr1026738pfj.175.1535102495127; Fri, 24 Aug 2018 02:21:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535102495; cv=none; d=google.com; s=arc-20160816; b=L05Sg92dBokIeJ2YRP+p29jmEcgKIZYFBPGCFScnYN3Byp/RLnFLdiNU6LmjF6LuP+ zHFJ6xjotM1RDJeAWbVXGUntAXmCaj8YNsoUks1yH4DHhJ01Uim8nOi5LPn5kQeB95RX naiFX1+yoF/BVcv3mg8vxRQ93ZeNDU3fVT6Fpr1wK+1AiAs8GLS6BsrYHwL9B2eYtDS1 DOpGPxs67dJagWl/jWZxqICjUv1+8HrbhjtRn0yF/xgKh3eu2k6jPGK9qthdTsTqb0/X kOxtQ8+irzRYmheyPShfBCNMiPu+/+PiNI6likKUiYhEuFsStUvO68vrqhVV4UwbGaqN pu0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=V5KxzKbPEKh15VckZhi+wrWCuks4RPVSThG8QwbL0Z8=; b=y/1SerClKeQ+da0LZ4ipq8nQEovL+MXkH+eayQIFQRSLprbGsyGZz6aSrfPa/kYU5p 0paoot13Fa4bay0nLTkcIzsuHBEYG/CuXZU2YNnxQ9ToRfm5oz4HWLNrNULu6S1/YrMm T4EW6aPkArJsQUvWG2uNMLLsECW7m/7C48fqow0mJtct7/0J2g+oMm8H/J9dGV6gFqt+ IlFEyTVQK2DK3HHlkKGGfECzSyvIvvl+LUPpshAL30/Gp3/451/vhKf3Z1orSEO+hCQo 7eCIJedaVYZofmtMefmbi4Epbh/7WQGpIl/ybakgC+6Z5zAepYD3P5/424spd40zXqnp jmZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TE1oNf5h; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a3-v6si6421805pld.123.2018.08.24.02.21.34; Fri, 24 Aug 2018 02:21:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TE1oNf5h; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727780AbeHXMzT (ORCPT + 5 others); Fri, 24 Aug 2018 08:55:19 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:44674 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726871AbeHXMzT (ORCPT ); Fri, 24 Aug 2018 08:55:19 -0400 Received: by mail-pg1-f195.google.com with SMTP id r1-v6so4031278pgp.11 for ; Fri, 24 Aug 2018 02:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V5KxzKbPEKh15VckZhi+wrWCuks4RPVSThG8QwbL0Z8=; b=TE1oNf5hN18R8DBmmI2wVeB1mB7plVYjeYeFN2BImp3b2ZMEGYjuZBTaXoxKaQaPHv 3JuUqWALeppdZ5MNaB+TsWGz/gQV8w0oH5eOmC1kPQ57c68+uCUXoWey/KPlnhHJyGA4 LpuWF/2NPyRO4w6PWfWweE0eObmZdh7o+y+so= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V5KxzKbPEKh15VckZhi+wrWCuks4RPVSThG8QwbL0Z8=; b=n35FzezpADHUsOg8OiI5G9DWGO+YS+QyCljdQWU3SUufeyUQ0MB2qOSJZ8t2SIO7Xq PzSQTzJPezIEV8x9ngFAf2Krat0/Wnurg70ZAgcvegQfX0okuf3dEmkmaMtrAjJN1aRF pPeSfMSZTus2iyXDuxraAufPwusNc83Y2ki4r5KICWVKB97rSBylDY9S1NknW21Y2KFP fttVpuZszynihnFCQKUryz3owXu8bVybgzi9+a8K8inaHHhFC8Ng8ygl0RhhrpV7+Kd+ ZyY0vJZ2MxOqMKxMEPbj7xHJYIkK0FS/0GClJoxvD2F1ToF/1qbVRCxx92EWhPnxZmVL Degg== X-Gm-Message-State: APzg51ClCb70JjESxhYBUWJIDdaEkrrYXtggK8P851zxDMIxmdT5K0r/ +TdIZPlzsXg+inu76tcVP2DqQg== X-Received: by 2002:a63:4104:: with SMTP id o4-v6mr905316pga.146.1535102493307; Fri, 24 Aug 2018 02:21:33 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id g6-v6sm9520314pfb.11.2018.08.24.02.21.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Aug 2018 02:21:32 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V6 4/9] mmc: sdhci: Add ADMA2 64-bit addressing support for V4 mode Date: Fri, 24 Aug 2018 17:20:23 +0800 Message-Id: <1535102428-20332-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> References: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 92 +++++++++++++++++++++++++++++++++++------------- drivers/mmc/host/sdhci.h | 12 +++++-- 2 files changed, 78 insertions(+), 26 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index df283ca..38d083c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -266,6 +266,52 @@ static void sdhci_set_default_irqs(struct sdhci_host *host) sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); } +static void sdhci_config_dma(struct sdhci_host *host) +{ + u8 ctrl; + u16 ctrl2; + + if (host->version < SDHCI_SPEC_200) + return; + + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + + /* + * Always adjust the DMA selection as some controllers + * (e.g. JMicron) can't do PIO properly when the selection + * is ADMA. + */ + ctrl &= ~SDHCI_CTRL_DMA_MASK; + if (!(host->flags & SDHCI_REQ_USE_DMA)) + goto out; + + /* Note if DMA Select is zero then SDMA is selected */ + if (host->flags & SDHCI_USE_ADMA) + ctrl |= SDHCI_CTRL_ADMA32; + + if (host->flags & SDHCI_USE_64_BIT_DMA) { + /* + * If v4 mode, all supported DMA can be 64-bit addressing if + * controller supports 64-bit system address, otherwise only + * ADMA can support 64-bit addressing. + */ + if (host->v4_mode) { + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 |= SDHCI_CTRL_64BIT_ADDR; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + } else if (host->flags & SDHCI_USE_ADMA) { + /* + * Don't need to undo SDHCI_CTRL_ADMA32 in order to + * set SDHCI_CTRL_ADMA64. + */ + ctrl |= SDHCI_CTRL_ADMA64; + } + } + +out: + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + static void sdhci_init(struct sdhci_host *host, int soft) { struct mmc_host *mmc = host->mmc; @@ -913,7 +959,6 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { - u8 ctrl; struct mmc_data *data = cmd->data; host->data_timeout = 0; @@ -1009,25 +1054,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) } } - /* - * Always adjust the DMA selection as some controllers - * (e.g. JMicron) can't do PIO properly when the selection - * is ADMA. - */ - if (host->version >= SDHCI_SPEC_200) { - ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); - ctrl &= ~SDHCI_CTRL_DMA_MASK; - if ((host->flags & SDHCI_REQ_USE_DMA) && - (host->flags & SDHCI_USE_ADMA)) { - if (host->flags & SDHCI_USE_64_BIT_DMA) - ctrl |= SDHCI_CTRL_ADMA64; - else - ctrl |= SDHCI_CTRL_ADMA32; - } else { - ctrl |= SDHCI_CTRL_SDMA; - } - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); - } + sdhci_config_dma(host); if (!(host->flags & SDHCI_REQ_USE_DMA)) { int flags; @@ -3504,6 +3531,19 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) return 0; } +static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) +{ + /* + * According to SD Host Controller spec v4.10, bit[27] added from + * version 4.10 in Capabilities Register is used as 64-bit System + * Address support for V4 mode. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) + return host->caps & SDHCI_CAN_64BIT_V4; + + return host->caps & SDHCI_CAN_64BIT; +} + int sdhci_setup_host(struct sdhci_host *host) { struct mmc_host *mmc; @@ -3575,7 +3615,7 @@ int sdhci_setup_host(struct sdhci_host *host) * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to * implement. */ - if (host->caps & SDHCI_CAN_64BIT) + if (sdhci_can_64bit_dma(host)) host->flags |= SDHCI_USE_64_BIT_DMA; if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { @@ -3609,8 +3649,8 @@ int sdhci_setup_host(struct sdhci_host *host) */ if (host->flags & SDHCI_USE_64_BIT_DMA) { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * - SDHCI_ADMA2_64_DESC_SZ; - host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + SDHCI_ADMA2_64_DESC_SZ(host); + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); } else { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * SDHCI_ADMA2_32_DESC_SZ; @@ -3618,7 +3658,11 @@ int sdhci_setup_host(struct sdhci_host *host) } host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; - buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + + /* + * Use zalloc to zero the reserved high 32-bits of 128-bit + * descriptors so that they never need to be written. + */ + buf = dma_zalloc_coherent(mmc_dev(mmc), host->align_buffer_sz + host->adma_table_sz, &dma, GFP_KERNEL); if (!buf) { pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 131d869..f3b9ebc 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -185,6 +185,7 @@ #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 #define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -205,6 +206,7 @@ #define SDHCI_CAN_VDD_330 0x01000000 #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 #define SDHCI_SUPPORT_SDR50 0x00000001 @@ -309,8 +311,14 @@ struct sdhci_adma2_32_desc { */ #define SDHCI_ADMA2_DESC_ALIGN 8 -/* ADMA2 64-bit DMA descriptor size */ -#define SDHCI_ADMA2_64_DESC_SZ 12 +/* + * ADMA2 64-bit DMA descriptor size + * According to SD Host Controller spec v4.10, there are two kinds of + * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit + * Descriptor, if Host Version 4 Enable is set in the Host Control 2 + * register, 128-bit Descriptor will be selected. + */ +#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte From patchwork Fri Aug 24 09:20:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145001 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1065536ljw; Fri, 24 Aug 2018 02:21:49 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaOkRsCjzg8r6jzWXOeGIX99cmZbHvcRblX8oytvzI93L29AvTN2sixRSeulF1HFpcGcgJB X-Received: by 2002:a63:4207:: with SMTP id p7-v6mr879282pga.201.1535102509726; Fri, 24 Aug 2018 02:21:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535102509; cv=none; d=google.com; s=arc-20160816; b=WuTGSvi/5r160jvvDPZtxpCF6qTI3+A1uGMcBbpEQFoJcCiv3kgOmtFbjZ4s7qZ01M 0UwgGRrNwRyoMv5YJFldEpI7nUcoDKSZh5WnQule1NWu5jPYkpFPjFS4WWdAPyVnqX0Q rcomHIWFv2HExWzyYlwPfwg/YG8jjR1h6FGX1bNMBt9ZiEUd2wdWXfnxbcS0ZjDzuW2s vBplOBCvHEgKJmOjqzTfiIRhvCOCMHILpHmoGEFqk0a7h8ydC1m4nbN1XHq9kcnpEWGY +WJ7rNtyi3HeiMgx/P8Fire9dlRCXdXZ3hhRIFxLbNatUyiaga0UKPSUNKHMprvySpnP 47tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=F8ycUMm5cEF7zHqTC/mFHa7ECSePE1v/XI0xbfy/QLA=; b=OuQgF7LF74BWGQPmaBwoBBeq32gYJQ443XIiMz3e1/2H04Yh89ojroPSXlw/HSQHLo ELYltb0DJryvVK2Gk2qhrBV17odhXMXbpT36WDQ0D/V+cn7d9CP+Y79ZCl4XxZspihD9 eAQyKuSC59y/BUHIf2wSJAAj0qwgW5YV5KDCuL2O/gx/OrHvvn3QJL1v4HFOksnqrzv0 QSp3G3ZsgvGoB+2Vw0ahAfWTNiFdD4/a58Ycp7zkcZv0pHy0Yvx3RDvy/5ywBTcGsLEE i3+NMFwF9P0LDI15K48tmrMn+fWEq7PEty3XMoYuM/nVMnNAHtg+NdJ5JyGzesZCc89K 4JqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z7qPe3TH; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ay10-v6si6389276plb.293.2018.08.24.02.21.49; Fri, 24 Aug 2018 02:21:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z7qPe3TH; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727524AbeHXMze (ORCPT + 5 others); Fri, 24 Aug 2018 08:55:34 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:37187 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727252AbeHXMzd (ORCPT ); Fri, 24 Aug 2018 08:55:33 -0400 Received: by mail-pf1-f194.google.com with SMTP id h69-v6so4270238pfd.4 for ; Fri, 24 Aug 2018 02:21:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F8ycUMm5cEF7zHqTC/mFHa7ECSePE1v/XI0xbfy/QLA=; b=Z7qPe3THEZioTqfmBT0VRxkEuJMLizX/DerVHLOSNrZCI2MSmODuw9sjtk9OfJ9+Fl D/qHOUKLUXODKZ8UbB/cFmv8tgDt7hNumQhM5lErvlyvQQ22+27KkijbhMKYB4B20VXc GgTu5PWE3jdRUwaT4fezdVhVpGHqKJbGnQQyA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F8ycUMm5cEF7zHqTC/mFHa7ECSePE1v/XI0xbfy/QLA=; b=FGG1gDIrza266gG/46HQvfHcy6t4028r7iYFwdLx8ppB84RS3Fw3o1IePbPLLE1XJ4 i4rTZh4o4+bthSvJ2XVccqr8eENkFfIlg1m0N0qiY1Oa3SHfTSYIFinvpbPAJMrJAXHJ J2YNPI7AXkZAheDJSkSUIBddxdtRu74OZWst0REkY0hycoLLpLrh1BBLzA4wxQBMzjSg o4LKo3UHaGXcVW+RUWjLBZ74mv9/L2ddMbPL0iHITaKc5U3aOMzi4CkVtOJM3hk/NLVd uqO4V4uEnEGSXTw+tj6ujZjK0pHJuW8LUoTy02dpdeRceEUA07pRviDhmI68L3Ld6rEI MasA== X-Gm-Message-State: APzg51BELG+AwQyt07wBKavaSWm+Qi+sao6yDartYfEstlIC7oYq77+p JhAF5kmxfsqI8hAQv1OmBnCJoA== X-Received: by 2002:a63:1c07:: with SMTP id c7-v6mr888654pgc.109.1535102507976; Fri, 24 Aug 2018 02:21:47 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id g6-v6sm9520314pfb.11.2018.08.24.02.21.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Aug 2018 02:21:47 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V6 7/9] mmc: sdhci: SDMA may use Auto-CMD23 in v4 mode Date: Fri, 24 Aug 2018 17:20:26 +0800 Message-Id: <1535102428-20332-8-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> References: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address register (05Fh-058h) instead of using register (000h-004h) to indicate its system address of data location. The register (000h-004h) is re-assigned to 32-bit Block Count and Auto CMD23 argument, so then SDMA may use Auto CMD23. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 7e01601..1cb55f2 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3828,10 +3828,14 @@ int sdhci_setup_host(struct sdhci_host *host) if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) host->flags |= SDHCI_AUTO_CMD12; - /* Auto-CMD23 stuff only works in ADMA or PIO. */ + /* + * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO; + * For v4 mode, SDMA may use Auto-CMD23 as well. + */ if ((host->version >= SDHCI_SPEC_300) && ((host->flags & SDHCI_USE_ADMA) || - !(host->flags & SDHCI_USE_SDMA)) && + (!host->v4_mode && !(host->flags & SDHCI_USE_SDMA)) || + (host->v4_mode && (host->flags & SDHCI_USE_SDMA))) && !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { host->flags |= SDHCI_AUTO_CMD23; DBG("Auto-CMD23 available\n"); From patchwork Fri Aug 24 09:20:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145002 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1065652ljw; Fri, 24 Aug 2018 02:21:57 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYAyUntGZ6uaU+qSXuBhORNsrDEI9CDguscbxNoHVLzY91/t+vz/fVtlTuJppawHt85VMQq X-Received: by 2002:a17:902:2804:: with SMTP id e4-v6mr860565plb.327.1535102517490; Fri, 24 Aug 2018 02:21:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535102517; cv=none; d=google.com; s=arc-20160816; b=UOoRarbuKSAWrGaACRLmVdOa/P2jmc0upU01ZcBkMozymcbQujFiqMDpLApwFtnmLR Lium35jU6mjJ7nMmGk1ZVx/E7pwK7ZF05aXIMe+x4bk2PRnMwwvK2kB4R0gXZ9XpqFgo obbu8zwSZtpPfCLOqzAlOdLzEqqZHxO/2qCgxVlYvmX6gqH5coBTJ/3fu4q6AUvpRpuP mMXCpa/TGuBU0H4qnBMGeefj0jNJqhi8My4q2BfQot2wr1ORnma1utWM48oRwkosLuyh WS4tpxNEdPNHJy48+KKmK4MmP3WP/0vxvFSjO+053DQdX2Fr/Jx/iNZfqqfWUf1L+1fq fnTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=dJzPIHC06ogP2ZQrnoPcO6/Nix0g9taouSxpG6mEOxc=; b=ot7g0bKknkPO4EK86BOJBJySVrpVu1OYsvcFjdTBU1iVcV1kq9+tqJoX37B4rDPfvN thpDWYwIdtN5TbogYWZLypvkLr8n3U8b39PCoc3JIKRYWhODcmg7rkmaLuFK1iR1/s6u +a27B9db6TsYyIala1mFvR/bIvHWHRDYtbYewl8vgRjZF0cKmhIQ8zrMeT6RdxeVhSLx 3fKaAnOuoeiGhTQJGsfBx0oY2tPg4NujXHdOet2WddrR7jei7CAUuMNQfh6Ub2wP0/LC aOsFQ7wLJe7wxRwLdMrWMd6WLX+kDIFuhviC6Te4CwlD57PV8mRbqqiDh/JMzA5jt3eA T3KQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YP8d1qw0; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h24-v6si5976237pgh.365.2018.08.24.02.21.57; Fri, 24 Aug 2018 02:21:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YP8d1qw0; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727092AbeHXMzl (ORCPT + 5 others); Fri, 24 Aug 2018 08:55:41 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:44507 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726840AbeHXMzk (ORCPT ); Fri, 24 Aug 2018 08:55:40 -0400 Received: by mail-pl1-f196.google.com with SMTP id ba4-v6so851648plb.11 for ; Fri, 24 Aug 2018 02:21:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dJzPIHC06ogP2ZQrnoPcO6/Nix0g9taouSxpG6mEOxc=; b=YP8d1qw0SpfWJhvY8Ar+DfJMkyzhKCPsd3YQ2IVrmc/cX8cWtTLnfS6NFmlIFaay7g jOFcA/QIrugmyKjZFKp5pG2sMBpY7KXeS59GVEo6LmycnJxoxAm8UC3sN1ErMsnSk0Ec ByaIuZUP4v/HEFmvMmS+85D9UYzrLcfwqS2Ow= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dJzPIHC06ogP2ZQrnoPcO6/Nix0g9taouSxpG6mEOxc=; b=l252yNJXJIm3JpzN7JheFZJ7T9wg07yh+8FRsDARx1b5fBlVM9RJa+sqCusRsm+6TI DXTIJK1VW2NMEjnudlgrWflj0UmP3NpBuhgm/EPz79bOH9GEyPPHPyWx21TbKVv6HL5d 3Bvy66tNd0OBAzNs/YH0v+iRElbihbIb7E93F2j+yVFNMNiqiTCzUDwOnjZbutdvLqHZ p9Zd3o7jpPBiQrLYjRL80dFRf9ofOz2e2M5FuhAw5XPwjhbIq+okKQiAeDjUXnxtitLY s47mm8C3O/7NQibt6N1sf2SXbqYdk/2Ylih1yOVemhJE6EcqX6NPRVGdYZdD7ZRr5jFI Rt/w== X-Gm-Message-State: APzg51CMMctHMOXfhREs3ns6FXjKrtd/Bn7XqtkS0tV7O0dUU5XXqdx8 o4/zMBPVdpnRUCENphzvFMvkgGTzsmA= X-Received: by 2002:a17:902:a5c2:: with SMTP id t2-v6mr882285plq.85.1535102513463; Fri, 24 Aug 2018 02:21:53 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id g6-v6sm9520314pfb.11.2018.08.24.02.21.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Aug 2018 02:21:52 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V6 8/9] mmc: sdhci-sprd: Add Spreadtrum's initial host controller Date: Fri, 24 Aug 2018 17:20:27 +0800 Message-Id: <1535102428-20332-9-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> References: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Chunyan Zhang This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by: Billows Wu Signed-off-by: Chunyan Zhang --- drivers/mmc/host/Kconfig | 13 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-sprd.c | 485 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 499 insertions(+) create mode 100644 drivers/mmc/host/sdhci-sprd.c -- 2.7.4 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 0581c19..c5424dc 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -581,6 +581,19 @@ config MMC_SDRICOH_CS To compile this driver as a module, choose M here: the module will be called sdricoh_cs. +config MMC_SDHCI_SPRD + tristate "Spreadtrum SDIO host Controller" + depends on ARCH_SPRD + depends on MMC_SDHCI_PLTFM + select MMC_SDHCI_IO_ACCESSORS + help + This selects the SDIO Host Controller in Spreadtrum + SoCs, this driver supports R11(IP version: R11P0). + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_TMIO_CORE tristate diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 85dc132..b0b6802 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o +obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o obj-$(CONFIG_MMC_CQHCI) += cqhci.o ifeq ($(CONFIG_CB710_DEBUG),y) diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c new file mode 100644 index 0000000..2551e10 --- /dev/null +++ b/drivers/mmc/host/sdhci-sprd.c @@ -0,0 +1,485 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Secure Digital Host Controller +// +// Copyright (C) 2018 Spreadtrum, Inc. +// Author: Chunyan Zhang + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sdhci-pltfm.h" + +/* SDHCI_ARGUMENT2 register high 16bit */ +#define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) + +#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 +#define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) +#define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) +#define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) +#define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) + +#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 +#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) +#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) + +#define SDHCI_SPRD_REG_DEBOUNCE 0x28C +#define SDHCI_SPRD_BIT_DLL_BAK BIT(0) +#define SDHCI_SPRD_BIT_DLL_VAL BIT(1) + +#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B + +/* SDHCI_HOST_CONTROL2 */ +#define SDHCI_SPRD_CTRL_HS200 0x0005 +#define SDHCI_SPRD_CTRL_HS400 0x0006 + +/* + * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is + * reserved, and only used on Spreadtrum's design, the hardware cannot work + * if this bit is cleared. + * 1 : normal work + * 0 : hardware reset + */ +#define SDHCI_HW_RESET_CARD BIT(3) + +#define SDHCI_SPRD_MAX_CUR 0xFFFFFF +#define SDHCI_SPRD_CLK_MAX_DIV 1023 + +#define SDHCI_SPRD_CLK_DEF_RATE 26000000 + +struct sdhci_sprd_host { + u32 version; + struct clk *clk_sdio; + struct clk *clk_enable; + u32 base_rate; +}; + +#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) + +static void sdhci_sprd_init_config(struct sdhci_host *host) +{ + u16 val; + + /* set dll backup mode */ + val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); + val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; + sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); +} + +static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) +{ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return SDHCI_SPRD_MAX_CUR; + + return readl_relaxed(host->ioaddr + reg); +} + +static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) +{ + /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return; + + if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) + val = val & SDHCI_SPRD_INT_SIGNAL_MASK; + + writel_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) +{ + /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_BLOCK_COUNT)) + return; + + writew_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) +{ + /* + * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the + * standard specification, sdhci_reset() write this register directly + * without checking other reserved bits, that will clear BIT(3) which + * is defined as hardware reset on Spreadtrum's platform and clearing + * it by mistake will lead the card not work. So here we need to work + * around it. + */ + if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { + if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) + val |= SDHCI_HW_RESET_CARD; + } + + writeb_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) +{ + u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + ctrl &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); +} + +static inline void +sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) +{ + u32 dll_dly_offset; + + dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); + if (en) + dll_dly_offset |= mask; + else + dll_dly_offset &= ~mask; + sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); +} + +static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) +{ + u32 div; + + /* select 2x clock source */ + if (base_clk <= clk * 2) + return 0; + + div = (u32) (base_clk / (clk * 2)); + + if ((base_clk / div) > (clk * 2)) + div++; + + if (div > SDHCI_SPRD_CLK_MAX_DIV) + div = SDHCI_SPRD_CLK_MAX_DIV; + + if (div % 2) + div = (div + 1) / 2; + else + div = div / 2; + + return div; +} + +static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, + unsigned int clk) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + u32 div, val, mask; + + div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); + + clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); + sdhci_enable_clk(host, clk); + + /* enable auto gate sdhc_enable_auto_gate */ + val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); + mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | + SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; + if (mask != (val & mask)) { + val |= mask; + sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); + } +} + +static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) +{ + bool en = false; + + if (clock == 0) { + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + } else if (clock != host->clock) { + sdhci_sprd_sd_clk_off(host); + _sdhci_sprd_set_clock(host, clock); + + if (clock <= 400000) + en = true; + sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | + SDHCI_SPRD_BIT_POSRD_DLY_INV, en); + } else { + _sdhci_sprd_set_clock(host, clock); + } +} + +static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); +} + +static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) +{ + return 400000; +} + +static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + u16 ctrl_2; + + if (timing == host->timing) + return; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (timing) { + case MMC_TIMING_UHS_SDR12: + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + break; + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + break; + case MMC_TIMING_UHS_SDR50: + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; + break; + case MMC_TIMING_UHS_SDR104: + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + break; + case MMC_TIMING_MMC_HS200: + ctrl_2 |= SDHCI_SPRD_CTRL_HS200; + break; + case MMC_TIMING_MMC_HS400: + ctrl_2 |= SDHCI_SPRD_CTRL_HS400; + break; + default: + break; + } + + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + +static void sdhci_sprd_hw_reset(struct sdhci_host *host) +{ + int val; + + /* + * Note: don't use sdhci_writeb() API here since it is redirected to + * sdhci_sprd_writeb() in which we have a workaround for + * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can + * not be cleared. + */ + val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); + val &= ~SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + /* wait for 10 us */ + usleep_range(10, 20); + + val |= SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + usleep_range(300, 500); +} + +static struct sdhci_ops sdhci_sprd_ops = { + .read_l = sdhci_sprd_readl, + .write_l = sdhci_sprd_writel, + .write_b = sdhci_sprd_writeb, + .set_clock = sdhci_sprd_set_clock, + .get_max_clock = sdhci_sprd_get_max_clock, + .get_min_clock = sdhci_sprd_get_min_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, + .hw_reset = sdhci_sprd_hw_reset, +}; + +static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct sdhci_host *host = mmc_priv(mmc); + + /* + * From version 4.10 onward, ARGUMENT2 register is also as 32-bit + * block count register which doesn't support stuff bits of + * CMD23 argument on Spreadtrum's sd host controller. + */ + if (host->version >= SDHCI_SPEC_410 && + mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && + (host->flags & SDHCI_AUTO_CMD23)) + host->flags &= ~SDHCI_AUTO_CMD23; + + sdhci_request(mmc, mrq); +} + +static const struct sdhci_pltfm_data sdhci_sprd_pdata = { + .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, + .quirks2 = SDHCI_QUIRK2_BROKEN_HS200, + .ops = &sdhci_sprd_ops, +}; + +static int sdhci_sprd_probe(struct platform_device *pdev) +{ + struct sdhci_host *host; + struct sdhci_sprd_host *sprd_host; + struct clk *clk; + int ret = 0; + + host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); + if (IS_ERR(host)) + return PTR_ERR(host); + + host->dma_mask = DMA_BIT_MASK(64); + pdev->dev.dma_mask = &host->dma_mask; + host->mmc_host_ops.request = sdhci_sprd_request; + + host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_ERASE | MMC_CAP_CMD23; + ret = mmc_of_parse(host->mmc); + if (ret) + goto pltfm_free; + + sprd_host = TO_SPRD_HOST(host); + + clk = devm_clk_get(&pdev->dev, "sdio"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_sdio = clk; + sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); + if (!sprd_host->base_rate) + sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; + + clk = devm_clk_get(&pdev->dev, "enable"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_enable = clk; + + ret = clk_prepare_enable(sprd_host->clk_sdio); + if (ret) + goto pltfm_free; + + clk_prepare_enable(sprd_host->clk_enable); + if (ret) + goto clk_disable; + + sdhci_sprd_init_config(host); + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> + SDHCI_VENDOR_VER_SHIFT); + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + pm_suspend_ignore_children(&pdev->dev, 1); + + sdhci_enable_v4_mode(host); + ret = sdhci_add_host(host); + if (ret) { + dev_err(&pdev->dev, "failed to add mmc host: %d\n", ret); + goto pm_runtime_disable; + } + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + + return 0; + +pm_runtime_disable: + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + + clk_disable_unprepare(sprd_host->clk_enable); + +clk_disable: + clk_disable_unprepare(sprd_host->clk_sdio); + +pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int sdhci_sprd_remove(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + struct mmc_host *mmc = host->mmc; + + mmc_remove_host(mmc); + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + mmc_free_host(mmc); + + return 0; +} + +static const struct of_device_id sdhci_sprd_of_match[] = { + { .compatible = "sprd,sdhci-r11", }, + { } +}; +MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); + +#ifdef CONFIG_PM +static int sdhci_sprd_runtime_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + sdhci_runtime_suspend_host(host); + + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + return 0; +} + +static int sdhci_sprd_runtime_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + int ret; + + ret = clk_prepare_enable(sprd_host->clk_enable); + if (ret) + return ret; + + ret = clk_prepare_enable(sprd_host->clk_sdio); + if (ret) { + clk_disable_unprepare(sprd_host->clk_enable); + return ret; + } + + sdhci_runtime_resume_host(host); + + return 0; +} +#endif + +static const struct dev_pm_ops sdhci_sprd_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, + sdhci_sprd_runtime_resume, NULL) +}; + +static struct platform_driver sdhci_sprd_driver = { + .probe = sdhci_sprd_probe, + .remove = sdhci_sprd_remove, + .driver = { + .name = "sdhci_sprd_r11", + .of_match_table = of_match_ptr(sdhci_sprd_of_match), + .pm = &sdhci_sprd_pm_ops, + }, +}; +module_platform_driver(sdhci_sprd_driver); + +MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:sdhci-sprd-r11"); From patchwork Fri Aug 24 09:20:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145004 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1065696ljw; Fri, 24 Aug 2018 02:22:01 -0700 (PDT) X-Google-Smtp-Source: ANB0Vda8CqjI7CwOoG4kGmFBnoms+rlkSUqqav2NG3Tn5nx/u4gTaYW8vUAjoSGq7gJ3YYeVPN75 X-Received: by 2002:a17:902:1566:: with SMTP id b35-v6mr881348plh.135.1535102520962; Fri, 24 Aug 2018 02:22:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535102520; cv=none; d=google.com; s=arc-20160816; b=Q9uUzo3o4Pi0YtZCm72KkZm2eVTHm+wM6yhNcp6fKT/f4O0v1p2uFhTZf553NaT6nf wNvj6Fr3hqdDW1TtBXj3yCy3MXMY2IEdO8zkk8Ub0obZT5IX3DZFXu7ZjL/B16yfj4C7 TtQpl+e7aI/Hj7h1XuJt4xu3hxm0BG94v44nJ/gKAyCC49KeolrhhvIRO5/lu14dQ/VN DhZbuD96harG3vs+iFb+pbCsKVJs5raIAf/qoqMRNYUJAc0xtWwSXbyo3IupJdePmOut nc0FBzknhd58Me04n5+pQJQAyOSR34hAUPQL2+o/X9jbq3smHcj8O2dDgBwcsq4+dfS+ NMBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=/RXtHte8bNFCXLz2sWlB+/MjHMcewoMGpsLw3S8KcCM=; b=LrICAc+++VAgilnvS23Sef3egJ3q8rkXqzTr3SvVI19w8Pn3FjJ/t9VYeBTofGJiSt H2qmWBZJOBfm8oZbzSMZptNp7gYKu2y2YKwAe2+6IRjL4JOkdfsLH+hLkoDGD0ghLLQD 4JGhJ97pyLC2XR0amt6PsqdNeTh20cjY6CY6/+FJy96ptO1fB0BY6MWfF6XAs+0qyOyH vW63b5+W/T3XQ6Iu3aJ3c+4E85kK02WwjqyHAqBcmI2CpMMVkc8CL9eAKgkZF2RFSaCF 82ISQ61303XWMAsTtt3B+mrmNwk+1K0IA8+p/JsGRm9B5T0vVzFRIcq41UGV6a01nlv3 FX4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RQ/9niS2"; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s2-v6si4407822plp.144.2018.08.24.02.22.00; Fri, 24 Aug 2018 02:22:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RQ/9niS2"; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726746AbeHXMzo (ORCPT + 5 others); Fri, 24 Aug 2018 08:55:44 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:33011 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727941AbeHXMzo (ORCPT ); Fri, 24 Aug 2018 08:55:44 -0400 Received: by mail-pl1-f193.google.com with SMTP id 60-v6so851168ple.0 for ; Fri, 24 Aug 2018 02:21:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/RXtHte8bNFCXLz2sWlB+/MjHMcewoMGpsLw3S8KcCM=; b=RQ/9niS2ZQDepy69GPR4TwrmfOO7UsOK2r2+SLhbspcKcRYUR5uLpEtybkOmM965Jq o2j18KVbNEKoeSXb0iYqm0uY+CI+ZWRvt8pa4ARh8rmundcEHO3lzIc5bIXK+7t8HXFw xUfnvM1MrewnCHXWevfo3yq+2FY5pS3dQzyVI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/RXtHte8bNFCXLz2sWlB+/MjHMcewoMGpsLw3S8KcCM=; b=O8jTB7gl/+YxCiNLKLA9zOjzduS4zdaFkFnBVRadaX/+b59ni/huQZXiKmRUKMSBSJ hvUjI3FvWG3EpehUqDyAJqm3jLcENeHlUmPHcnHjg1ovMIjTGUVNJUm5ML8GZqRh1mQP Z4GN1eMmdpdkeuhPxJ5mLwb7oQlZrirgGpKrEEPeYEr9CteKvUxfHIht7bkMysobV5az bM0tCEUaWLkG1ofhme2tHnS2iNeF2IHKCAaJK+MGN2phXllFTrXYv6hKcc48HCTkd3x5 lOQcYYJNc/wRLzaPNTRqHwWobkdUv579fgeqGKWt9W1s9ljXr9x4Tb+I0i+C54pmRWDj ehkA== X-Gm-Message-State: APzg51DS0t7/XKpr8Qa0eNotiYcWeKEmCEuzj1rZwOxGtRACtJClUUat k7dyiNi90cg4La7A4916NVtX4g== X-Received: by 2002:a17:902:8a92:: with SMTP id p18-v6mr891941plo.148.1535102517890; Fri, 24 Aug 2018 02:21:57 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id g6-v6sm9520314pfb.11.2018.08.24.02.21.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Aug 2018 02:21:57 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V6 9/9] dt-bindings: sdhci-sprd: Add bindings for the sdhci-sprd controller Date: Fri, 24 Aug 2018 17:20:28 +0800 Message-Id: <1535102428-20332-10-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> References: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Chunyan Zhang This patch adds the device-tree binding documentation for Spreadtrum SDHCI driver. Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/mmc/sdhci-sprd.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sprd.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt new file mode 100644 index 0000000..45c9978 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt @@ -0,0 +1,41 @@ +* Spreadtrum SDHCI controller (sdhci-sprd) + +The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface +for MMC, SD and SDIO types of cards. + +This file documents differences between the core properties in mmc.txt +and the properties used by the sdhci-sprd driver. + +Required properties: +- compatible: Should contain "sprd,sdhci-r11". +- reg: physical base address of the controller and length. +- interrupts: Interrupts used by the SDHCI controller. +- clocks: Should contain phandle for the clock feeding the SDHCI controller +- clock-names: Should contain the following: + "sdio" - SDIO source clock (required) + "enable" - gate clock which used for enabling/disabling the device (required) + +Optional properties: +- assigned-clocks: the same with "sdio" clock +- assigned-clock-parents: the default parent of "sdio" clock + +Examples: + +sdio0: sdio@20600000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20600000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>; + assigned-clocks = <&ap_clk CLK_EMMC_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + status = "okay"; +};