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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 100sm1263446otv.32.2021.07.09.10.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 10:43:09 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Sibi S Cc: Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: soc: qcom: aoss: Add SC8180X and generic compatible Date: Fri, 9 Jul 2021 10:41:40 -0700 Message-Id: <20210709174142.1274554-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210709174142.1274554-1-bjorn.andersson@linaro.org> References: <20210709174142.1274554-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a generic compatible for all versions of the AOSS QMP to the binding, in order to allow a single implementation for them and then add a specific compatible for the Qualcomm SC8180x platform. Signed-off-by: Bjorn Andersson --- Changes since v1: - Mention the generic compatible in $subject and message. Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.29.2 Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt index 783dc81b0f26..3747032311a4 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt @@ -18,10 +18,13 @@ power-domains. Definition: must be one of: "qcom,sc7180-aoss-qmp" "qcom,sc7280-aoss-qmp" + "qcom,sc8180x-aoss-qmp" "qcom,sdm845-aoss-qmp" "qcom,sm8150-aoss-qmp" "qcom,sm8250-aoss-qmp" "qcom,sm8350-aoss-qmp" + and: + "qcom,aoss-qmp" - reg: Usage: required @@ -70,7 +73,7 @@ The following example represents the AOSS side-channel message RAM and the mechanism exposing the power-domains, as found in SDM845. aoss_qmp: qmp@c300000 { - compatible = "qcom,sdm845-aoss-qmp"; + compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0c300000 0x100000>; interrupts = ; mboxes = <&apss_shared 0>; From patchwork Fri Jul 9 17:41:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 471889 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp525332jao; Fri, 9 Jul 2021 10:43:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxG+N1ug8XXzcUA2apxqsHOIWdXfzHdSTsGrOvccZKuam6ikLbgwQ8Ytl5DJ7JoyJUByQY3 X-Received: by 2002:a17:906:17d0:: with SMTP id u16mr3679174eje.129.1625852594822; Fri, 09 Jul 2021 10:43:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625852594; cv=none; d=google.com; s=arc-20160816; b=gFXvWi3j00a8TYfqyLJEiSKI+UMJaUvI0XauUgaIVAl1m5Zpy1u0waQ1WhBOpLqulI Jai29B/91TVbH8imaxB+hHzG5h2MH+LkQHmjvrWQxVaSqZ1+amQm0kI5dNdJSpqP5UMn msdlFU8LO6fhiOe8QntYZHdwufpTfT4VKhQ3PGDqlLAt3aC27NHqtXQGCdCM535iOiGK mQ0e0D7KRPKH9xaQaM2SaAB5jPRDZW+6WVJTUc1Uafsus8zcnwWpSeZKEqyJxVR7SiVZ K0j2XI8gXU8souuIfZMXrD7hNTSiZj7LBCiTzS63M3rdDm3W4IQ22KkMMkVCFcrSD7gK +sqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=t+noCRKNuxgj94k9yRux6lWJbMi/RvWXTgfE54TN/88=; b=Gs5pjB6SV/ktigV3v7eH9VVsE6iZz4qw8OBX/GOSlom11FXKVml6rMgTde25GiQpTk Iq7FsSqL1SYJO8j0iNSv8gkBqnostu5oh+dD+75fFbfdaVfi+46kYIDNzuHKzOSWP9Ht YMsSF+SbSWRQCUGSEDQZe9LVfWuPna+8f423uj607NnjgKcFSI9HN4qWWczLgx1DeZhm X63mC+Eggmzsd7zyHtlA/fRLVY0NthDYZZDZ7poIs+aN6cEiKX3jixdD3tnpoP0sg8Tf 7gnHSWCS79lIjeTmztGxW/KgOxJ5A68ZThGMtfns3pDap6hP5h1cPEHgZOfVu5JBCnPw OMHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="p/Vp0yMe"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 100sm1263446otv.32.2021.07.09.10.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 10:43:10 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Sibi S Cc: Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 2/3] dt-bindings: soc: qcom: aoss: Convert to YAML Date: Fri, 9 Jul 2021 10:41:41 -0700 Message-Id: <20210709174142.1274554-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210709174142.1274554-1-bjorn.andersson@linaro.org> References: <20210709174142.1274554-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert to YAML in order to allow validation. Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson --- Changes since v1: - Dropped qoutes around compatible strings - Fixed indentation of the compatible enum members - Picked up Rob's R-b .../bindings/soc/qcom/qcom,aoss-qmp.txt | 90 -------------- .../bindings/soc/qcom/qcom,aoss-qmp.yaml | 114 ++++++++++++++++++ 2 files changed, 114 insertions(+), 90 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml -- 2.29.2 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt deleted file mode 100644 index 3747032311a4..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt +++ /dev/null @@ -1,90 +0,0 @@ -Qualcomm Always-On Subsystem side channel binding - -This binding describes the hardware component responsible for side channel -requests to the always-on subsystem (AOSS), used for certain power management -requests that is not handled by the standard RPMh interface. Each client in the -SoC has it's own block of message RAM and IRQ for communication with the AOSS. -The protocol used to communicate in the message RAM is known as Qualcomm -Messaging Protocol (QMP) - -The AOSS side channel exposes control over a set of resources, used to control -a set of debug related clocks and to affect the low power state of resources -related to the secondary subsystems. These resources are exposed as a set of -power-domains. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,sc7180-aoss-qmp" - "qcom,sc7280-aoss-qmp" - "qcom,sc8180x-aoss-qmp" - "qcom,sdm845-aoss-qmp" - "qcom,sm8150-aoss-qmp" - "qcom,sm8250-aoss-qmp" - "qcom,sm8350-aoss-qmp" - and: - "qcom,aoss-qmp" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the message RAM for this - client's communication with the AOSS - -- interrupts: - Usage: required - Value type: - Definition: should specify the AOSS message IRQ for this client - -- mboxes: - Usage: required - Value type: - Definition: reference to the mailbox representing the outgoing doorbell - in APCS for this client, as described in mailbox/mailbox.txt - -- #clock-cells: - Usage: optional - Value type: - Definition: must be 0 - The single clock represents the QDSS clock. - -- #power-domain-cells: - Usage: optional - Value type: - Definition: must be 1 - The provided power-domains are: - CDSP state (0), LPASS state (1), modem state (2), SLPI - state (3), SPSS state (4) and Venus state (5). - -= SUBNODES -The AOSS side channel also provides the controls for three cooling devices, -these are expressed as subnodes of the QMP node. The name of the node is used -to identify the resource and must therefor be "cx", "mx" or "ebi". - -- #cooling-cells: - Usage: optional - Value type: - Definition: must be 2 - -= EXAMPLE - -The following example represents the AOSS side-channel message RAM and the -mechanism exposing the power-domains, as found in SDM845. - - aoss_qmp: qmp@c300000 { - compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; - reg = <0x0c300000 0x100000>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #power-domain-cells = <1>; - - cx_cdev: cx { - #cooling-cells = <2>; - }; - - mx_cdev: mx { - #cooling-cells = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml new file mode 100644 index 000000000000..93e4b737ee1b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Always-On Subsystem side channel binding + +maintainers: + - Bjorn Andersson + +description: + This binding describes the hardware component responsible for side channel + requests to the always-on subsystem (AOSS), used for certain power management + requests that is not handled by the standard RPMh interface. Each client in the + SoC has it's own block of message RAM and IRQ for communication with the AOSS. + The protocol used to communicate in the message RAM is known as Qualcomm + Messaging Protocol (QMP) + + The AOSS side channel exposes control over a set of resources, used to control + a set of debug related clocks and to affect the low power state of resources + related to the secondary subsystems. These resources are exposed as a set of + power-domains. + +properties: + compatible: + items: + - enum: + - qcom,sc7180-aoss-qmp + - qcom,sc7280-aoss-qmp + - qcom,sc8180x-aoss-qmp + - qcom,sdm845-aoss-qmp + - qcom,sm8150-aoss-qmp + - qcom,sm8250-aoss-qmp + - qcom,sm8350-aoss-qmp + - const: qcom,aoss-qmp + + reg: + maxItems: 1 + description: + The base address and size of the message RAM for this client's + communication with the AOSS + + interrupts: + maxItems: 1 + description: + Should specify the AOSS message IRQ for this client + + mboxes: + maxItems: 1 + description: + Reference to the mailbox representing the outgoing doorbell in APCS for + this client, as described in mailbox/mailbox.txt + + "#clock-cells": + const: 0 + description: + The single clock represents the QDSS clock. + + "#power-domain-cells": + const: 1 + description: | + The provided power-domains are: + CDSP state (0), LPASS state (1), modem state (2), SLPI + state (3), SPSS state (4) and Venus state (5). + +required: + - compatible + - reg + - interrupts + - mboxes + - "#clock-cells" + +additionalProperties: false + +patternProperties: + "^(cx|mx|ebi)$": + type: object + description: + The AOSS side channel also provides the controls for three cooling devices, + these are expressed as subnodes of the QMP node. The name of the node is + used to identify the resource and must therefor be "cx", "mx" or "ebi". + + properties: + "#cooling-cells": + const: 2 + + required: + - "#cooling-cells" + + additionalProperties: false + +examples: + - | + #include + + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0c300000 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + + cx_cdev: cx { + #cooling-cells = <2>; + }; + + mx_cdev: mx { + #cooling-cells = <2>; + }; + }; +... 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 100sm1263446otv.32.2021.07.09.10.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 10:43:11 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Sibi S Cc: Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] soc: qcom: aoss: Add generic compatible Date: Fri, 9 Jul 2021 10:41:42 -0700 Message-Id: <20210709174142.1274554-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210709174142.1274554-1-bjorn.andersson@linaro.org> References: <20210709174142.1274554-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It seems we don't need platform specific implementation for the AOSS QMP, so let's introduce a generic compatible to avoid having to update the driver for each platform. Signed-off-by: Bjorn Andersson Reviewed-by: Sibi Sankar Tested-by: Sibi Sankar --- Changes since v1: - None drivers/soc/qcom/qcom_aoss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 934fcc4d2b05..92a1af70a649 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -602,6 +602,7 @@ static const struct of_device_id qmp_dt_match[] = { { .compatible = "qcom,sm8150-aoss-qmp", }, { .compatible = "qcom,sm8250-aoss-qmp", }, { .compatible = "qcom,sm8350-aoss-qmp", }, + { .compatible = "qcom,aoss-qmp", }, {} }; MODULE_DEVICE_TABLE(of, qmp_dt_match);