From patchwork Wed Aug 29 07:02:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145384 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp339846ljw; Wed, 29 Aug 2018 00:03:20 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZ4uXpm3XNeFMG5zaXj5h9w5tMNeSjkfcCYFCdwFADYo8W67O6QxzMlbaameDPKeFMM6z6T X-Received: by 2002:a17:902:1566:: with SMTP id b35-v6mr4703102plh.135.1535526200772; Wed, 29 Aug 2018 00:03:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535526200; cv=none; d=google.com; s=arc-20160816; b=mlfx/YqB+S/CpRc6UTyWb8Z3RgpBkl0eI6Z8lXd65pxKAO9/ZSSvgA8TVUr57o19Oq 5VzWOeBttf18ThN9xI5dw6wU0zj4nzRv9rtsaEUvbrcSXJLREeQgj/MSuuQk/FL7gxBU 4fZj9sB5zOI7TPXzk36VyquMCyoeKaCLjSHps9gzNjqYxGUPijhSvznn01WctEs3Y3F6 tSNMdhLqyK6MaAO+w2lPF5XzEeATYKK+v//qvCxbfHbCT33WxHWUQqOXiC+G4fccHfSj zD31ObkyL0fiHgkFlAqfZDheZkLDjTvcO/bK6GSzkiFBiDarrCG98wGdF3uqNTis468b G/Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=++1fRQNMnXH0A0SYZtvAp1/7snJJJbIXHOql7gVNj04=; b=K3+Dy065aS16soEb/5ZHc3N4xNDwBNbEsz7UWcEtC1ALELYGggAhMIu8Fo6/+QzX6B ib3oWulLI/vy5SSijKeq6KARo61bQGSKjQedenX39XkOLqj93g7TxPPO+NPubgVToRNr nP5ustVHAHGvDjpjf8E+DsrVqBe4QWt69mTGcKX8AocrmLd01DwBAHBKpCLVNTR5mqMR qAi1OLizBabbKXV2iBjR9WbJ85TXK6NLQcKWFJ4oLUCypoBRE1jIhyGUdi1krWxL1Y7l oKgcV2vBJLvEBASq0pa441vvzh1c4QGtPzeDs4WR3TP9cqjlII7V9Pjxmy/1hGfTGV0m T9xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BOj+JRQH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t89-v6si3030701pfe.59.2018.08.29.00.03.20; Wed, 29 Aug 2018 00:03:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BOj+JRQH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727652AbeH2K6n (ORCPT + 32 others); Wed, 29 Aug 2018 06:58:43 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:42606 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727625AbeH2K6m (ORCPT ); Wed, 29 Aug 2018 06:58:42 -0400 Received: by mail-pl1-f196.google.com with SMTP id g23-v6so1880038plq.9 for ; Wed, 29 Aug 2018 00:03:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=++1fRQNMnXH0A0SYZtvAp1/7snJJJbIXHOql7gVNj04=; b=BOj+JRQH3cjH6wss3IOQ35mX1jeAxamz9/uZJmdsbxWmm8KX/Rp3UoDa1j1JhJRtmq 3NEjRJjtNz6LmV4aE689SdAkmmOZ6AUknrsB0demBYZRj3AF5mzdXvaRRaYk9dVkjhdH ExNN38rlF0LpYG3eCiIpXP/GnYUrpuIag7HeA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=++1fRQNMnXH0A0SYZtvAp1/7snJJJbIXHOql7gVNj04=; b=SMo8Y8fHR4S785VK5819o8J8RaGMqNy9gdj0FM0FW+ojr+4B4BkltkFl4XucJKTKbx Qx/RT4Ehx6eeFbHraaA5P/njH/9D8PQc6ehkPScr5EOYMSlRKmqBtLw0nC+xQN3TBI2J Jam4Yfckb0AtkJDC09daq2H2wdiIdFM55D0A/ub0PAwQWTPKG5j1z926Yse4ehccUYAd 8oT5B+K/9PCbhFrDT9NHmeOyTvBlHTzSC1SkvgAZgBG2FaTSC+WrFthCWc/jg8zlQISv WiO80JH4lAlErh2MvkXARbUynvCdMLmpVLoUwX9PdSyoj0j5Ox1SxfwEaoEjzScxmffw p0XQ== X-Gm-Message-State: APzg51B4W8cuRd1UkC0C2VihQbXxTT65//VAiMQhjdDVswMBNfmvs3oe lhqBcSQvpKvCEC+CwwPAYqHI0Q== X-Received: by 2002:a17:902:1ab:: with SMTP id b40-v6mr4825100plb.55.1535526197764; Wed, 29 Aug 2018 00:03:17 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:16 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 1/9] mmc: sdhci: Add version V4 definition Date: Wed, 29 Aug 2018 15:02:56 +0800 Message-Id: <1535526184-32718-2-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Added definitions for v400, v410, v420. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 2 +- drivers/mmc/host/sdhci.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) -- 2.7.4 Acked-by: Adrian Hunter diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 97e4efa..01bf88c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3508,7 +3508,7 @@ int sdhci_setup_host(struct sdhci_host *host) override_timeout_clk = host->timeout_clk; - if (host->version > SDHCI_SPEC_300) { + if (host->version > SDHCI_SPEC_420) { pr_err("%s: Unknown controller version (%d). You may experience problems.\n", mmc_hostname(mmc), host->version); } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 732d82f..dbd48a8 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -270,6 +270,9 @@ #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_SPEC_400 3 +#define SDHCI_SPEC_410 4 +#define SDHCI_SPEC_420 5 /* * End of controller registers. From patchwork Wed Aug 29 07:02:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145386 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp339980ljw; Wed, 29 Aug 2018 00:03:29 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbQYXXHMRkPoSC6jBB/dUT61Jr+Z6GLzaf6u66uUMHxveP1pRpbF1EnPOCsG/nwe7ei1VQy X-Received: by 2002:a63:ba1c:: with SMTP id k28-v6mr4543594pgf.76.1535526209508; Wed, 29 Aug 2018 00:03:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535526209; cv=none; d=google.com; s=arc-20160816; b=SiuLajE4H3xkdlKo4OIryIWyp21Wh35aWjXU1SrMrcKZGhT6takfNNWHfDKV5BS3Y7 NAYiQBlY0106xFmVfuQCXA35hLIEMPdDnbHN7r7jGYjYOxQMJQUB38rE7uz6snu93hCv w+2dC5eviwQk/xG6DhidxVvp1tbW3gXgVUX6P16fbaWRvqv6t0QaXg5+k/1NTIdtEBuy RUIwhLdexFejZXjfvY+R82KGAF0AGM8IwKPZuJjlCV7NeP2/u8SVrfNk7/4ATJgYwC1n XM7WSHtg14SoHWJ3fydJsrWagtmbpLIahacfELaTXN06P2reByTCIxqnCB6Wv2DP0Ymb BEGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=BASbtQme+9NYFc4kTckiwE+4eWZRxL4aqBbLe9Llj1Q=; b=kC+oOBcO3ZpzagWhVr+aXZl8PKlT315JUbSP9dI77298zz1bWed0uUEJFRbYKCE2PE cEJiCfSQel29JqmB4dZlNJciUJ+dtcSKcrABayprIeqOwa9XE1G8oHj77WcTAKge1zVF JljvPOI55rXWKjRnH3MhMfvfzaUFT7hEdxhM4TMDHQ2v2r/qGeWxnSTeUECSktM/DcVh EXiK4XLk9LLBZ18P0porZ6jWUD6PuThjJuVTT1Lon1AwitYcLlNHmne+qWxTHipB2086 XJxyHSFoD49RpU/N0r9D263bDdaQJ2zFZ2dC92AkdeqXJmod+zvRRDQjiVTyVRDo7Z3b lxpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bnWksmN6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c3-v6si2937528pld.457.2018.08.29.00.03.29; Wed, 29 Aug 2018 00:03:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bnWksmN6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727701AbeH2K6w (ORCPT + 32 others); Wed, 29 Aug 2018 06:58:52 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:37629 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726858AbeH2K6v (ORCPT ); Wed, 29 Aug 2018 06:58:51 -0400 Received: by mail-pg1-f196.google.com with SMTP id 2-v6so1392731pgo.4 for ; Wed, 29 Aug 2018 00:03:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BASbtQme+9NYFc4kTckiwE+4eWZRxL4aqBbLe9Llj1Q=; b=bnWksmN6GQj35dKzO4xh6PQHDeTHjXqRX/50rR0UJsPqMDLeO6PJ8Y3I8b484TM3i9 /oobJYzs2wrpgQl+XdL82G6I4HKhf2nhTwYEWtMza29xB7v54kMbwGUmLwG6+mCQ6X3d +JrJD3xSTr9McuDvh6oHF8wdznp0iTc7o0zuc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BASbtQme+9NYFc4kTckiwE+4eWZRxL4aqBbLe9Llj1Q=; b=jR7X5rwg+St9IYIEgLGEessXhq7pWxUr8GQ6eQOgazF/BX5vi8LWlig4f7DggzNv1u /Alu6amAlutVzz6koMCaQGFeYeGVRljkOgD9dPWPzHPPfo5usVlFYd/TFIR1zIgxddE0 sxpKwiBvwJGQk/D68rnckHR0ncr6BEGfs3xQPTdAOpKSiBNksdVBHNvkGdCDS5UsNLrR rpR3+voiG5ONUvXtnQjRJygqDZv1PyQRFR46R5/C1unzUGCB+9jKtm1wU+fP52C+EnD9 DLXH92pm4SEBlkKIy0syOonEi9e0y89AjFcxdXy9AqUoJuUwnRh135SC3wqMabAmvYNf Qxhw== X-Gm-Message-State: APzg51BxQAhTNnSrfdw81Kxaimz8DyXg86dz/IHIRwibK/SsSkUi5Gkt fHndfPjjeGZjEgnIFXKLvhDZPbxCFwQ= X-Received: by 2002:a63:444d:: with SMTP id t13-v6mr4541487pgk.102.1535526206262; Wed, 29 Aug 2018 00:03:26 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:25 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 3/9] mmc: sdhci: Change SDMA address register for v4 mode Date: Wed, 29 Aug 2018 15:02:58 +0800 Message-Id: <1535526184-32718-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to the SD host controller specification version 4.10, when Host Version 4 is enabled, SDMA uses ADMA System Address register (05Fh-058h) instead of using SDMA System Address register to support both 32-bit and 64-bit addressing. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) -- 2.7.4 Acked-by: Adrian Hunter diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 0c61105..6fb70da 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -727,7 +727,7 @@ static void sdhci_adma_table_post(struct sdhci_host *host, } } -static u32 sdhci_sdma_address(struct sdhci_host *host) +static dma_addr_t sdhci_sdma_address(struct sdhci_host *host) { if (host->bounce_buffer) return host->bounce_addr; @@ -735,6 +735,17 @@ static u32 sdhci_sdma_address(struct sdhci_host *host) return sg_dma_address(host->data->sg); } +static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr) +{ + if (host->v4_mode) { + sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS); + if (host->flags & SDHCI_USE_64_BIT_DMA) + sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI); + } else { + sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); + } +} + static unsigned int sdhci_target_timeout(struct sdhci_host *host, struct mmc_command *cmd, struct mmc_data *data) @@ -994,8 +1005,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) SDHCI_ADMA_ADDRESS_HI); } else { WARN_ON(sg_cnt != 1); - sdhci_writel(host, sdhci_sdma_address(host), - SDHCI_DMA_ADDRESS); + sdhci_set_sdma_addr(host, sdhci_sdma_address(host)); } } @@ -2830,7 +2840,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) * some controllers are faulty, don't trust them. */ if (intmask & SDHCI_INT_DMA_END) { - u32 dmastart, dmanow; + dma_addr_t dmastart, dmanow; dmastart = sdhci_sdma_address(host); dmanow = dmastart + host->data->bytes_xfered; @@ -2838,12 +2848,12 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) * Force update to the next DMA block boundary. */ dmanow = (dmanow & - ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + + ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + SDHCI_DEFAULT_BOUNDARY_SIZE; host->data->bytes_xfered = dmanow - dmastart; - DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n", - dmastart, host->data->bytes_xfered, dmanow); - sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); + DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n", + &dmastart, host->data->bytes_xfered, &dmanow); + sdhci_set_sdma_addr(host, dmanow); } if (intmask & SDHCI_INT_DATA_END) { @@ -3590,8 +3600,8 @@ int sdhci_setup_host(struct sdhci_host *host) } } - /* SDMA does not support 64-bit DMA */ - if (host->flags & SDHCI_USE_64_BIT_DMA) + /* SDMA does not support 64-bit DMA if v4 mode not set */ + if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode) host->flags &= ~SDHCI_USE_SDMA; if (host->flags & SDHCI_USE_ADMA) { From patchwork Wed Aug 29 07:02:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145387 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp340033ljw; Wed, 29 Aug 2018 00:03:34 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZG6Hu9zwlkizzP26ExIZLy22cFplxAVOVYWSf8EkO/yYei1Nwbf7kes6OypnW+w4HkjhiD X-Received: by 2002:a17:902:a502:: with SMTP id s2-v6mr4781766plq.311.1535526214139; Wed, 29 Aug 2018 00:03:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535526214; cv=none; d=google.com; s=arc-20160816; b=lALg9ACVZ7SWjKKbeRPNpGkRBZFNSiBS4ACOJuSRek0LFx9ni0Ufxl+VpkkN82zdMu g5SkoeoLAzt6ff8JaUcPk2D4OuRwCpWouP8BLwf1doIyVx1JQL0cR/GtFk+AZpiXx520 lEE/rQMleGMUrmEMJO+S4tOKVxkFJoXkAFw5MeANFDdNTO+WRkckXytX5GgGb0FotClB 6zvFDyUi6+7LimMZVg+jW/ab56uWcXOiNNAG+rbcrMrBen8RbgFAtfrifo8ivUrnR8v6 uMO4KQ8Uim8j2tbVPzQdaOg/f2ns4/Zw2jiexJhYxeQDaPHjLT11aI3KiTJlFPijzp39 ekLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=c/eV9ZN7dNN0gTb1HotdKJUB+PKAX41PZSlC9GVsCR4=; b=w/ohzVS/U/BBBM33/ehYRgI8FYGPCmLpdTkI/Y/tYDreaViSzwYqHMmYZCOuDH1w4b zOanBXks3xO0UCuVA1xXnYVYIti4pHNpGcZW8Syyd5ZUDK1bLtMMleTTsZ78xhQfFasQ FwSIOD+QFzXh/qXKg5YQ7vBh0Zi75RjMk2RSZdiPrCVFI34CyG8l2lvH1ZuuJvCAJgWW u3JIpNFeKWPg6gpAKIRnb1vStt3ZMa+NRjSYjsDMBpfYPofahoHoU4e1Oufcu6WkPZrK YIwKp+nCeo5Y8YZsEZD+ByP5RpX0oU9Fxuvq1JBeGeU7gOhJZfnM8diKoZZGQWHGZVbP +0qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iGDms1bG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t64-v6si2959480pgd.176.2018.08.29.00.03.33; Wed, 29 Aug 2018 00:03:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iGDms1bG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727722AbeH2K64 (ORCPT + 32 others); Wed, 29 Aug 2018 06:58:56 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:36420 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726858AbeH2K64 (ORCPT ); Wed, 29 Aug 2018 06:58:56 -0400 Received: by mail-pl1-f196.google.com with SMTP id e11-v6so1897217plb.3 for ; Wed, 29 Aug 2018 00:03:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=c/eV9ZN7dNN0gTb1HotdKJUB+PKAX41PZSlC9GVsCR4=; b=iGDms1bGEXHVyC9Lz1Sq6+1gpZzMe7gRddF7OC5SiZxFn0I6odf01I53tcgHGUoYAr FGCEIHaBbBx9WvaAmiDSZAh2yA0gcHdq1kxOcPhvLEIcWgbJpXVxj0CbJ+SQpvnhUZMR h14i/JmOVODpA7RWBlp8Br/W1vdl635OZ/Cag= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c/eV9ZN7dNN0gTb1HotdKJUB+PKAX41PZSlC9GVsCR4=; b=cj4kB5CAEB5FTcVZI39HyJOXyJd0VH+FBR78jPmUz4OIKcT5UKi6VxL+6nuNjkcdkZ K7+hIPsitcpwGmMuFCGVouM2aj+0yMQMR0aRjLBhrFkIrakCKqWXrU+FycVpmWTH1MTt 8nZXTt8j5pSIiZT1VdmtRqbivVipTVOttgWOvyZdgcUvZq1LJSDzsgohiAsYi+uo0Igz NETFJs2wKQurjIrX5nQNDLj6dt3sXOm1l9kh61g6lCaDiCDQn9Obb369QBSIFyZ3m27r U02T/B2ppuKnfLdByGJJRahPDgAREyX+OX2RuFdo9wXszjtoKZRLVc3l8BOC+xHyIJAp xYZg== X-Gm-Message-State: APzg51BrAyb+aLsIIly50Prpc+GiAu+fbxlwy1Zq6OLB+1UoC7RPm6SC ojn/wml8XzO898k8nx1Pa76Z+g== X-Received: by 2002:a17:902:4401:: with SMTP id k1-v6mr4562523pld.97.1535526210900; Wed, 29 Aug 2018 00:03:30 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:30 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 4/9] mmc: sdhci: Add ADMA2 64-bit addressing support for V4 mode Date: Wed, 29 Aug 2018 15:02:59 +0800 Message-Id: <1535526184-32718-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 92 +++++++++++++++++++++++++++++++++++------------- drivers/mmc/host/sdhci.h | 12 +++++-- 2 files changed, 78 insertions(+), 26 deletions(-) -- 2.7.4 Acked-by: Adrian Hunter diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 6fb70da..17345b6 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -266,6 +266,52 @@ static void sdhci_set_default_irqs(struct sdhci_host *host) sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); } +static void sdhci_config_dma(struct sdhci_host *host) +{ + u8 ctrl; + u16 ctrl2; + + if (host->version < SDHCI_SPEC_200) + return; + + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + + /* + * Always adjust the DMA selection as some controllers + * (e.g. JMicron) can't do PIO properly when the selection + * is ADMA. + */ + ctrl &= ~SDHCI_CTRL_DMA_MASK; + if (!(host->flags & SDHCI_REQ_USE_DMA)) + goto out; + + /* Note if DMA Select is zero then SDMA is selected */ + if (host->flags & SDHCI_USE_ADMA) + ctrl |= SDHCI_CTRL_ADMA32; + + if (host->flags & SDHCI_USE_64_BIT_DMA) { + /* + * If v4 mode, all supported DMA can be 64-bit addressing if + * controller supports 64-bit system address, otherwise only + * ADMA can support 64-bit addressing. + */ + if (host->v4_mode) { + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 |= SDHCI_CTRL_64BIT_ADDR; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + } else if (host->flags & SDHCI_USE_ADMA) { + /* + * Don't need to undo SDHCI_CTRL_ADMA32 in order to + * set SDHCI_CTRL_ADMA64. + */ + ctrl |= SDHCI_CTRL_ADMA64; + } + } + +out: + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + static void sdhci_init(struct sdhci_host *host, int soft) { struct mmc_host *mmc = host->mmc; @@ -913,7 +959,6 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { - u8 ctrl; struct mmc_data *data = cmd->data; host->data_timeout = 0; @@ -1009,25 +1054,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) } } - /* - * Always adjust the DMA selection as some controllers - * (e.g. JMicron) can't do PIO properly when the selection - * is ADMA. - */ - if (host->version >= SDHCI_SPEC_200) { - ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); - ctrl &= ~SDHCI_CTRL_DMA_MASK; - if ((host->flags & SDHCI_REQ_USE_DMA) && - (host->flags & SDHCI_USE_ADMA)) { - if (host->flags & SDHCI_USE_64_BIT_DMA) - ctrl |= SDHCI_CTRL_ADMA64; - else - ctrl |= SDHCI_CTRL_ADMA32; - } else { - ctrl |= SDHCI_CTRL_SDMA; - } - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); - } + sdhci_config_dma(host); if (!(host->flags & SDHCI_REQ_USE_DMA)) { int flags; @@ -3511,6 +3538,19 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) return 0; } +static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) +{ + /* + * According to SD Host Controller spec v4.10, bit[27] added from + * version 4.10 in Capabilities Register is used as 64-bit System + * Address support for V4 mode. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) + return host->caps & SDHCI_CAN_64BIT_V4; + + return host->caps & SDHCI_CAN_64BIT; +} + int sdhci_setup_host(struct sdhci_host *host) { struct mmc_host *mmc; @@ -3582,7 +3622,7 @@ int sdhci_setup_host(struct sdhci_host *host) * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to * implement. */ - if (host->caps & SDHCI_CAN_64BIT) + if (sdhci_can_64bit_dma(host)) host->flags |= SDHCI_USE_64_BIT_DMA; if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { @@ -3616,8 +3656,8 @@ int sdhci_setup_host(struct sdhci_host *host) */ if (host->flags & SDHCI_USE_64_BIT_DMA) { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * - SDHCI_ADMA2_64_DESC_SZ; - host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + SDHCI_ADMA2_64_DESC_SZ(host); + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); } else { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * SDHCI_ADMA2_32_DESC_SZ; @@ -3625,7 +3665,11 @@ int sdhci_setup_host(struct sdhci_host *host) } host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; - buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + + /* + * Use zalloc to zero the reserved high 32-bits of 128-bit + * descriptors so that they never need to be written. + */ + buf = dma_zalloc_coherent(mmc_dev(mmc), host->align_buffer_sz + host->adma_table_sz, &dma, GFP_KERNEL); if (!buf) { pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 61611e3..c5cc513 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -185,6 +185,7 @@ #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 #define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -205,6 +206,7 @@ #define SDHCI_CAN_VDD_330 0x01000000 #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 #define SDHCI_SUPPORT_SDR50 0x00000001 @@ -309,8 +311,14 @@ struct sdhci_adma2_32_desc { */ #define SDHCI_ADMA2_DESC_ALIGN 8 -/* ADMA2 64-bit DMA descriptor size */ -#define SDHCI_ADMA2_64_DESC_SZ 12 +/* + * ADMA2 64-bit DMA descriptor size + * According to SD Host Controller spec v4.10, there are two kinds of + * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit + * Descriptor, if Host Version 4 Enable is set in the Host Control 2 + * register, 128-bit Descriptor will be selected. + */ +#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte From patchwork Wed Aug 29 07:03:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145388 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp340090ljw; Wed, 29 Aug 2018 00:03:38 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZGHZjZkdf68hJ5TWvfbzNN98YGw7MCDSxjHtiPSHNTYqFzBP8MBi42ymTjP+/ZX6x2udFn X-Received: by 2002:a65:6309:: with SMTP id g9-v6mr4588670pgv.153.1535526218746; Wed, 29 Aug 2018 00:03:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535526218; cv=none; d=google.com; s=arc-20160816; b=MoZmZ0Lf52eLGRd4j2uzJbuRv4VGg6msil3yBoYLOqan1lW+s9uBTlHSDevyItTdlX DOqq0khSi1YcPJu3wgPVw3GkbnXSKuf1CD+zLsSNVnhW9uJwegiY4Ld77kf84/rwUAtV x+TAa5fYI79Sn6iJrL2Qcem22k/VfIegas94pkLu1xIiacM4y/tilkY21PePQiavOX9W DOXEdbxLgqy4bSHfmR8N2gHkzePaE/+EbigstcbXA4HSS//o8KYd3cvngmMidSnEulLg O+5y2KZ5rUwPenJHsJglksPkjCZLnf2SQZKdGUGLmRPcjLYjt3RPjZ83HXGk0Oxcwd+w WHwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=gVnMBXKc4i1JKgy6ffbRwQOZ0ThpKQAJZ1YKfPm++hw=; b=LG0LiUKOtJ760JFGpnl0nswjXF5v8gFDpvwG7rtoiWl/iN9eaWLJA0C5TnlPu6r5cQ YQcrSxMTTu5cLE9Y6R2XinL/pj7U6bh/eSsS7XLefWECqJaJ/PjEaIDIdrvEzauC1Zu3 0RSVTKyCXdzhVhFKtZiHfOUpe+Jf+taZ4pTsVT+pKIHJ6Ed5jxvLXthZvXfuhCZxjGSz pmI22CAqtDd/JcX9GQ8vfxds3ka/FfJClkpMikfO3wEUKky2U4DF6hYq/SKJ5aiZ5D3z jaTjjEv0VnkuhtuSdkTy3e1VdXd9aYAfdoK6LgLUHtqQz1CdZx/JtMX5aQz0+roJ8c30 r82g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZgS7aX3G; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t64-v6si2959480pgd.176.2018.08.29.00.03.38; Wed, 29 Aug 2018 00:03:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZgS7aX3G; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727749AbeH2K7B (ORCPT + 32 others); Wed, 29 Aug 2018 06:59:01 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:43704 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727172AbeH2K7B (ORCPT ); Wed, 29 Aug 2018 06:59:01 -0400 Received: by mail-pl1-f195.google.com with SMTP id x6-v6so1879566plv.10 for ; Wed, 29 Aug 2018 00:03:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gVnMBXKc4i1JKgy6ffbRwQOZ0ThpKQAJZ1YKfPm++hw=; b=ZgS7aX3Gd161MtYIFxe4+J6bndokBsbo5aXCfXNj3pxipKi+TVYcErEWiGn27HJGHL UWVYIe2mMiv4As65G44FqFrne5ummVTBxIV0F+IQ0LUUVXUVOi6kTX0Bpo8aLatbXUaY f526m9PouwRhPGgltyy115t1Q9tRqkrsiwdBg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gVnMBXKc4i1JKgy6ffbRwQOZ0ThpKQAJZ1YKfPm++hw=; b=GBp2yYC3/JAlJLzo4JiLPI3jKi72BTetCrzDSAwlMVXZCldwpBDTS9EIB6PZVb1qw/ L32VbbWdYIUqJ+/sHV4RxZjhd3yHHw6URAYEEEvl6gWpYK9DhIeYeCABXHZrrpsjIiSo olU8G8josTreLXrSih38G2mD968fbKwfI4pLLet2/30sUxrgM8LHUXHknCjN/uubbneu AItThwx+wG1H9F50m3h6TsyjHmn6AOZkdJUsGPjBdcq9t4DjE6aVHEsMxqc7xgUDV0m/ 0KarsPecuHMvBZMpwq55SwpKidYFd/fEP6vx8YYnemDC01KON2asKpW1dvfWIUNCVk6W 0gdw== X-Gm-Message-State: APzg51Atbx+SK/rMTxMeuvT9Ci5w4WYdH1zyN+doLh/7WkoG4kiZxlrR jUDzRGF2k5AVzoMjod+0FZLAIg== X-Received: by 2002:a17:902:850c:: with SMTP id bj12-v6mr4823484plb.330.1535526216022; Wed, 29 Aug 2018 00:03:36 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:35 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 5/9] mmc: sdhci: Add 32-bit block count support for v4 mode Date: Wed, 29 Aug 2018 15:03:00 +0800 Message-Id: <1535526184-32718-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Since using 32-bit Block Count would cause problems for auto-cmd23, it can be chosen via host->quirk2. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 14 +++++++++++++- drivers/mmc/host/sdhci.h | 8 ++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 17345b6..604bf4c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1073,7 +1073,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + /* + * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count + * can be supported, in that case 16-bit block count register must be 0. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode && + (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); + } else { + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + } } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c5cc513..f7a1079 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) @@ -462,6 +463,13 @@ struct sdhci_host { * obtainable timeout. */ #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) +/* + * 32-bit block count may not support eMMC where upper bits of CMD23 are used + * for other purposes. Consequently we support 16-bit block count by default. + * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit + * block count. + */ +#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ From patchwork Wed Aug 29 07:03:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145389 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp340148ljw; Wed, 29 Aug 2018 00:03:43 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZlpJlHYhd+YuVdlVK+k9DrtoZsdI7qIywAytPK9DeJ2QQis/M9U9k9fDdS0NxskWP/vSt/ X-Received: by 2002:a62:4808:: with SMTP id v8-v6mr4681675pfa.89.1535526223574; Wed, 29 Aug 2018 00:03:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535526223; cv=none; d=google.com; s=arc-20160816; b=KA34ghk31rhfEBf68o0E84fjIiQtYFTX0Yt+8/EcAf3/4QnkYZa6+VXmgdH6Ha8juZ aAB1iwv7daiSqUs9NVdQ90spXtFWW9iweFROpEXUrKC+zZhvmcKQRPLVgQO4FhR6bNKM nAIE4dg+RWMH3AAgv5dHc0sd9ojPLlISBSbDLwgCuKwwrZQn1Zi8tnvttMx7nFFzYr+h 9ucavd32zlotuddOWqjl6CUOBMhCpxQjo5qjAoqWxv9O82wRmQllo43HhozYMEukKNiu +tYn+qeocZXCam5ZxZgiTSr0B+1y8fml5ST7pL/BIDGOIsOWSikKKKhSCufmx5pLhaAm wr6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=9gO45GPUCiWNoJSPPW5yykw6lOn1on3+rP/v8SuzWGk=; b=aesYZPItCUI9Xsne5iucEPbwy9Pe20KLa7cuURzSpY06Bx2JyNwI9M/6XnhNNGxRBA pdbN39zsWVfnVpI67tZn3szx6FHmo4lGBsJUfRnSsJ5IB5e1KvUCRRIf8FMN/mokRCB4 4ovhmCOHWg9pUfkCDvE23Ql2AzDIqMkoHHnnJGCpGrn2/KMyOF+fte44I2xpTjePbAxH K5X9AQfa1ypTehGLLVn5j1l5k9piy9+KnvES7XxQyVd3x0q7kBDz6+KCgIifiNLdSoTO 6C4WKigAv1I9CbHZmC948V/xhBYyHUgrXU7AOyYiEry0XUn5UQoshBgSUJd55H3nZkFF TWLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QBFWRQX0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t64-v6si2959480pgd.176.2018.08.29.00.03.43; Wed, 29 Aug 2018 00:03:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QBFWRQX0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727781AbeH2K7G (ORCPT + 32 others); Wed, 29 Aug 2018 06:59:06 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:46926 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727172AbeH2K7F (ORCPT ); Wed, 29 Aug 2018 06:59:05 -0400 Received: by mail-pg1-f194.google.com with SMTP id b129-v6so1903607pga.13 for ; Wed, 29 Aug 2018 00:03:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9gO45GPUCiWNoJSPPW5yykw6lOn1on3+rP/v8SuzWGk=; b=QBFWRQX0gaMKEq94OiPVi2I1NokcHktXgosg718cMFPkhord4M7chknNgxq8A2jmQj x06VfYu0EJETEi2z/cDBCJCJ0siqFU0S5OPRdYA9iXvj1SgN9zgcWt3HBSVW8vWLILlz 2OvFYmmAM+K2bS4ZEIoUgPzpEeGwH0MVRT/tI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9gO45GPUCiWNoJSPPW5yykw6lOn1on3+rP/v8SuzWGk=; b=F2JhdB7VslOG0Fpf5CpjEZZWUYrMR1Hg0ZufA1L0fXrtuotIF/c5kBrXwdF8xUF3Ew 9cC220mHXuIGtRaw2Jzx7Uk4nk79MPaxzeC/EVMx8D8HPl8CI6GBJ+9V6tcHEmYGXaQn 0onG5r3G7A1pzQm8MhUvmrvkWtf7WsSLoHBHWvLCfhmAXA+l0YfA+3DiipQmkHVqrhKr b1/unn1xp1h+xRQhyKUOWYVA4q9bKziDX42axLYvl/u8HSZFuNYKRWb8oU9YFG4XnaxK QY4FYOOKBZg8Zbwq9dy8/R7o7z2F7RuMB+QvxNM5kEAFAphsDEc99dYkVPviRKLYqbSE dCIA== X-Gm-Message-State: APzg51CpT5Si0bZUiZ8Bao/fxG7ImLLsLMetsXr+Wk+fSxsJLJPrS5nh yAJvHjC2nYbhQSR4Cn2N0ElHJg== X-Received: by 2002:a65:5189:: with SMTP id h9-v6mr4598889pgq.13.1535526220465; Wed, 29 Aug 2018 00:03:40 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:39 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 6/9] mmc: sdhci: Add Auto CMD Auto Select support Date: Wed, 29 Aug 2018 15:03:01 +0800 Message-Id: <1535526184-32718-7-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As SD Host Controller Specification v4.10 documents: Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. Selection of Auto CMD depends on setting of CMD23 Enable in the Host Control 2 register which indicates whether card supports CMD23. If CMD23 Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is used. In case of Version 4.10 or later, use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable. This patch add this new mode support. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 49 ++++++++++++++++++++++++++++++++++++++---------- drivers/mmc/host/sdhci.h | 2 ++ 2 files changed, 41 insertions(+), 10 deletions(-) -- 2.7.4 Acked-by: Adrian Hunter diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 604bf4c..62d843ac90 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1095,6 +1095,43 @@ static inline bool sdhci_auto_cmd12(struct sdhci_host *host, !mrq->cap_cmd_during_tfr; } +static inline void sdhci_auto_cmd_select(struct sdhci_host *host, + struct mmc_command *cmd, + u16 *mode) +{ + bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && + (cmd->opcode != SD_IO_RW_EXTENDED); + bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23); + u16 ctrl2; + + /* + * In case of Version 4.10 or later, use of 'Auto CMD Auto + * Select' is recommended rather than use of 'Auto CMD12 + * Enable' or 'Auto CMD23 Enable'. + */ + if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) { + *mode |= SDHCI_TRNS_AUTO_SEL; + + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (use_cmd23) + ctrl2 |= SDHCI_CMD23_ENABLE; + else + ctrl2 &= ~SDHCI_CMD23_ENABLE; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + + return; + } + + /* + * If we are sending CMD23, CMD12 never gets sent + * on successful completion (so no Auto-CMD12). + */ + if (use_cmd12) + *mode |= SDHCI_TRNS_AUTO_CMD12; + else if (use_cmd23) + *mode |= SDHCI_TRNS_AUTO_CMD23; +} + static void sdhci_set_transfer_mode(struct sdhci_host *host, struct mmc_command *cmd) { @@ -1123,17 +1160,9 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; - /* - * If we are sending CMD23, CMD12 never gets sent - * on successful completion (so no Auto-CMD12). - */ - if (sdhci_auto_cmd12(host, cmd->mrq) && - (cmd->opcode != SD_IO_RW_EXTENDED)) - mode |= SDHCI_TRNS_AUTO_CMD12; - else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { - mode |= SDHCI_TRNS_AUTO_CMD23; + sdhci_auto_cmd_select(host, cmd, &mode); + if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); - } } if (data->flags & MMC_DATA_READ) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f7a1079..4a19ff8 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -42,6 +42,7 @@ #define SDHCI_TRNS_BLK_CNT_EN 0x02 #define SDHCI_TRNS_AUTO_CMD12 0x04 #define SDHCI_TRNS_AUTO_CMD23 0x08 +#define SDHCI_TRNS_AUTO_SEL 0x0C #define SDHCI_TRNS_READ 0x10 #define SDHCI_TRNS_MULTI 0x20 @@ -185,6 +186,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CMD23_ENABLE 0x0800 #define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 From patchwork Wed Aug 29 07:03:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145390 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp340200ljw; Wed, 29 Aug 2018 00:03:47 -0700 (PDT) X-Google-Smtp-Source: ANB0VdasEEwmeQ6jjlz9DWUJprnDiGFpoBLYZ9pVKz9dw4PsU/hxlLazJsKgnxlCCZqLX8sPEUhq X-Received: by 2002:a63:ad07:: with SMTP id g7-v6mr4535973pgf.19.1535526227507; Wed, 29 Aug 2018 00:03:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535526227; cv=none; d=google.com; s=arc-20160816; b=wPksZDfnrWoRFODEWQX7fDC2RIOr6wMmqbyuWJDk4CgsbfZy+pEeluQBSgKMmTxoDy jpMun/Zcm8O8QXba5H4FvXj/63VShPEusl+JwSSQdtSfBZw10NkPP7AsNKhoSaSPbwDO oI18+EpcwhX8blqlCeoLEOqyjmafUfJQ8H1Z9YXMS/mg+qXcjt2vWKPzTm2AZizPa32R hWZt+HoMGqYC8W6R7E5RUf5y5X2Tqico4ko2wYzFoaW4w+6v0bMnuG9bgUNF9GaDaanr QLDj5Z/QjqDq1z8XPOhr9+/nS1NVnBUL8hbO6QMuAVQZEsHcxmvqRpHLJ5nikXk8w3bg jwpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=F6JNjnqOBxraoAmJ2G9nQq3A9aaEWZWPodCkmFELEA4=; b=qkn0GPkVJCx2V8a7Ep9N36CgVOy333kNez6QpGBxmKl4KN2I+zuspvlMTrLOL+WYPt V9zf44ECvTTVwrAhcAySrenRJnU8ypKQi/EHVMKX0+nyujmxCOKKod/aXlgYadgGvdPY 7hTzPtubA5fsVjXErneILdw7Yevu36Ui+hF7QktJ8i9LkGL/Bn9cAUwmT0DqDksjz4yP N5IlED4C0JDPBMRlZ7sQtc0rwlS/U3PZayx8gh15yjU1DJmgHBo/qsQmDLw9Ervoq51C tjdlX8Nwx9JahRpaQBYZxcxSzcAsuv0HmIaSqFkiZxZI1VpSQIfDOsJQi/hapqjSy8E1 t2qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FTt8+uiI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p1-v6si3020050pfb.280.2018.08.29.00.03.47; Wed, 29 Aug 2018 00:03:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FTt8+uiI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727816AbeH2K7K (ORCPT + 32 others); Wed, 29 Aug 2018 06:59:10 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:37307 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727785AbeH2K7J (ORCPT ); Wed, 29 Aug 2018 06:59:09 -0400 Received: by mail-pl1-f193.google.com with SMTP id d12-v6so1893802pls.4 for ; Wed, 29 Aug 2018 00:03:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F6JNjnqOBxraoAmJ2G9nQq3A9aaEWZWPodCkmFELEA4=; b=FTt8+uiIDtMNr76i4SHHbEdmo3x0fQckM4/6nQz3cKegXczL/kS8xRQ86loF+ym1uP 3Fpd5LHKwS30oEPpmqKE/5WBxvTynx6qm7zdYVXJzSnMnivIcq/YIMSSdvCqnFxpwflb ohKMYLCNY5PjsqLIsr49T3uTBongbaNEe/jJg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F6JNjnqOBxraoAmJ2G9nQq3A9aaEWZWPodCkmFELEA4=; b=UydP+YzQ4Agt3W67qlrekxq4/q9sasFw1w3btTTFHzcmbyp0JUGO4+jjuzyOrv0f05 MaLd20NkklNibnDWkAtbao7GX7bBaHdRVgCqUkDt17c93Sp/ZKbKOtac883Z7lZ8QZKZ EhZ6jcKFPa96L/MolL+qwL8UeVeWM1Obmsg7l3uRsFMiL243ELLS0x/msKD71xh/MeIt U/xowuQ4PxexWVnNKonl9/BzsR7KutzFwHcwgatRi4sFXqC/nVcVAGbqQzWpVdFYybTK G+aM4wHaWU0tquew9kYsNmf02bFGsIpUKQM/5gxH6e4pJRS3SPUE8+y+oCDUoIQ/WhaF OXdw== X-Gm-Message-State: APzg51Aiwfq/dsvwVCboYtMD1t1lJbRRvfOgQpJb7IO4DgH/1UJOSwz1 jA1nAqB7aH/QYXjrkB4AI034UA== X-Received: by 2002:a17:902:a987:: with SMTP id bh7-v6mr4834081plb.182.1535526224623; Wed, 29 Aug 2018 00:03:44 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:43 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 7/9] mmc: sdhci: SDMA may use Auto-CMD23 in v4 mode Date: Wed, 29 Aug 2018 15:03:02 +0800 Message-Id: <1535526184-32718-8-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address register (05Fh-058h) instead of using register (000h-004h) to indicate its system address of data location. The register (000h-004h) is re-assigned to 32-bit Block Count and Auto CMD23 argument, so then SDMA may use Auto CMD23. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 62d843ac90..ac92e0f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3834,10 +3834,14 @@ int sdhci_setup_host(struct sdhci_host *host) if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) host->flags |= SDHCI_AUTO_CMD12; - /* Auto-CMD23 stuff only works in ADMA or PIO. */ + /* + * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO; + * For v4 mode, SDMA may use Auto-CMD23 as well. + */ if ((host->version >= SDHCI_SPEC_300) && ((host->flags & SDHCI_USE_ADMA) || - !(host->flags & SDHCI_USE_SDMA)) && + (!host->v4_mode && !(host->flags & SDHCI_USE_SDMA)) || + (host->v4_mode && (host->flags & SDHCI_USE_SDMA))) && !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { host->flags |= SDHCI_AUTO_CMD23; DBG("Auto-CMD23 available\n"); From patchwork Wed Aug 29 07:03:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145391 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp340278ljw; Wed, 29 Aug 2018 00:03:53 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYB2Gz+lMDvhcO9kDcnTAtCz1UxMi5Wk8d+rbcUHLFVQFaZxj3iPxn7iygfkvDGFUx2Amzx X-Received: by 2002:a17:902:ab93:: with SMTP id f19-v6mr4605828plr.252.1535526233225; Wed, 29 Aug 2018 00:03:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535526233; cv=none; d=google.com; s=arc-20160816; b=zMwFuWBhtRHSWnhVCLEFAi2RYNI3biTR67+Aechr3rwtgQK5Y8SPGVLDg2KlAXYBpr dFc2yPoaux/eEja2QVO/I+KZEkuQzxYdqdel0YVV653ZHbSXeAtn/CwXuXvF2OF331Hd cXWcWTdcqm/+iTbnDis6Ha67bmH5qNE431lTy1o3GY/n8mUeAfzN2ZTVHzPnOzWIdmKd Vsg072t9Z7n3xgt+YDFOHKN1ZbetRWSETEyIJlimPf2SyOvOQzIAgMGtpXC2KI70yHSn 1rSf4FF8M6Cs3bmZpvPBkiI32Ly0K12iN0niguceW4HrqUe7ND5SpR0ofwlz0i5Ny+8/ oOoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=EOMZ+0K209Ld8iUvEB262q4DzLp3hVOASvPvbcCcg2M=; b=buHkQ/YvUb1YWHGNSxLB6tAGxaRdRHKAiyOCNwQ5R1QOxVgU04VGJZkWVuem1Wz6zq oZTSZzBUjuX2o2nj8ubleiEkiPEZT9LOuDlwdSmkom6UysMX1HrExphoNHu9VOB1+CEt 9ibk2r3xAZOWG24TyNzdvLBK3ih40fUjtcE/aUQFnxjEOgh8w7XM7Nx7p9LqBeVtG0Gw qNz6EtaOnZqTE15XZpS+B3egN4gkYlypNt10szzkbakOwn7Y9vqJdARgm6CyhZuoctUw gESwxzGKZ/UEdmnTRSZP5GgsfqFfEDA31f9/mZQXHat2PSSK/x6qYDs1re42qq5ZSDtC qevA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JUqpZI61; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x6-v6si2810814pge.100.2018.08.29.00.03.52; Wed, 29 Aug 2018 00:03:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JUqpZI61; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727838AbeH2K7Q (ORCPT + 32 others); Wed, 29 Aug 2018 06:59:16 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:36985 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727526AbeH2K7P (ORCPT ); Wed, 29 Aug 2018 06:59:15 -0400 Received: by mail-pf1-f194.google.com with SMTP id h69-v6so1859929pfd.4 for ; Wed, 29 Aug 2018 00:03:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EOMZ+0K209Ld8iUvEB262q4DzLp3hVOASvPvbcCcg2M=; b=JUqpZI61TEon5sfgOcZNnaAZXcYm0PEL3aOemvMnN6FR5HYF/TXQuOhczmHF/bFTrS zssrxO5GF5MefrC2mZ/XfjgL87Bhb2z24urqAcHBKzlrGNMiLJR7MUGrNtad7JAaEpA2 doOln/nrKkAC4EcRiI0G0zCAuTiFihET3GDcU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EOMZ+0K209Ld8iUvEB262q4DzLp3hVOASvPvbcCcg2M=; b=W56jAN6BSXcI3XaoHpUxuOpHVp0QRu+EGi1t7iZQWUlWUSLRYbx6BXmNjOu192DAVl KTSxEKxTfNo7noFYY28WepP3VOsDKwyC/hRPcURn8PCvx3abtkiQcuUuW+9zshq77faj f7GRsREgY/XsG3dvLSzCtQWkySyU4j1eXdVKk+mOvP97qXY45t+X9xc3S26xgFI5cKks +k99q4A4L73ARZ8YW0JDOa+ubd5z4aFOHSyrC9WFxk3G7wrm/QmJ3weZPWwRQP1FD3Zk bwVlHEoOkzkldGtUiLq4/1oepEJ3wqOCkemSpjPwIxuvnxY6ydM8SQ7qFMLGzhz0pQYZ 8YPw== X-Gm-Message-State: APzg51CCJeEYiDt27MXgTkD4iQrnGlZDhyT3PJW4NP0IwqTOHtJ++oru r48rC9HiEIZWJjhVbQF3PbU+rA== X-Received: by 2002:a62:760a:: with SMTP id r10-v6mr4677067pfc.207.1535526230129; Wed, 29 Aug 2018 00:03:50 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:49 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 8/9] mmc: sdhci-sprd: Add Spreadtrum's initial host controller Date: Wed, 29 Aug 2018 15:03:03 +0800 Message-Id: <1535526184-32718-9-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunyan Zhang This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by: Billows Wu Signed-off-by: Chunyan Zhang --- drivers/mmc/host/Kconfig | 13 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-sprd.c | 498 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 512 insertions(+) create mode 100644 drivers/mmc/host/sdhci-sprd.c -- 2.7.4 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index d09feb6..cf984f0 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -593,6 +593,19 @@ config MMC_SDRICOH_CS To compile this driver as a module, choose M here: the module will be called sdricoh_cs. +config MMC_SDHCI_SPRD + tristate "Spreadtrum SDIO host Controller" + depends on ARCH_SPRD + depends on MMC_SDHCI_PLTFM + select MMC_SDHCI_IO_ACCESSORS + help + This selects the SDIO Host Controller in Spreadtrum + SoCs, this driver supports R11(IP version: R11P0). + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_TMIO_CORE tristate diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index a835d1a..5363d06 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -92,6 +92,7 @@ obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o +obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o obj-$(CONFIG_MMC_CQHCI) += cqhci.o ifeq ($(CONFIG_CB710_DEBUG),y) diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c new file mode 100644 index 0000000..decd8cd --- /dev/null +++ b/drivers/mmc/host/sdhci-sprd.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Secure Digital Host Controller +// +// Copyright (C) 2018 Spreadtrum, Inc. +// Author: Chunyan Zhang + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sdhci-pltfm.h" + +/* SDHCI_ARGUMENT2 register high 16bit */ +#define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) + +#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 +#define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) +#define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) +#define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) +#define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) + +#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 +#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) +#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) + +#define SDHCI_SPRD_REG_DEBOUNCE 0x28C +#define SDHCI_SPRD_BIT_DLL_BAK BIT(0) +#define SDHCI_SPRD_BIT_DLL_VAL BIT(1) + +#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B + +/* SDHCI_HOST_CONTROL2 */ +#define SDHCI_SPRD_CTRL_HS200 0x0005 +#define SDHCI_SPRD_CTRL_HS400 0x0006 + +/* + * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is + * reserved, and only used on Spreadtrum's design, the hardware cannot work + * if this bit is cleared. + * 1 : normal work + * 0 : hardware reset + */ +#define SDHCI_HW_RESET_CARD BIT(3) + +#define SDHCI_SPRD_MAX_CUR 0xFFFFFF +#define SDHCI_SPRD_CLK_MAX_DIV 1023 + +#define SDHCI_SPRD_CLK_DEF_RATE 26000000 + +struct sdhci_sprd_host { + u32 version; + struct clk *clk_sdio; + struct clk *clk_enable; + u32 base_rate; + int flags; /* backup of host attribute */ +}; + +#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) + +static void sdhci_sprd_init_config(struct sdhci_host *host) +{ + u16 val; + + /* set dll backup mode */ + val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); + val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; + sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); +} + +static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) +{ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return SDHCI_SPRD_MAX_CUR; + + return readl_relaxed(host->ioaddr + reg); +} + +static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) +{ + /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return; + + if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) + val = val & SDHCI_SPRD_INT_SIGNAL_MASK; + + writel_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) +{ + /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_BLOCK_COUNT)) + return; + + writew_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) +{ + /* + * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the + * standard specification, sdhci_reset() write this register directly + * without checking other reserved bits, that will clear BIT(3) which + * is defined as hardware reset on Spreadtrum's platform and clearing + * it by mistake will lead the card not work. So here we need to work + * around it. + */ + if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { + if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) + val |= SDHCI_HW_RESET_CARD; + } + + writeb_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) +{ + u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + ctrl &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); +} + +static inline void +sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) +{ + u32 dll_dly_offset; + + dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); + if (en) + dll_dly_offset |= mask; + else + dll_dly_offset &= ~mask; + sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); +} + +static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) +{ + u32 div; + + /* select 2x clock source */ + if (base_clk <= clk * 2) + return 0; + + div = (u32) (base_clk / (clk * 2)); + + if ((base_clk / div) > (clk * 2)) + div++; + + if (div > SDHCI_SPRD_CLK_MAX_DIV) + div = SDHCI_SPRD_CLK_MAX_DIV; + + if (div % 2) + div = (div + 1) / 2; + else + div = div / 2; + + return div; +} + +static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, + unsigned int clk) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + u32 div, val, mask; + + div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); + + clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); + sdhci_enable_clk(host, clk); + + /* enable auto gate sdhc_enable_auto_gate */ + val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); + mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | + SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; + if (mask != (val & mask)) { + val |= mask; + sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); + } +} + +static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) +{ + bool en = false; + + if (clock == 0) { + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + } else if (clock != host->clock) { + sdhci_sprd_sd_clk_off(host); + _sdhci_sprd_set_clock(host, clock); + + if (clock <= 400000) + en = true; + sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | + SDHCI_SPRD_BIT_POSRD_DLY_INV, en); + } else { + _sdhci_sprd_set_clock(host, clock); + } +} + +static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); +} + +static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) +{ + return 400000; +} + +static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + u16 ctrl_2; + + if (timing == host->timing) + return; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (timing) { + case MMC_TIMING_UHS_SDR12: + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + break; + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + break; + case MMC_TIMING_UHS_SDR50: + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; + break; + case MMC_TIMING_UHS_SDR104: + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + break; + case MMC_TIMING_MMC_HS200: + ctrl_2 |= SDHCI_SPRD_CTRL_HS200; + break; + case MMC_TIMING_MMC_HS400: + ctrl_2 |= SDHCI_SPRD_CTRL_HS400; + break; + default: + break; + } + + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + +static void sdhci_sprd_hw_reset(struct sdhci_host *host) +{ + int val; + + /* + * Note: don't use sdhci_writeb() API here since it is redirected to + * sdhci_sprd_writeb() in which we have a workaround for + * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can + * not be cleared. + */ + val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); + val &= ~SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + /* wait for 10 us */ + usleep_range(10, 20); + + val |= SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + usleep_range(300, 500); +} + +static struct sdhci_ops sdhci_sprd_ops = { + .read_l = sdhci_sprd_readl, + .write_l = sdhci_sprd_writel, + .write_b = sdhci_sprd_writeb, + .set_clock = sdhci_sprd_set_clock, + .get_max_clock = sdhci_sprd_get_max_clock, + .get_min_clock = sdhci_sprd_get_min_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, + .hw_reset = sdhci_sprd_hw_reset, +}; + +static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + host->flags = sprd_host->flags; + + /* + * From version 4.10 onward, ARGUMENT2 register is also as 32-bit + * block count register which doesn't support stuff bits of + * CMD23 argument on Spreadtrum's sd host controller. + */ + if (host->version >= SDHCI_SPEC_410 && + mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && + (host->flags & SDHCI_AUTO_CMD23)) + host->flags &= ~SDHCI_AUTO_CMD23; + + sdhci_request(mmc, mrq); +} + +static const struct sdhci_pltfm_data sdhci_sprd_pdata = { + .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, + .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | + SDHCI_QUIRK2_USE_32BIT_BLK_CNT, + .ops = &sdhci_sprd_ops, +}; + +static int sdhci_sprd_probe(struct platform_device *pdev) +{ + struct sdhci_host *host; + struct sdhci_sprd_host *sprd_host; + struct clk *clk; + int ret = 0; + + host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); + if (IS_ERR(host)) + return PTR_ERR(host); + + host->dma_mask = DMA_BIT_MASK(64); + pdev->dev.dma_mask = &host->dma_mask; + host->mmc_host_ops.request = sdhci_sprd_request; + + host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_ERASE | MMC_CAP_CMD23; + ret = mmc_of_parse(host->mmc); + if (ret) + goto pltfm_free; + + sprd_host = TO_SPRD_HOST(host); + + clk = devm_clk_get(&pdev->dev, "sdio"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_sdio = clk; + sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); + if (!sprd_host->base_rate) + sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; + + clk = devm_clk_get(&pdev->dev, "enable"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_enable = clk; + + ret = clk_prepare_enable(sprd_host->clk_sdio); + if (ret) + goto pltfm_free; + + clk_prepare_enable(sprd_host->clk_enable); + if (ret) + goto clk_disable; + + sdhci_sprd_init_config(host); + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> + SDHCI_VENDOR_VER_SHIFT); + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + pm_suspend_ignore_children(&pdev->dev, 1); + + sdhci_enable_v4_mode(host); + + ret = sdhci_setup_host(host); + if (ret) + goto pm_runtime_disable; + + sprd_host->flags = host->flags; + + ret = __sdhci_add_host(host); + if (ret) + goto err_cleanup_host; + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + + return 0; + +err_cleanup_host: + sdhci_cleanup_host(host); + +pm_runtime_disable: + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + + clk_disable_unprepare(sprd_host->clk_enable); + +clk_disable: + clk_disable_unprepare(sprd_host->clk_sdio); + +pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int sdhci_sprd_remove(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + struct mmc_host *mmc = host->mmc; + + mmc_remove_host(mmc); + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + mmc_free_host(mmc); + + return 0; +} + +static const struct of_device_id sdhci_sprd_of_match[] = { + { .compatible = "sprd,sdhci-r11", }, + { } +}; +MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); + +#ifdef CONFIG_PM +static int sdhci_sprd_runtime_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + sdhci_runtime_suspend_host(host); + + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + return 0; +} + +static int sdhci_sprd_runtime_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + int ret; + + ret = clk_prepare_enable(sprd_host->clk_enable); + if (ret) + return ret; + + ret = clk_prepare_enable(sprd_host->clk_sdio); + if (ret) { + clk_disable_unprepare(sprd_host->clk_enable); + return ret; + } + + sdhci_runtime_resume_host(host); + + return 0; +} +#endif + +static const struct dev_pm_ops sdhci_sprd_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, + sdhci_sprd_runtime_resume, NULL) +}; + +static struct platform_driver sdhci_sprd_driver = { + .probe = sdhci_sprd_probe, + .remove = sdhci_sprd_remove, + .driver = { + .name = "sdhci_sprd_r11", + .of_match_table = of_match_ptr(sdhci_sprd_of_match), + .pm = &sdhci_sprd_pm_ops, + }, +}; +module_platform_driver(sdhci_sprd_driver); + +MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:sdhci-sprd-r11"); From patchwork Wed Aug 29 07:03:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145392 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp340331ljw; Wed, 29 Aug 2018 00:03:56 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbgTmv1JXDYqiBgp21iy1VeZucR1spr10rF/dqLpkIenRebc4VU8pVRE3JsslCsi3so5lr6 X-Received: by 2002:a17:902:925:: with SMTP id 34-v6mr4718419plm.307.1535526236458; Wed, 29 Aug 2018 00:03:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535526236; cv=none; d=google.com; s=arc-20160816; b=oMFwWJ67MNdUH2rzuLnZGP3AwmIaC/U3mcmXS9MJj+Ifp+vH+AAdIB72iLHaqCjZh1 mOKcctAEGsj8HUSIO4UVnLvD8hIm9T9+QIKJmBmQFUrC9gf/yGhFnQBsr+YFVnKfAPY+ 1IIAsIURI4tyP0NtQiYs0zvEx4H5tB6/UMj0uEuIB0g4+NZ+aIHm3JnlNWDBLB9cUvDJ e6IvlM7nVPQyuP59o3nacI8KSBVOeBT6za2lGp+ja8FMMNm64eMIAactvuMonrx0ruvi jr/OD9N/lFSi5vzvPIwxlBGG1HrUXPwMoNl/okzuk4Ys9QaQSZDVWpB6UCMKRdV3nZ2c GkMw== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id x6-v6si2810814pge.100.2018.08.29.00.03.56; Wed, 29 Aug 2018 00:03:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jr7z9Xrh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727866AbeH2K7T (ORCPT + 32 others); Wed, 29 Aug 2018 06:59:19 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:42646 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727526AbeH2K7T (ORCPT ); Wed, 29 Aug 2018 06:59:19 -0400 Received: by mail-pl1-f196.google.com with SMTP id g23-v6so1880652plq.9 for ; Wed, 29 Aug 2018 00:03:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/RXtHte8bNFCXLz2sWlB+/MjHMcewoMGpsLw3S8KcCM=; b=Jr7z9XrhU3HrcPk/AT/DjDvnFFmTvleGb0H/furxCuBSYyZzL7uKeWtLUYar+F4IIm Wrt2u60UvZF4n/jHJcSF2kmPpVoRuvu+KpbmsZeWZoPnrxTfLHtVhelmeOLNp4to8NNb 2scOigqUNNicqcWV8Z83dAFah/7kyxkvoRmRg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/RXtHte8bNFCXLz2sWlB+/MjHMcewoMGpsLw3S8KcCM=; b=ntuAL9LrX8NLPCLu1EG7qc9UdBWR7sDWlXv1q7GThCsyPuGT4XFYcazWicqShyVHAN WpaSnt5ZrJD0oCviHNibN+3b0YdizfbTYSyTlz14VVmLLKIk637MpiIQIcCBmO8SxxqM 67Li2uA6JRR5ZNFA8yUYRIXyfr3gmgmOCYkhg5L3BRxo8OQNAS5LtoYYOpbTapVUqDb8 w4dsiKlfN5lUIXfVaYfWhOK4uYDnj2RsGx/uTpZNBEIK4cyfMqZnznWPCgGQ23s1uOxy 2h2x/zhysLE9qXfqS3EfbrMdpa6yLhVlST/QdXM5lIuapRbWa4z+lZHjePe5V70BiIbC gYMQ== X-Gm-Message-State: APzg51AV3JxvQn1unyHPPdGhzLtsi0Il/spGxBkxIGFpwEo4ABdq+AfG 2cNbe3An/UsKWKMGmTlEiM62+w== X-Received: by 2002:a17:902:7203:: with SMTP id ba3-v6mr4757417plb.179.1535526234254; Wed, 29 Aug 2018 00:03:54 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:53 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 9/9] dt-bindings: sdhci-sprd: Add bindings for the sdhci-sprd controller Date: Wed, 29 Aug 2018 15:03:04 +0800 Message-Id: <1535526184-32718-10-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunyan Zhang This patch adds the device-tree binding documentation for Spreadtrum SDHCI driver. Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/mmc/sdhci-sprd.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sprd.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt new file mode 100644 index 0000000..45c9978 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt @@ -0,0 +1,41 @@ +* Spreadtrum SDHCI controller (sdhci-sprd) + +The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface +for MMC, SD and SDIO types of cards. + +This file documents differences between the core properties in mmc.txt +and the properties used by the sdhci-sprd driver. + +Required properties: +- compatible: Should contain "sprd,sdhci-r11". +- reg: physical base address of the controller and length. +- interrupts: Interrupts used by the SDHCI controller. +- clocks: Should contain phandle for the clock feeding the SDHCI controller +- clock-names: Should contain the following: + "sdio" - SDIO source clock (required) + "enable" - gate clock which used for enabling/disabling the device (required) + +Optional properties: +- assigned-clocks: the same with "sdio" clock +- assigned-clock-parents: the default parent of "sdio" clock + +Examples: + +sdio0: sdio@20600000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20600000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>; + assigned-clocks = <&ap_clk CLK_EMMC_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + status = "okay"; +};