From patchwork Thu Aug 30 08:21:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145526 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp536503ljw; Thu, 30 Aug 2018 01:22:12 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZ0+BUVCAF7WRDUnXWWLqxLlUTZUnbLNPlO1+7ReYB3nnVSiU1pakXvCyzSqO1PAczNge1e X-Received: by 2002:a17:902:8bc4:: with SMTP id r4-v6mr8932341plo.124.1535617332658; Thu, 30 Aug 2018 01:22:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535617332; cv=none; d=google.com; s=arc-20160816; b=OQNxYFd9UkIxjIU4lp+Ij5unEGTeKOiW4nIH1gj335AWTjJNuC3+X128SHIcpyF+Te KYc8HnztBJh3+/uU9s/ROcVoNOSLVMnpqlX4kZR/WZyR0ILPprIp9FnHVpRZOK9fJAse VyqrXkVKUz1Hzd/OP+WumU3ofFdvvR3gQka9zYTsWvIGXB05EzWUZLMKn2CGpkq695wh 7fqCsP9EAlSLBDQEmXQo0MUgHzrx8GR5wpRBhSnf8ORsuGhdbhH/sjUDEEcb+ewPmr31 blBbn+K/fr0QgyRRstnkFLJtX3JtMUM2trHMktkghlJ3yxicxxSkkCnTRkbFF7tDeCKP hWcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=wj6LwXf/jUT8nmKoqSVJBo3vcF/egS7nUByoGr88L4Q=; b=BSrMFbvnJUx3xCgYwl0/RY5yrOUk2PZfq0ub38QNx/wUfL+q3hzqyBUeXADrxaZDBa PCHQfYW/KWb3p1Qj1V6rhdXFwapPwRf+32EZpSG2GfwkIPJ5YaHNkTc3pBQpM3ilDyIg Epc7Sdi6HIXsM39YSvAm6kA6tesqFWrbJWDeSrq07wDIKhS3Ms4+TQmFVdHmP12BoxDP EvdJxHHoqyUR94nEJVwdi7lekwnG9xVekSSV6ZyaJ1M+ugUYOFxEOinzcYKot3H8hR4+ ZNSsArgkvMWJ1jIjrb55yedLIO8ScHPrU+SOXYkkghI0S7aeRAOaDlsv5+pG37GZ+ZCp jD1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jon+xq5T; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r34-v6si6362275pgb.656.2018.08.30.01.22.12; Thu, 30 Aug 2018 01:22:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jon+xq5T; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728009AbeH3MXJ (ORCPT + 5 others); Thu, 30 Aug 2018 08:23:09 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:42299 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728008AbeH3MXI (ORCPT ); Thu, 30 Aug 2018 08:23:08 -0400 Received: by mail-pf1-f194.google.com with SMTP id l9-v6so3546972pff.9 for ; Thu, 30 Aug 2018 01:22:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wj6LwXf/jUT8nmKoqSVJBo3vcF/egS7nUByoGr88L4Q=; b=jon+xq5Tky6PYU/p0fvDZeq0yrKRr3lHslFiLxKk450BYuaRzVEsYsxXsAsYXegIG5 8Kmzr+9KpbIYCYhKyFpVSoniiB021+DE5InFWFWTz0N7ZqWdy6Xbch6prxLHJM86+3ZS z0KfP3QTQSkvbD8m2VW7QwF8dd3dJm48hmAfA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wj6LwXf/jUT8nmKoqSVJBo3vcF/egS7nUByoGr88L4Q=; b=psM6gyNczar8ltaN5j6l3JYbuwVVjpkIsys8lmB3Ccr6JO6kmFjkdZqpcIZdzris2O j+pMz/WinvDFt17YNPquCr2l4EO0cgOujmi95J4xZx+WrDD3XyaZsr0u2M+CUzVvtcGs ES1n3ga/OJUSk96nO0LHkVxweWImqq7w3frMvEuDl5WC334oIGF5NRB0jHd4rTPh2ivk uxStZK0VnlCoueJfAulkZ6R36NEFtK37WEFYti7R0c57pQ2YVZq06c4+8QTVBcvlyucp oodIECa6Fj7id5v5ZgLyiREz6mO3FCvVtzvhfeKjSzTKFUR2a1C6iFV3jhk5GB0NtK/b 3uQg== X-Gm-Message-State: APzg51DeNv2JfPLlZOyoALdL0lAver1PvIQm04+mvCwOkQnHPTwKO2ah hrAsIBvVwnHt3KmpiAovByr+1Q== X-Received: by 2002:a65:650f:: with SMTP id x15-v6mr8942680pgv.127.1535617330612; Thu, 30 Aug 2018 01:22:10 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j22-v6sm8224885pfh.45.2018.08.30.01.22.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Aug 2018 01:22:09 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter , Rob Herring Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V8 3/9] mmc: sdhci: Change SDMA address register for v4 mode Date: Thu, 30 Aug 2018 16:21:39 +0800 Message-Id: <1535617305-16952-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> References: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org According to the SD host controller specification version 4.10, when Host Version 4 is enabled, SDMA uses ADMA System Address register (05Fh-058h) instead of using SDMA System Address register to support both 32-bit and 64-bit addressing. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 0c61105..6fb70da 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -727,7 +727,7 @@ static void sdhci_adma_table_post(struct sdhci_host *host, } } -static u32 sdhci_sdma_address(struct sdhci_host *host) +static dma_addr_t sdhci_sdma_address(struct sdhci_host *host) { if (host->bounce_buffer) return host->bounce_addr; @@ -735,6 +735,17 @@ static u32 sdhci_sdma_address(struct sdhci_host *host) return sg_dma_address(host->data->sg); } +static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr) +{ + if (host->v4_mode) { + sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS); + if (host->flags & SDHCI_USE_64_BIT_DMA) + sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI); + } else { + sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); + } +} + static unsigned int sdhci_target_timeout(struct sdhci_host *host, struct mmc_command *cmd, struct mmc_data *data) @@ -994,8 +1005,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) SDHCI_ADMA_ADDRESS_HI); } else { WARN_ON(sg_cnt != 1); - sdhci_writel(host, sdhci_sdma_address(host), - SDHCI_DMA_ADDRESS); + sdhci_set_sdma_addr(host, sdhci_sdma_address(host)); } } @@ -2830,7 +2840,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) * some controllers are faulty, don't trust them. */ if (intmask & SDHCI_INT_DMA_END) { - u32 dmastart, dmanow; + dma_addr_t dmastart, dmanow; dmastart = sdhci_sdma_address(host); dmanow = dmastart + host->data->bytes_xfered; @@ -2838,12 +2848,12 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) * Force update to the next DMA block boundary. */ dmanow = (dmanow & - ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + + ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + SDHCI_DEFAULT_BOUNDARY_SIZE; host->data->bytes_xfered = dmanow - dmastart; - DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n", - dmastart, host->data->bytes_xfered, dmanow); - sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); + DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n", + &dmastart, host->data->bytes_xfered, &dmanow); + sdhci_set_sdma_addr(host, dmanow); } if (intmask & SDHCI_INT_DATA_END) { @@ -3590,8 +3600,8 @@ int sdhci_setup_host(struct sdhci_host *host) } } - /* SDMA does not support 64-bit DMA */ - if (host->flags & SDHCI_USE_64_BIT_DMA) + /* SDMA does not support 64-bit DMA if v4 mode not set */ + if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode) host->flags &= ~SDHCI_USE_SDMA; if (host->flags & SDHCI_USE_ADMA) { From patchwork Thu Aug 30 08:21:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145532 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp536875ljw; Thu, 30 Aug 2018 01:22:41 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaHyafR3v3GnAFkK5X82fG5zIrKKH5MtxoOp2EX54J8OfFyCjj6knb82ic0k58fYWF+AEg2 X-Received: by 2002:a17:902:4d46:: with SMTP id o6-v6mr9136691plh.59.1535617361443; Thu, 30 Aug 2018 01:22:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535617361; cv=none; d=google.com; s=arc-20160816; b=dyawAEqFSjqJf4sRqHpQxr928FuvsmmWqyXyhF8NAde+QOwaFOVBwGcjymO2AuimK1 bjhQLaszNg+Rh2iVu9hNTlWCehBP0c4f/TF0ARgQ71FAqcNUFYhDnhoYAKDEHbKV6dtg OgxVGZji/I1oX/shLZZ5Uu5EfoJl6MB6KIGDyVI8l2BHyWlpyBuGUlJ0FDUcHsX6KN1Y FJCFVK9PmWvKejzSiU+BjFoMPNMMn3W+aP1sXq68ODeFHLle+UokeWA9RlZ6149e1jO6 Hsxvnm1wWPIFPTq0y2AO/9KJaLbMlDuhIan96TibqLzUAmDlz0vj4OyKELqQJfzjv44C /vnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=/RXtHte8bNFCXLz2sWlB+/MjHMcewoMGpsLw3S8KcCM=; b=gLnX1K7hFa1uFKz4sruK18NLacj9SBP0dx+G0afsQF48megRUx1w6fH16NEiYY3Mqk TDe3P2HszjcyZoK1x1luSxy5WrXjW3JcwaYl8Bifs8Mq/4yOFNiwHTJptopxdO7wu9nO rNYyIU5qyNjHVQdXxyddA4R8CGlkVwbCZpODqZL7O5LPqq5I9E9GFe89N5roI69p7HRt q/zKpyRPqrn6Xjo1qxkOrq5mi1ZCMeFwUJSaY4Wgu8c/0YBuVLf/RJOV9NQUvHTKrfnF M7fWFG6t8XF9mgaIfPPjudTN5Mrm+zwzmc6QljGWSMygIcPDST2VWxUWFoeN8PBVzn4e SrtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ehdLvAHu; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a6-v6si5707520plz.227.2018.08.30.01.22.41; Thu, 30 Aug 2018 01:22:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ehdLvAHu; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728134AbeH3MXi (ORCPT + 5 others); Thu, 30 Aug 2018 08:23:38 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:40508 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728068AbeH3MXh (ORCPT ); Thu, 30 Aug 2018 08:23:37 -0400 Received: by mail-pf1-f194.google.com with SMTP id s13-v6so3550340pfi.7 for ; Thu, 30 Aug 2018 01:22:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/RXtHte8bNFCXLz2sWlB+/MjHMcewoMGpsLw3S8KcCM=; b=ehdLvAHulsqEGy2bI4CKy7Yju2jHtCBeOXunvc9ihc53cj2WslPESCJbLHPy1vlTvy E5paeKwr31lXBvDbVokPkwrPYr9JEkaEUbQw9yqhF3NaN+wyhQjNA6FcnMP49yd6Z83z K4WhB54ZIzBNrW5MufdnAHX7F7gaN8WAyiYeA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/RXtHte8bNFCXLz2sWlB+/MjHMcewoMGpsLw3S8KcCM=; b=ZmrfRNUsSLq+pYcKChRPWwc9zxyT06TQ6mVM4qv0tSkmpnWpSmSOD7ESExAWeSAzCC dw0QOcjH7og99o/Y+Fba8CLiBAGmEftsSWC6iYzQGhWRvgPQ+23b2FdxIFV4mPqeo5Ib m39w753kDZW9gEjJa3BTDKn4etvYcTf0RFCzUOO/ppIjfq6GF53oXXOsgu4LFTafa2ee D7LcCvcc2atudkHjbh3ESttme10RpVzuEI71JIrSefC1LngdvkQ711hOz1BOx+TxlFBj 3pfNopxoPzaNP6EonfpV3KZ5MOOFq0iik+6Wm92NhxMlzqA66DCfbjJSR3gQcGBwZBZy Cejg== X-Gm-Message-State: APzg51DyPs0/OInoVEOIQeYd2rizj5leXCE4tBZKSMNOLrkeTcUIQRe6 A/6c/bSuGyfs673D7QBU5jrKwQ== X-Received: by 2002:a65:6413:: with SMTP id a19-v6mr1774313pgv.359.1535617359659; Thu, 30 Aug 2018 01:22:39 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j22-v6sm8224885pfh.45.2018.08.30.01.22.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Aug 2018 01:22:38 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter , Rob Herring Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V8 9/9] dt-bindings: sdhci-sprd: Add bindings for the sdhci-sprd controller Date: Thu, 30 Aug 2018 16:21:45 +0800 Message-Id: <1535617305-16952-10-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> References: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Chunyan Zhang This patch adds the device-tree binding documentation for Spreadtrum SDHCI driver. Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/mmc/sdhci-sprd.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sprd.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt new file mode 100644 index 0000000..45c9978 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt @@ -0,0 +1,41 @@ +* Spreadtrum SDHCI controller (sdhci-sprd) + +The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface +for MMC, SD and SDIO types of cards. + +This file documents differences between the core properties in mmc.txt +and the properties used by the sdhci-sprd driver. + +Required properties: +- compatible: Should contain "sprd,sdhci-r11". +- reg: physical base address of the controller and length. +- interrupts: Interrupts used by the SDHCI controller. +- clocks: Should contain phandle for the clock feeding the SDHCI controller +- clock-names: Should contain the following: + "sdio" - SDIO source clock (required) + "enable" - gate clock which used for enabling/disabling the device (required) + +Optional properties: +- assigned-clocks: the same with "sdio" clock +- assigned-clock-parents: the default parent of "sdio" clock + +Examples: + +sdio0: sdio@20600000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20600000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>; + assigned-clocks = <&ap_clk CLK_EMMC_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + status = "okay"; +};