From patchwork Wed Jul 21 08:39:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 483504 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5313AC12002 for ; Wed, 21 Jul 2021 08:58:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3B2316101E for ; Wed, 21 Jul 2021 08:58:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235712AbhGUIQu (ORCPT ); Wed, 21 Jul 2021 04:16:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:50696 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237204AbhGUH77 (ORCPT ); Wed, 21 Jul 2021 03:59:59 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8923B6121F; Wed, 21 Jul 2021 08:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626856759; bh=JQBY01HlySg61KGcooyIwhgyIlhQj6EZr5kggVNvmjA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KHE86lzZy7C8Cy7F6ZjS5aHgZSDeltJdbkZ4cDoQxkLuzGn5ezWfDymILt8PbgyFQ U1pO15GuhQtVraeTkZpX7d6Rv29AUegXWoOKN71pF/gRZfazaTbeWvn5XAYG2dNRYy 73PQzOSdIGHPTQNRBrQuWUTchsQMLvDjDqIfE7r69iLdhvQdhVqnd/va11htsI8DdD YhQBquGm1Ba4ikP5T/z2CbLy/Wkq08q4al+HgJwK445CGR8Nkk5XCvR0QrWqmP93PZ aq++iXSHkq+0Lclwa5xxVYRQYrcJ0W7ImHjNDaNsnL1ofLaceJsigjAZFTCpofahc0 Q4E1VCx7BPdfg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m67l5-0022da-Et; Wed, 21 Jul 2021 10:39:15 +0200 From: Mauro Carvalho Chehab To: Vinod Koul , Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v7 05/10] dt-bindings: PCI: kirin: Fix compatible string Date: Wed, 21 Jul 2021 10:39:07 +0200 Message-Id: <1b145c6be3c8e219a937a81b922b757470d9013d.1626855713.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The pcie-kirin driver doesn't declare a hisilicon,kirin-pcie. Also, remove the useless comment after the description, as other compat will be supported by the same driver in the future. Acked-by: Rob Herring Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/pci/kirin-pcie.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt index 7db30534498f..7adab8999a6a 100644 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt @@ -9,7 +9,7 @@ Additional properties are described here: Required properties - compatible: - "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC + "hisilicon,kirin960-pcie" - reg: Should contain rc_dbi, apb, phy, config registers location and length. - reg-names: Must include the following entries: "dbi": controller configuration registers; @@ -23,7 +23,7 @@ Optional properties: Example based on kirin960: pcie@f4000000 { - compatible = "hisilicon,kirin-pcie"; + compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; reg-names = "dbi","apb","phy", "config"; From patchwork Wed Jul 21 08:39:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 484117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95618C12002 for ; Wed, 21 Jul 2021 08:57:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7EC0D610D2 for ; Wed, 21 Jul 2021 08:57:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237162AbhGUIQL (ORCPT ); Wed, 21 Jul 2021 04:16:11 -0400 Received: from mail.kernel.org ([198.145.29.99]:50210 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237043AbhGUH74 (ORCPT ); Wed, 21 Jul 2021 03:59:56 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7BC6D6120D; Wed, 21 Jul 2021 08:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626856759; bh=eT62F16m4fmnu9+ZtQ5I8OSRvrVJgO8LuBY471amLVk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Br++L+BMZpXlfIiTwaiiu5mB4JjjUqyv6G64sI0V1bbQyS9c+PeZ0m7ZhzDuddfcf w3au81XBOfLEPCPavw40MZC1PdGN922M25MJaMAvcw4w/3WoRxzPh0iVbbN4oAMebN bvwpBsPghVG1CtVYDrwfuNXJdeNwOyMCvQEmEdObHqx07TDW72HWe7vILxB9qrARCm d6P+AS3tsD3qBsyu1mfKn/vihaIU2hB/tQMVLU4htAVv3sVz4tbOP7uSrbnxciigJ6 FUaKlhcQIweW7Aay5dm6UnwsNqO0BMHjNTozFZIFvwCvilYRnKBRBy7BEu4acJrYZx dzQzuwCB6hyKQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m67l5-0022de-GT; Wed, 21 Jul 2021 10:39:15 +0200 From: Mauro Carvalho Chehab To: Vinod Koul , Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Kishon Vijay Abraham I , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v7 06/10] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Date: Wed, 21 Jul 2021 10:39:08 +0200 Message-Id: <946f2426bc542638240980931eae924c57f2ba27.1626855713.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the bindings for HiKey 970 (hi3670) PCIe PHY interface, supported via the pcie-kirin driver. Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Mauro Carvalho Chehab --- .../phy/hisilicon,phy-hi3670-pcie.yaml | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml new file mode 100644 index 000000000000..a5ea13332cac --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin970 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 970. + +properties: + compatible: + const: hisilicon,hi970-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + phy-supply: + description: The PCIe PHY power supply + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe AUX clock + - description: PCIe APB PHY clock + - description: PCIe APB SYS clock + - description: PCIe ACLK clock + + clock-names: + items: + - const: phy_ref + - const: aux + - const: apb_phy + - const: apb_sys + - const: aclk + + reset-gpios: + description: PCI PERST reset GPIOs + maxItems: 4 + + clkreq-gpios: + description: Clock request GPIOs + maxItems: 3 + + hisilicon,eye-diagram-param: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Eye diagram for phy. + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - reset-gpios + - clkreq-gpios + - hisilicon,eye-diagram-param + - phy-supply + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + #phy-cells = <0>; + phy-supply = <&ldo33>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", "aclk"; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + }; + }; From patchwork Wed Jul 21 08:39:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 483267 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp5988830jao; Wed, 21 Jul 2021 01:58:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTsvD+RKj1PKpeSu4KuKtNDu5jY1PccH2LlUtMnvPpOTSCZAOZLpGj7BjfVzsrWMMvP0LY X-Received: by 2002:a5e:d707:: with SMTP id v7mr11335000iom.46.1626857914585; Wed, 21 Jul 2021 01:58:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626857914; cv=none; d=google.com; s=arc-20160816; b=OWAY2v+NIp5Y6adN297JDZ/gpfukITYyP9a1woLc+cjTnzC+4qz77Zq8WVO6gLNKK7 iyGpeQe5ngZY5p9oKOsa2Ce4Zb7dEDakTQZoFJK1c/2R1QYAbHDKAsK6AmLJF1uxkO8j OeDKjpuRsktpnsOmq0xZCJH8X2gNlIRv1L0KvWLrOM8JM4gXtnJ5F8VVVrJZ8ldPoKBT AN1D+sq12CzJwKgwmhC0GxzWXrvUjQKPifp5UOUCe6JpQi01h1DLN5EEINoIkfqDqmHb 2AhovpbKIzgK/ackhKV+3un+74Tc31sdPz/Lujr5GGLe5bzeAQHpXOg2Y35kjag6xzGB 1RQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UDc4GdZdJMpvgCWtdJv7KQj8GnX0PhO4hBOrQhQRhw8=; b=sClajXJeJiOxjOAfAhuLlDVGXMO1GZLUuZAOqA8QGS/mm0hFATvC2xpVRw4mvIPiQo NnxpbHWZXgMSc6oYPgGDeJx4k4wkpUB0k7Xa/c4hOvE9FP4j3VKxccq7Po1uMvenQkc1 OW9ps08SvkZNcaR/oSjcjffJtnOrjpkITODfq5Q4h4VJvGyLVf9TelmRHzLd6PeyGia4 4bfbBoIEWeY67icoFNd/qS4O4jrbkFzEdREaio9kOSg9K0iIcIhVe5OdCBn+DPvIAKBZ ww/6uxa8A44ZniDBt9iLNiro/BNWv1UpV5yCeD95D6CMEI6ih4oiZpmyYL2HpUPbAVYN XS0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=HE1psxCh; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v20si26601868jao.88.2021.07.21.01.58.34; Wed, 21 Jul 2021 01:58:34 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=HE1psxCh; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236338AbhGUIRh (ORCPT + 7 others); Wed, 21 Jul 2021 04:17:37 -0400 Received: from mail.kernel.org ([198.145.29.99]:50692 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237189AbhGUH77 (ORCPT ); Wed, 21 Jul 2021 03:59:59 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7F0FC6120E; Wed, 21 Jul 2021 08:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626856759; bh=qppQeRmcGvRopw+qAp0appWXEfjJqS9op3P1nX7fpKw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HE1psxChELNcYD+pQFaPbsX6HWoNH6MbChbYD/U8PfJyE+1dSjVmIB2gfjpGaqSo2 EsAzC2GgmDL4SZ537gPH7unHcMaq7jBmAGP1li3VRwWHAtXuk79YqmTk0LkPFS2Uid wWpeZSs49ubTuz079OH/WoKZW7XdtiPcuibTarOVk2fiA+PLu2WEMW7JKdXWvKcGXQ 5lJQ8Ygv8kKLFnHWX6uN+LvSt5+w8rEpRlzndY75pd4rc+FvAaH/gSf53EYDsjBhNh 4hniAJxQNitvJbWf2XdB+X8HxsEdXwPAEpx8ByYN34awryL083C48QZFfJV5XDqWt8 aSTk9LoQKEIYg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m67l5-0022dm-LS; Wed, 21 Jul 2021 10:39:15 +0200 From: Mauro Carvalho Chehab To: Vinod Koul , Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Manivannan Sadhasivam , =?utf-8?q?Krzysztof_Wilczy=C5=84s?= =?utf-8?q?ki?= , Binghui Wang , Lorenzo Pieralisi , Rob Herring , Wei Xu , Xiaowei Song , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH v7 08/10] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Date: Wed, 21 Jul 2021 10:39:10 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Manivannan Sadhasivam Add DTS bindings for the HiKey 970 board's PCIe hardware. Co-developed-by: Mauro Carvalho Chehab Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++ .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - drivers/pci/controller/dwc/pcie-kirin.c | 12 ---- 3 files changed, 71 insertions(+), 13 deletions(-) -- 2.31.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 1f228612192c..6dfcfcfeedae 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; @@ -660,6 +666,71 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + its_pcie: interrupt-controller@f4000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + + phy-supply = <&ldo33>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", + "aclk"; + + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, + <&gpio17 0 0 >; + + /* vboost iboost pre post main */ + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF>; + + #phy-cells = <0>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi index 48c739eacba0..03452e627641 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi @@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */ regulator-name = "ldo33"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; }; ldo34: LDO34 { /* GPS AUX IN VDD */ diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index bfc0513f7b15..9dad14929538 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -347,18 +347,6 @@ static const struct regmap_config pcie_kirin_regmap_conf = { .reg_stride = 4, }; -/* Registers in PCIeCTRL */ -static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie, - u32 val, u32 reg) -{ - writel(val, kirin_pcie->apb_base + reg); -} - -static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg) -{ - return readl(kirin_pcie->apb_base + reg); -} - static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { From patchwork Wed Jul 21 08:39:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 483503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD28DC12002 for ; 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Wed, 21 Jul 2021 10:39:15 +0200 From: Mauro Carvalho Chehab To: Vinod Koul , Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Binghui Wang , Gustavo Pimentel , Jingoo Han , Rob Herring , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v7 09/10] dt-bindings: PCI: kirin-pcie.txt: Convert it to yaml Date: Wed, 21 Jul 2021 10:39:11 +0200 Message-Id: <656b8ffe505081b003650f040de4d52131d70b8f.1626855713.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the file into a JSON description at the yaml format. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 87 +++++++++++++++++++ .../devicetree/bindings/pci/kirin-pcie.txt | 50 ----------- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +- MAINTAINERS | 2 +- 4 files changed, 89 insertions(+), 52 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file mode 100644 index 000000000000..eabc651c9766 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin SoCs PCIe host DT description + +maintainers: + - Xiaowei Song + - Binghui Wang + +description: | + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. + It shares common functions with the PCIe DesignWare core driver and + inherits common properties defined in + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + contains: + enum: + - hisilicon,kirin960-pcie + - hisilicon,kirin970-pcie + + reg: + description: | + Should contain rc_dbi, apb, config registers location and length. + minItems: 3 + maxItems: 4 + + reg-names: + items: + - const: dbi # controller configuration registers + - const: apb # apb Ctrl register defined by Kirin + - const: config # PCIe configuration space registers + - const: phy # apb PHY register used on Kirin 960 PHY + minItems: 3 + maxItems: 4 + + reset-gpios: + description: The GPIO(s) to generate PCIe PERST# assert and deassert signal. + minItems: 1 + maxItems: 4 + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf4000000 0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt deleted file mode 100644 index 7adab8999a6a..000000000000 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ /dev/null @@ -1,50 +0,0 @@ -HiSilicon Kirin SoCs PCIe host DT description - -Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. -It shares common functions with the PCIe DesignWare core driver and -inherits common properties defined in -Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. - -Additional properties are described here: - -Required properties -- compatible: - "hisilicon,kirin960-pcie" -- reg: Should contain rc_dbi, apb, phy, config registers location and length. -- reg-names: Must include the following entries: - "dbi": controller configuration registers; - "apb": apb Ctrl register defined by Kirin; - "phy": apb PHY register defined by Kirin; - "config": PCIe configuration space registers. -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. - -Optional properties: - -Example based on kirin960: - - pcie@f4000000 { - compatible = "hisilicon,kirin960-pcie"; - reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; - reg-names = "dbi","apb","phy", "config"; - bus-range = <0x0 0x1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; - num-lanes = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, - <0x0 0 0 2 &gic 0 0 0 283 4>, - <0x0 0 0 3 &gic 0 0 0 284 4>, - <0x0 0 0 4 &gic 0 0 0 285 4>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; - }; diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index a8c1db879fb9..d80894a5abf5 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -34,7 +34,7 @@ properties: minItems: 2 maxItems: 5 items: - enum: [dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link] + enum: [dbi, dbi2, config, atu, apb, app, elbi, mgmt, ctrl, parf, cfg, link] num-lanes: description: | diff --git a/MAINTAINERS b/MAINTAINERS index b54bd9dd07ec..d5f53b2d3f9c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14420,7 +14420,7 @@ M: Xiaowei Song M: Binghui Wang L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/kirin-pcie.txt +F: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml F: drivers/pci/controller/dwc/pcie-kirin.c PCIE DRIVER FOR HISILICON STB From patchwork Wed Jul 21 08:39:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 484116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-25.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72DF9C12002 for ; Wed, 21 Jul 2021 08:58:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5D5736101E for ; Wed, 21 Jul 2021 08:58:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236283AbhGUIRK (ORCPT ); Wed, 21 Jul 2021 04:17:10 -0400 Received: from mail.kernel.org ([198.145.29.99]:50686 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237199AbhGUH77 (ORCPT ); Wed, 21 Jul 2021 03:59:59 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 73441611C1; Wed, 21 Jul 2021 08:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626856759; bh=UiGm31iNvtZ99MxpzCURtzkORD4wRkDpyBs+z354Skc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UtxQCWdBRZWDky07nm1s0kA3QWg+5PTN9Vz4d5pLJr49ovk8Vo5aGmd5khMIpyIvU PySZgKlEja2/mUSUBfdnJ39BoepAkiTcC52s660cFip94zJNELiSze44jbP/VGQgzC qYqgggffENGpn3sWUxNhDo6i7jqjEeLEO06JMEdpYsrjPuJZ0h41Bt7CWOLLYPCv3r FBYZ8sVSu4GW5SdSSZ+7HvTnDCfNKHECECTKgYXIYYEMu33DGQMgoPb66pyXKuArce P5UoxTRVtg+r0gwk2WhMjdkxf5KK6xO6CWrAoUs1hhUtXwz+cE981RBWZTcABNHgYL CbqyDSG3IhqvA== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m67l5-0022dv-Om; Wed, 21 Jul 2021 10:39:15 +0200 From: Mauro Carvalho Chehab To: Vinod Koul , Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Kishon Vijay Abraham I , Manivannan Sadhasivam , Rob Herring , Wei Xu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v7 10/10] phy-hi3670-pcie: Move reset-gpios to the PCIe DT schema Date: Wed, 21 Jul 2021 10:39:12 +0200 Message-Id: <25f0d338b301157d4b0fe8ab97db542635dff562.1626855713.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PHY interface as found on HiKey 970 uses 4 reset-gpios instead of just one. That seems to be due to electrical requirements, as, on HiKey 970, the PERST# signal is provided via one GPIO per connected/available PCIe device: - GPIO 56 has a pullup logic from 1V8 to 2V5 connected to a PCIe bridge chip (PEX 8606); - GPIO 25 has a pullup logic from 1V8 to 3V3 connected to the PERST# pin at the M.2 slot; - GPIO 220 has a pullup logic from 1V8 to 3V3 connected to the PERST# pin at the PCIe mini slot; - GPIO 203 has a pullup logic from 1V8 to 3V3 connected to the PERST# pin at the Ethernet chipset. Originally, this was mapped via the PHY interface, but, as such design may also be used with different hardware, remap this to use the pcie-bus DT schema. This patch depends on a DT schema patch submitted at: https://github.com/devicetree-org/dt-schema/pull/56 Signed-off-by: Mauro Carvalho Chehab --- .../phy/hisilicon,phy-hi3670-pcie.yaml | 7 --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 5 +- drivers/phy/hisilicon/phy-hi3670-pcie.c | 54 ++++++++++--------- 3 files changed, 31 insertions(+), 35 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml index a5ea13332cac..86767c53bc91 100644 --- a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml @@ -42,10 +42,6 @@ properties: - const: apb_sys - const: aclk - reset-gpios: - description: PCI PERST reset GPIOs - maxItems: 4 - clkreq-gpios: description: Clock request GPIOs maxItems: 3 @@ -60,7 +56,6 @@ required: - reg - clocks - clock-names - - reset-gpios - clkreq-gpios - hisilicon,eye-diagram-param - phy-supply @@ -86,8 +81,6 @@ examples: <&crg_ctrl HI3670_ACLK_GATE_PCIE>; clock-names = "phy_ref", "aux", "apb_phy", "apb_sys", "aclk"; - reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, - <&gpio3 1 0 >, <&gpio27 4 0 >; clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 6dfcfcfeedae..a07790c76b72 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -687,9 +687,6 @@ pcie_phy: pcie-phy@fc000000 { "apb_phy", "apb_sys", "aclk"; - reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, - <&gpio3 1 0 >, <&gpio27 4 0 >; - clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; @@ -729,6 +726,8 @@ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; }; /* UFS */ diff --git a/drivers/phy/hisilicon/phy-hi3670-pcie.c b/drivers/phy/hisilicon/phy-hi3670-pcie.c index 0bc0203e9140..82cc5fc4eac2 100644 --- a/drivers/phy/hisilicon/phy-hi3670-pcie.c +++ b/drivers/phy/hisilicon/phy-hi3670-pcie.c @@ -553,11 +553,13 @@ static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable) return 0; } -static int hi3670_pcie_get_apb(struct hi3670_pcie_phy *phy) +static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy) { struct device_node *pcie_port; struct device *dev = phy->dev; struct device *pcie_dev; + char name[32]; + int i; pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie"); if (!pcie_port) { @@ -586,6 +588,27 @@ static int hi3670_pcie_get_apb(struct hi3670_pcie_phy *phy) return -ENODEV; } + /* perst reset gpios */ + phy->n_gpio_resets = of_gpio_named_count(pcie_dev->of_node, + "reset-gpios"); + if (phy->n_gpio_resets > MAX_GPIO_RESETS) { + dev_err(dev, "Too many GPIO resets!\n"); + return -EINVAL; + } + for (i = 0; i < phy->n_gpio_resets; i++) { + phy->gpio_id_reset[i] = of_get_named_gpio(pcie_dev->of_node, + "reset-gpios", i); + if (phy->gpio_id_reset[i] < 0) + return phy->gpio_id_reset[i]; + + sprintf(name, "pcie_perst_%d", i); + + phy->reset_names[i] = devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!phy->reset_names[i]) + return -ENOMEM; + } + return 0; } @@ -644,16 +667,17 @@ static int hi3670_pcie_phy_init(struct phy *generic_phy) int ret; /* - * The code under hi3670_pcie_get_apb() need to access the - * DWC APB registers. So, get them from - * the pcie driver's regmap (see pcie-kirin regmap). + * The code under hi3670_pcie_get_resources_from_pcie() need to + * access the reset-gpios and the APB registers, both from the + * pcie-kirin driver. * + * The APB is obtained via the pcie driver's regmap * Such kind of resource can only be obtained during the PCIe * power_on sequence, as the code inside pcie-kirin needs to * be already probed, as it needs to register the APB regmap. */ - ret = hi3670_pcie_get_apb(phy); + ret = hi3670_pcie_get_resources_from_pcie(phy); if (ret) return ret; @@ -800,26 +824,6 @@ static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy, if (IS_ERR(phy->base)) return PTR_ERR(phy->base); - /* perst reset gpios */ - phy->n_gpio_resets = of_gpio_named_count(np, "reset-gpios"); - if (phy->n_gpio_resets > MAX_GPIO_RESETS) { - dev_err(dev, "Too many GPIO resets!\n"); - return -EINVAL; - } - for (i = 0; i < phy->n_gpio_resets; i++) { - phy->gpio_id_reset[i] = of_get_named_gpio(dev->of_node, - "reset-gpios", i); - if (phy->gpio_id_reset[i] < 0) - return phy->gpio_id_reset[i]; - - sprintf(name, "pcie_perst_%d", i); - - phy->reset_names[i] = devm_kstrdup_const(dev, name, - GFP_KERNEL); - if (!phy->reset_names[i]) - return -ENOMEM; - } - /* clock request gpios */ phy->n_gpio_clkreq = of_gpio_named_count(np, "clkreq-gpios"); if (phy->n_gpio_clkreq > MAX_GPIO_CLKREQ) {