From patchwork Thu May 18 09:47:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 100072 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp634418qge; Thu, 18 May 2017 02:47:49 -0700 (PDT) X-Received: by 10.84.198.36 with SMTP id o33mr3803259pld.145.1495100868408; Thu, 18 May 2017 02:47:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495100868; cv=none; d=google.com; s=arc-20160816; b=qioHQttOK4vNi2FbOwdkqoXfY3Hor1IT4GcQ9afKA+4NtQ+v8wTcGv7XsmoW9k3pou 6uKsykM8jSR6Rjlc+Krx2y1+Yu6680/v6w6alm3EK3XHv+V89EvznR6FIZxPDR4XQ+hx BypmB18LrVtyPXY5JGIvUtzTuAe7tXZDHh/xEBSJ+qJ9DgGZLf1ORPVlNGDWm1e5StoG qAgwnkjDGIsvAF0K5cvPzR3xy5kIHTzTiJ1QnxgMBkgy08xGkmvx8WsQ5roB8urmPoOt wj0kGhrsCdmMmkpTohaKWck6eBzo6yqgHfzNi306L9ta3ccv/R4yUkCLO60v0hPE7/WF cwLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=xUJ0KNro7ANYTRNK6edAP2Tl+YVEY0vvxwAQ8eceEdo=; b=GQ5Budvkk7wm4TwtD/kJ846YDKrUtNP4am0U5XJTS69DvwauntG2s2vHlmJhLQCsJ5 vjgi25EzNBmhP2XIrDjsDVeKBj44m7sizmMqoJ9hK0MvO5I2H6NpqSPUX7GB/NL3cvcg KE80wXqZ+b5Ftlgqhp21XZw2RYTqAZM6iY+lwwQNMTKX+1I6GS5KkDiXPM0P7sfSJg1F h3ujuoCPPQaN3LUppExbL17lHfVFwKBpoTUALtAettdH4ndT13mZyLOvokMBVb04kfYn MCqwDcIleZ0JDD2iZ6qNAlx9hhBZSPLMg9ml5C5ccrovAjEytYjW7h8KKbK9ZDcGLtKv ocrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id w15sm2377437edw.27.2017.05.18.02.47.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 02:47:38 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Christoffer Dall Subject: [PULL 02/13] arm64: KVM: Do not use stack-protector to compile EL2 code Date: Thu, 18 May 2017 11:47:11 +0200 Message-Id: <20170518094722.9926-3-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170518094722.9926-1-cdall@linaro.org> References: <20170518094722.9926-1-cdall@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier We like living dangerously. Nothing explicitely forbids stack-protector to be used in the EL2 code, while distributions routinely compile their kernel with it. We're just lucky that no code actually triggers the instrumentation. Let's not try our luck for much longer, and disable stack-protector for code living at EL2. Cc: stable@vger.kernel.org Signed-off-by: Marc Zyngier Acked-by: Christoffer Dall Signed-off-by: Christoffer Dall --- arch/arm64/kvm/hyp/Makefile | 2 ++ 1 file changed, 2 insertions(+) -- 2.9.0 diff --git a/arch/arm64/kvm/hyp/Makefile b/arch/arm64/kvm/hyp/Makefile index aaf42ae..14c4e3b 100644 --- a/arch/arm64/kvm/hyp/Makefile +++ b/arch/arm64/kvm/hyp/Makefile @@ -2,6 +2,8 @@ # Makefile for Kernel-based Virtual Machine module, HYP part # +ccflags-y += -fno-stack-protector + KVM=../../../../virt/kvm obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v2-sr.o From patchwork Thu May 18 09:47:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 100075 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp634459qge; Thu, 18 May 2017 02:47:56 -0700 (PDT) X-Received: by 10.84.178.129 with SMTP id z1mr3831923plb.44.1495100876142; Thu, 18 May 2017 02:47:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495100876; cv=none; d=google.com; s=arc-20160816; b=QUBl5/vG/y/VIy480/4Z/YwyCllSEPJJet513/tfhXMX9I9QjcD1ZOdXER06E+aQI6 Y6JWKRHYTTNnmTjB/ohNd003NsaMrw/JyJXBn5AxQ3FNsUGzF7eTlPhEA/5DG3a/B7gS TgkKwqiE0uvAXzj+u7qqtTPMLARx7lAFuOhtHCghY49+xafzGpQoc5wQ6Kxum0wewBbJ Fl1CoAbubo0jbk0SnTq66BkWkYe1y+TQtjTjeDbIVugma69LgM6H7vC7ahVAzgJNISW6 k5hTkpQ/nrp1qk642GtTbncvfOOprWccCHm3ZSSEbvpxJJB5LQof5fkkilnFPkrdsGER ghkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=UiF4naM2eba60FJdhmDeH4sufkyHSYyWZZOKHuNV2uI=; b=cxvFDwProBD/l2dYGr/U1HIG5wy5SUwaabUliCgW4YkNrOuXcMVMNu7Y5w0Mnk/O8Z mCudQZYkuNDaROjwjpxa1H3yKZBMp7XNvmJPHK/yWfcXtSbEyFcqvjpDfqPHCLw+da8G SoDUa9GnLQTf3mWewtDZrpmkYJwzxmELKBK7XIs+Z1FMA0V2BLE0VRYS7hYBUZdUWAP3 vd8vCSXx7qzAH0YxU0D+3CmLygDN0NnyP1/5WxkwevYcCymdA8juBbeWzFWAIDCvWDD5 R1ms87Ch7x37xMh5i2nFWcSohcH8+CXbv0Q0hVTv0N2YieziOrd0Kq00xfLCtY/eJki+ f7hQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id w15sm2377437edw.27.2017.05.18.02.47.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 02:47:39 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Christoffer Dall Subject: [PULL 03/13] arm: KVM: Do not use stack-protector to compile HYP code Date: Thu, 18 May 2017 11:47:12 +0200 Message-Id: <20170518094722.9926-4-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170518094722.9926-1-cdall@linaro.org> References: <20170518094722.9926-1-cdall@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier We like living dangerously. Nothing explicitely forbids stack-protector to be used in the HYP code, while distributions routinely compile their kernel with it. We're just lucky that no code actually triggers the instrumentation. Let's not try our luck for much longer, and disable stack-protector for code living at HYP. Cc: stable@vger.kernel.org Signed-off-by: Marc Zyngier Acked-by: Christoffer Dall Signed-off-by: Christoffer Dall --- arch/arm/kvm/hyp/Makefile | 2 ++ 1 file changed, 2 insertions(+) -- 2.9.0 diff --git a/arch/arm/kvm/hyp/Makefile b/arch/arm/kvm/hyp/Makefile index 3023bb5..8679405 100644 --- a/arch/arm/kvm/hyp/Makefile +++ b/arch/arm/kvm/hyp/Makefile @@ -2,6 +2,8 @@ # Makefile for Kernel-based Virtual Machine module, HYP part # +ccflags-y += -fno-stack-protector + KVM=../../../../virt/kvm obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v2-sr.o From patchwork Thu May 18 09:47:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 100074 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp634442qge; Thu, 18 May 2017 02:47:52 -0700 (PDT) X-Received: by 10.99.173.12 with SMTP id g12mr3364650pgf.225.1495100872710; Thu, 18 May 2017 02:47:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495100872; cv=none; d=google.com; s=arc-20160816; b=imXmHgp5G9We+hjYbgNtQDve6gLqCaGtqI+xlor9JYg9C/WYjBdoj98dUWIoalUHCK RW4KHIml6FWNxe+gVqaZsEcGKpPYZXJ5yEw6hLtSh7X5xRU8Wn1diiA4CJntRj4uFMGA 6jp+H0R65VkMP0+4MqVlEYxpKmHiovf/YJevs9FXe2lPXlkbLhCM6K5R63Q7nNNNRteX GmAwkZ5NS9I5UamO4hQbm61AGnFnuEXIo5Y7RY/oM5K4OIaUAo4/E0Z5Lb2EI1Mek0oM UWgd6gQb4MfBxg1dz+6pKcQOY0K7kpq0cGb7WRql3WkvXkqj7TRcX03aiijKt5P/kdUG GyRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=+l2eDeYQRBSHmiv6JZQRzqPo5IYD0EKoP4jYyMv0IGw=; b=SibJC2aDcAAG3bQmXIYoVI+5p75UPgu6AP956fJVeWB29eT+g+f/fpOhzs6m2AywTR ne9FcvUQ6P7jTh3eyam/Hq3c7h90M7DJkMrhIuEee5w7JlA9mtNscSsNHSGKvovvufnk Slwk/y1DZEdQpDPX7Wd0cnZMSOXL7E5B+C+ouQSP8hK5sppqJV+MQL8Pk3MPKsnMkhsV LMp8lIW/vpiR8rPj30XlAiKcxVbJl2wV7IMtFaHFhPspK88snkYUNhKVmCPTQiZgTKMn uDUlcRczf/2Q75np16hvPL+kjJxWbWGU4wjZZq/CwbRda3cdn1saXbVNA4KJ+5i+YEO2 AdtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id w15sm2377437edw.27.2017.05.18.02.47.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 02:47:40 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Christoffer Dall Subject: [PULL 04/13] KVM: arm/arm64: vgic-v2: Do not use Active+Pending state for a HW interrupt Date: Thu, 18 May 2017 11:47:13 +0200 Message-Id: <20170518094722.9926-5-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170518094722.9926-1-cdall@linaro.org> References: <20170518094722.9926-1-cdall@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier When an interrupt is injected with the HW bit set (indicating that deactivation should be propagated to the physical distributor), special care must be taken so that we never mark the corresponding LR with the Active+Pending state (as the pending state is kept in the physycal distributor). Cc: stable@vger.kernel.org Fixes: 140b086dd197 ("KVM: arm/arm64: vgic-new: Add GICv2 world switch backend") Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic/vgic-v2.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.9.0 diff --git a/virt/kvm/arm/vgic/vgic-v2.c b/virt/kvm/arm/vgic/vgic-v2.c index a65757a..504b4bd 100644 --- a/virt/kvm/arm/vgic/vgic-v2.c +++ b/virt/kvm/arm/vgic/vgic-v2.c @@ -149,6 +149,13 @@ void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) if (irq->hw) { val |= GICH_LR_HW; val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT; + /* + * Never set pending+active on a HW interrupt, as the + * pending state is kept at the physical distributor + * level. + */ + if (irq->active && irq_is_pending(irq)) + val &= ~GICH_LR_PENDING_BIT; } else { if (irq->config == VGIC_CONFIG_LEVEL) val |= GICH_LR_EOI; From patchwork Thu May 18 09:47:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 100073 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp634425qge; Thu, 18 May 2017 02:47:50 -0700 (PDT) X-Received: by 10.99.96.70 with SMTP id u67mr3565233pgb.101.1495100870497; Thu, 18 May 2017 02:47:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495100870; cv=none; d=google.com; s=arc-20160816; b=k4X0EgUW4wNXH4oTj0H9ZSP+1zpMLT0SaxPkiwNId9OpNPJuIkJ12WO5r3Y2hgc3K4 9gBIwWfqtGO1V4VA/T4EDTYCE0Uli6NgamWt2AprkqVF8EsnIofqb+R3XeskUBQotgyL Hrcl+yzrseKNVRcRCUPrGIPqdBWLhvNtHJIZwaDo6oOJoNoVt6V8Gu5wRMJI1YpDqWnS SuyhvnTh24DauGiPVsd+pWAcgPyUddJj/BdHgEca+FSDjxOOEfiJvPr81lpMTb4lSLH3 Mk0XASdEGutS1Wda19WRwbsn6g/bIF3AZ+2CY1y8tIe4BR8r3LPBr2sVUAroJPJO3Dby u2ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=LcR5X+/y65yXGW3Z3jUfDsouRSLk6Wp0VA+ixUPV3zY=; b=OPDUVcoJ81l03EEINoAV0DArGzGtcB9yq6zceDlNpY6AlMwZPiVP7P5TS9S5BxeEIm Ba+d7A6Q/L0RYx8FcySSrLy23grLgnyL5jUkViIaPgslRzdRvC6jrn+5zNaZamBq2vN5 2rq9YB58W8QGl8nzI2fImpYQopdVBgLCcacRwqXKKB0xatbr7Pkmy1NzKkKyM51xrNXA 7dfNWU7AISCsfg6E78QpJt3WoQcg3KvQUp/aLt2Xbod6QXbne6vM7amMUpFe2s+q2/IC IBFX251CWtKHsqIbzD0e06vL3w9L1ayFLm9Rjc87OClK2vhmy9cfGA1XFcDcWzv+wYTT dkHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id w15sm2377437edw.27.2017.05.18.02.47.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 02:47:41 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Christoffer Dall Subject: [PULL 05/13] KVM: arm/arm64: vgic-v3: Do not use Active+Pending state for a HW interrupt Date: Thu, 18 May 2017 11:47:14 +0200 Message-Id: <20170518094722.9926-6-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170518094722.9926-1-cdall@linaro.org> References: <20170518094722.9926-1-cdall@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier When an interrupt is injected with the HW bit set (indicating that deactivation should be propagated to the physical distributor), special care must be taken so that we never mark the corresponding LR with the Active+Pending state (as the pending state is kept in the physycal distributor). Cc: stable@vger.kernel.org Fixes: 59529f69f504 ("KVM: arm/arm64: vgic-new: Add GICv3 world switch backend") Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic/vgic-v3.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.9.0 diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c index 8fa737e..6fe3f00 100644 --- a/virt/kvm/arm/vgic/vgic-v3.c +++ b/virt/kvm/arm/vgic/vgic-v3.c @@ -127,6 +127,13 @@ void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) if (irq->hw) { val |= ICH_LR_HW; val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT; + /* + * Never set pending+active on a HW interrupt, as the + * pending state is kept at the physical distributor + * level. + */ + if (irq->active && irq_is_pending(irq)) + val &= ~ICH_LR_PENDING_BIT; } else { if (irq->config == VGIC_CONFIG_LEVEL) val |= ICH_LR_EOI; From patchwork Thu May 18 09:47:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 100078 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp634578qge; Thu, 18 May 2017 02:48:19 -0700 (PDT) X-Received: by 10.84.224.10 with SMTP id r10mr3795442plj.25.1495100899062; Thu, 18 May 2017 02:48:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495100899; cv=none; d=google.com; s=arc-20160816; b=c5UZQat6mo1PGdbb0CIS8Z9fkSmJGu7POOUu2o2keJnZr6fy8wL15/sTp1HS0jVHDi HZVTJRiE7NLrVwWdVxq3cfjU4kx0UPaFLgtU6q62qhuchtwGHOWkFHrx2FgonT+GONgd 3bd6iogsAXLuLVNUhRtoqTSp+Nn2VwbnqxTUn5U2LCNjKZQtRw2m4Dn/Tkel/WoV2g+e tAw8L7mHaOGS4bVrdIoOZRMQQueoiUuOHTqTqUNmbX3AfsS2fjh0IpkmLTD6fSyPLL3w aJPQ8Wy9aupu27qjIaQIKf01U9pINnoYOl+9mX1BIsD9my9ypo+avtLtbU+Om2ahv1Dq ZzbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=K1WEH2iJnVWBs0DbSdUNh8yprlxphjcvnxLybUjCgU4=; b=ElT0/DB6ycq3uAEnnECdJCsQpQtXwRSze4Yj8sqewP5abAtmroHChCzahGjRrXbDys /nlZYfYOQ8akMW1NyLZZ3oCP8RyFJ9HO+2ouOcFpVpeTEZw9oMrE2cATd0VUHh1LOVwA j+8q73K1J9+6eHHB17gN85D3Vg0YNzrIlpw0KFIHsR7W9JFiHBAYKzgghyQDIN+2M4h5 tiT6KBs+KyNgjW4A9bwYZWuUFxxCoqhxS81wyBtyRT/Kz1OJ0dXgUucX1n4Vc3gUZLwv 8V8f70GoRftyR3D7ku+nI5EVSgQ0WeMvT6OXy0YZr4yE5gm6fVyrdMSfgvxS04ixsoeK 3Urg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id w15sm2377437edw.27.2017.05.18.02.47.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 02:47:44 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Zhichao Huang , stable@vger.kernel.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Christoffer Dall Subject: [PULL 08/13] KVM: arm: plug potential guest hardware debug leakage Date: Thu, 18 May 2017 11:47:17 +0200 Message-Id: <20170518094722.9926-9-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170518094722.9926-1-cdall@linaro.org> References: <20170518094722.9926-1-cdall@linaro.org> MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Zhichao Huang Hardware debugging in guests is not intercepted currently, it means that a malicious guest can bring down the entire machine by writing to the debug registers. This patch enable trapping of all debug registers, preventing the guests to access the debug registers. This includes access to the debug mode(DBGDSCR) in the guest world all the time which could otherwise mess with the host state. Reads return 0 and writes are ignored (RAZ_WI). The result is the guest cannot detect any working hardware based debug support. As debug exceptions are still routed to the guest normal debug using software based breakpoints still works. To support debugging using hardware registers we need to implement a debug register aware world switch as well as special trapping for registers that may affect the host state. Cc: stable@vger.kernel.org Signed-off-by: Zhichao Huang Signed-off-by: Alex Bennée Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall --- arch/arm/include/asm/kvm_coproc.h | 3 +- arch/arm/kvm/coproc.c | 77 ++++++++++++++++++++++++++++++--------- arch/arm/kvm/handle_exit.c | 4 +- arch/arm/kvm/hyp/switch.c | 4 +- 4 files changed, 66 insertions(+), 22 deletions(-) -- 2.9.0 diff --git a/arch/arm/include/asm/kvm_coproc.h b/arch/arm/include/asm/kvm_coproc.h index 4917c2f..e74ab0f 100644 --- a/arch/arm/include/asm/kvm_coproc.h +++ b/arch/arm/include/asm/kvm_coproc.h @@ -31,7 +31,8 @@ void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table); int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run); -int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run); +int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run); +int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run); diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c index ac8d36d..1403ffb 100644 --- a/arch/arm/kvm/coproc.c +++ b/arch/arm/kvm/coproc.c @@ -112,12 +112,6 @@ int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run) return 1; } -int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run) -{ - kvm_inject_undefined(vcpu); - return 1; -} - static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) { /* @@ -533,12 +527,7 @@ static int emulate_cp15(struct kvm_vcpu *vcpu, return 1; } -/** - * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access - * @vcpu: The VCPU pointer - * @run: The kvm_run struct - */ -int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run) +static struct coproc_params decode_64bit_hsr(struct kvm_vcpu *vcpu) { struct coproc_params params; @@ -552,9 +541,38 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run) params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf; params.CRm = 0; + return params; +} + +/** + * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access + * @vcpu: The VCPU pointer + * @run: The kvm_run struct + */ +int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + struct coproc_params params = decode_64bit_hsr(vcpu); + return emulate_cp15(vcpu, ¶ms); } +/** + * kvm_handle_cp14_64 -- handles a mrrc/mcrr trap on a guest CP14 access + * @vcpu: The VCPU pointer + * @run: The kvm_run struct + */ +int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + struct coproc_params params = decode_64bit_hsr(vcpu); + + /* raz_wi cp14 */ + pm_fake(vcpu, ¶ms, NULL); + + /* handled */ + kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); + return 1; +} + static void reset_coproc_regs(struct kvm_vcpu *vcpu, const struct coproc_reg *table, size_t num) { @@ -565,12 +583,7 @@ static void reset_coproc_regs(struct kvm_vcpu *vcpu, table[i].reset(vcpu, &table[i]); } -/** - * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access - * @vcpu: The VCPU pointer - * @run: The kvm_run struct - */ -int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run) +static struct coproc_params decode_32bit_hsr(struct kvm_vcpu *vcpu) { struct coproc_params params; @@ -584,9 +597,37 @@ int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run) params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7; params.Rt2 = 0; + return params; +} + +/** + * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access + * @vcpu: The VCPU pointer + * @run: The kvm_run struct + */ +int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + struct coproc_params params = decode_32bit_hsr(vcpu); return emulate_cp15(vcpu, ¶ms); } +/** + * kvm_handle_cp14_32 -- handles a mrc/mcr trap on a guest CP14 access + * @vcpu: The VCPU pointer + * @run: The kvm_run struct + */ +int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + struct coproc_params params = decode_32bit_hsr(vcpu); + + /* raz_wi cp14 */ + pm_fake(vcpu, ¶ms, NULL); + + /* handled */ + kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); + return 1; +} + /****************************************************************************** * Userspace API *****************************************************************************/ diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c index 5fd7968..f86a9aa 100644 --- a/arch/arm/kvm/handle_exit.c +++ b/arch/arm/kvm/handle_exit.c @@ -95,9 +95,9 @@ static exit_handle_fn arm_exit_handlers[] = { [HSR_EC_WFI] = kvm_handle_wfx, [HSR_EC_CP15_32] = kvm_handle_cp15_32, [HSR_EC_CP15_64] = kvm_handle_cp15_64, - [HSR_EC_CP14_MR] = kvm_handle_cp14_access, + [HSR_EC_CP14_MR] = kvm_handle_cp14_32, [HSR_EC_CP14_LS] = kvm_handle_cp14_load_store, - [HSR_EC_CP14_64] = kvm_handle_cp14_access, + [HSR_EC_CP14_64] = kvm_handle_cp14_64, [HSR_EC_CP_0_13] = kvm_handle_cp_0_13_access, [HSR_EC_CP10_ID] = kvm_handle_cp10_id, [HSR_EC_HVC] = handle_hvc, diff --git a/arch/arm/kvm/hyp/switch.c b/arch/arm/kvm/hyp/switch.c index 92678b7..624a510 100644 --- a/arch/arm/kvm/hyp/switch.c +++ b/arch/arm/kvm/hyp/switch.c @@ -48,7 +48,9 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu, u32 *fpexc_host) write_sysreg(HSTR_T(15), HSTR); write_sysreg(HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11), HCPTR); val = read_sysreg(HDCR); - write_sysreg(val | HDCR_TPM | HDCR_TPMCR, HDCR); + val |= HDCR_TPM | HDCR_TPMCR; /* trap performance monitors */ + val |= HDCR_TDRA | HDCR_TDOSA | HDCR_TDA; /* trap debug regs */ + write_sysreg(val, HDCR); } static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu) From patchwork Thu May 18 09:47:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 100077 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp634564qge; Thu, 18 May 2017 02:48:17 -0700 (PDT) X-Received: by 10.84.178.101 with SMTP id y92mr3766112plb.116.1495100896931; Thu, 18 May 2017 02:48:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495100896; cv=none; d=google.com; s=arc-20160816; b=MI/pbO2+hWLq6oAMUiW429ajkCBjF+721Mz+kaRZtavM1VuGJBekaXbO4D9QXAQHBm gJcZr0a67Zxf5o1mZmiaMPTKXoxeBXVMfySYMnxHxJ/1KMQtkwKfPd+RqwL4sPmFlavk zZQDEUi6EZxMdrZoIhoZkN60hTZNZYSF8SbeKi/eyJB+B5vN7ZMCrAKFnxpZDasHad6t mMJuJ4EXYtv3IkPJcSAjLx87TcEryOfF2qXvipHSEgvQRJ2gSiCcv4do+BHTZvKwgrp5 0csaDP79opY1LjNCyWN071fDjzNwfvwiMvuJiuAc7wIdhwWVjpiPE7ORyDOrgcpge8AJ l9wg== ARC-Message-Signature: i=1; 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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id w15sm2377437edw.27.2017.05.18.02.47.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 02:47:46 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Suzuki K Poulose , stable@vger.kernel.org, Christoffer Dall Subject: [PULL 10/13] kvm: arm/arm64: Force reading uncached stage2 PGD Date: Thu, 18 May 2017 11:47:19 +0200 Message-Id: <20170518094722.9926-11-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170518094722.9926-1-cdall@linaro.org> References: <20170518094722.9926-1-cdall@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Suzuki K Poulose Make sure we don't use a cached value of the KVM stage2 PGD while resetting the PGD. Cc: Marc Zyngier Cc: stable@vger.kernel.org Signed-off-by: Suzuki K Poulose Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall --- virt/kvm/arm/mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.9.0 diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index 909a1a7..704e35f 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -837,7 +837,7 @@ void kvm_free_stage2_pgd(struct kvm *kvm) spin_lock(&kvm->mmu_lock); if (kvm->arch.pgd) { unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE); - pgd = kvm->arch.pgd; + pgd = READ_ONCE(kvm->arch.pgd); kvm->arch.pgd = NULL; } spin_unlock(&kvm->mmu_lock); From patchwork Thu May 18 09:47:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 100076 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp634538qge; Thu, 18 May 2017 02:48:12 -0700 (PDT) X-Received: by 10.99.126.20 with SMTP id z20mr3409792pgc.158.1495100892657; Thu, 18 May 2017 02:48:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495100892; cv=none; d=google.com; s=arc-20160816; b=ySBf2J/wWz+7mwmZtRNKv+Cd5/Fqevqh+tL2EdzQZVU+eHRu7JAYTb+9++22LlXmK8 rFqd9qkgbuV6psBsNl6uCaehMrfIwlzqRMxiu3V4tf/i/qfG/59pLFX49jF9D0VE3dY+ eJmvTVL1iBJ5Jmql5oTupBWBzKvjikzxtDwOc16ZAzGMDBdSFiQoVWro0LSQl8eJddDi fbY2HCpwtK9czdzXUa9jCXHiKgNEi7tSSLMZbuus7lEYHNTIjE/tcjRWXSoXjp9BLlxE LPohNnHAxBM6GcTMiRXtDybTbAImXkSsh5H4yxmljsUoxhoL1HyK4hunHfuVJo9nADzU 5ndw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=UJ4ttGo1yIqZOj1ZDuN3LmBaUNvY9FDwdN8JzwZ8ZaM=; b=g2XLAR3VEeHi9KoiCE7/uZ5fW8IkJKtDP1XRN+2+P8HFLkFDX2Cvg125yDwMKZHouZ u4e54ton1P+TPGTHhBuZtTupIuO/aSWPG1ea6hmw4nvbzx7LhXSrZwTkBE957Apv4UXy 9/xdUhjJmdwF7nP2MnG9TqGe1ZIKFbMEqOyZ8XcjpLo6yX2gWn0UeGzY+i80gV0TutZE gdc1u28QYAdzBUfRPFB+I9dusWQdiOOVNSt74IPWrMk7k47Wm5UmIssbEpWLS0kUYHry 6htTM2asK+qjDkLWTvJvbgy9PNKmI0UC5wM6LwmoBSkOorLo1Rmvddn0YmmBqb9OIHSo 0i4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id w15sm2377437edw.27.2017.05.18.02.47.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 02:47:47 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Suzuki K Poulose , Mark Rutland , andreyknvl@google.com, stable@vger.kernel.org, Christoffer Dall Subject: [PULL 11/13] kvm: arm/arm64: Fix use after free of stage2 page table Date: Thu, 18 May 2017 11:47:20 +0200 Message-Id: <20170518094722.9926-12-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170518094722.9926-1-cdall@linaro.org> References: <20170518094722.9926-1-cdall@linaro.org> MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Suzuki K Poulose We yield the kvm->mmu_lock occassionaly while performing an operation (e.g, unmap or permission changes) on a large area of stage2 mappings. However this could possibly cause another thread to clear and free up the stage2 page tables while we were waiting for regaining the lock and thus the original thread could end up in accessing memory that was freed. This patch fixes the problem by making sure that the stage2 pagetable is still valid after we regain the lock. The fact that mmu_notifer->release() could be called twice (via __mmu_notifier_release and mmu_notifier_unregsister) enhances the possibility of hitting this race where there are two threads trying to unmap the entire guest shadow pages. While at it, cleanup the redudant checks around cond_resched_lock in stage2_wp_range(), as cond_resched_lock already does the same checks. Cc: Mark Rutland Cc: Radim Krčmář Cc: andreyknvl@google.com Cc: Paolo Bonzini Cc: stable@vger.kernel.org Acked-by: Marc Zyngier Signed-off-by: Suzuki K Poulose Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall --- virt/kvm/arm/mmu.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) -- 2.9.0 diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index 704e35f..a2d6324 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -295,6 +295,13 @@ static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size) assert_spin_locked(&kvm->mmu_lock); pgd = kvm->arch.pgd + stage2_pgd_index(addr); do { + /* + * Make sure the page table is still active, as another thread + * could have possibly freed the page table, while we released + * the lock. + */ + if (!READ_ONCE(kvm->arch.pgd)) + break; next = stage2_pgd_addr_end(addr, end); if (!stage2_pgd_none(*pgd)) unmap_stage2_puds(kvm, pgd, addr, next); @@ -1170,11 +1177,13 @@ static void stage2_wp_range(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) * large. Otherwise, we may see kernel panics with * CONFIG_DETECT_HUNG_TASK, CONFIG_LOCKUP_DETECTOR, * CONFIG_LOCKDEP. Additionally, holding the lock too long - * will also starve other vCPUs. + * will also starve other vCPUs. We have to also make sure + * that the page tables are not freed while we released + * the lock. */ - if (need_resched() || spin_needbreak(&kvm->mmu_lock)) - cond_resched_lock(&kvm->mmu_lock); - + cond_resched_lock(&kvm->mmu_lock); + if (!READ_ONCE(kvm->arch.pgd)) + break; next = stage2_pgd_addr_end(addr, end); if (stage2_pgd_present(*pgd)) stage2_wp_puds(pgd, addr, next);