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[209.132.180.67]) by mx.google.com with ESMTP id y63-v6si4614228pgd.435.2018.09.13.11.06.10; Thu, 13 Sep 2018 11:06:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="YP3b5fT/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728045AbeIMXQo (ORCPT + 6 others); Thu, 13 Sep 2018 19:16:44 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:45418 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726396AbeIMXQo (ORCPT ); Thu, 13 Sep 2018 19:16:44 -0400 Received: by mail-pg1-f196.google.com with SMTP id x26-v6so3093114pge.12 for ; Thu, 13 Sep 2018 11:06:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IcdjBf6hpefPaBGV+IahZNov4drS61mOuhpNieTWlYI=; b=YP3b5fT/nw/BpNTfwP85rrdqWXwRXr1eWO/r0Rp0M70tGuL7vzJMTb/DPSBEnQLWGX i7kT+mXHK41SgPxTo7sZvZZ7DhCFtimnp1xFZDwQnmCUEmXot+cBsSK1PCBrtktNmO12 7La/aY9AXtmfZFFOtwwbiQpiDr6Isw6419L3k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IcdjBf6hpefPaBGV+IahZNov4drS61mOuhpNieTWlYI=; b=niXWWa4DE6welOkUunUP33cYLD1V3QPPt9EFMqLfk/JEiPlFIh6U3Jwbe9GG/XCyo/ D661Qsf7wbJK1OipuQQ6DcvVQ/+botdGLD0Q1OKNVQaqr2rCrT5ykh51PKeuEC17JFUs R6+ZCFuQ7vlwpSh9VJD4as8VdenMR16TNnaGvzp7odzR23rAQyNeN32kHDAr8yJBcCXK uEkIb0lNRE1ePfMthxt5bRgeG+K9KzDAxo28whwFxgAOsbS4SOsrQ+PI0jtG/9B9cJzD v3K7FJ7bipPXYDCD2SERTCKn7qUZz5nwyBRmU6TkK8d6iWBpxHgQjZdDvQdPOVAAGmfN 0x5Q== X-Gm-Message-State: APzg51DS6Hq+x2HmunG1vF3QK+U1cwq7XbGot5AtwYZclObLI1NtSFnE xj7NZnDEtOh2dXKr9gJscZ6T X-Received: by 2002:a62:438f:: with SMTP id l15-v6mr8651573pfi.196.1536861967718; Thu, 13 Sep 2018 11:06:07 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:6115:a36e:955b:f94d:4607:e9b9]) by smtp.gmail.com with ESMTPSA id u184-v6sm8856802pgd.46.2018.09.13.11.05.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Sep 2018 11:06:07 -0700 (PDT) From: Manivannan Sadhasivam To: heiko@sntech.de, robh+dt@kernel.org Cc: vicencb@gmail.com, shawn.lin@rock-chips.com, ezequiel@collabora.com, enric.balletbo@collabora.com, pbrobinson@gmail.com, tom@vamrs.com, dev@vamrs.com, stephen@vamrs.com, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 1/4] arm64: dts: rockchip: Split out common nodes for Rock960 based boards Date: Thu, 13 Sep 2018 23:35:42 +0530 Message-Id: <20180913180545.29756-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180913180545.29756-1-manivannan.sadhasivam@linaro.org> References: <20180913180545.29756-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since the same family members of Rock960 boards (Rock960 and Ficus) share the same configuration, split out the common nodes into a common dtsi file for reducing code duplication. The board specific nodes for Ficus boards are then placed in corresponding board DTS file. Below are some of the key differences between both Rock960 and Ficus boards: 1. Different host enable GPIO for USB 2. Different power and reset GPIO for PCI-E 3. No Ethernet port on Rock960 Only the properties which differ between both boards are placed in the board specific dts and the reset of the nodes are placed in common dtsi file. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Ezequiel Garcia --- arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 524 +---------------- .../boot/dts/rockchip/rk3399-rock960.dtsi | 541 ++++++++++++++++++ 2 files changed, 546 insertions(+), 519 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi -- 2.17.1 diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts index 8978d924eb83..cce266da28cd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts @@ -7,8 +7,7 @@ */ /dts-v1/; -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" +#include "rk3399-rock960.dtsi" / { model = "96boards RK3399 Ficus"; @@ -24,97 +23,6 @@ clock-output-names = "clkin_gmac"; #clock-cells = <0>; }; - - vcc1v8_s0: vcc1v8-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_drv>; - regulator-boot-on; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc5v0_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 0>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; }; &gmac { @@ -133,279 +41,8 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - status = "okay"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_hdmi: LDO_REG2 { - regulator-name = "vcca1v8_hdmi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: LDO_REG4 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc3v0_sd: LDO_REG5 { - regulator-name = "vcc3v0_sd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca0v9_hdmi: LDO_REG7 { - regulator-name = "vcca0v9_hdmi"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&io_domains { - bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ - audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ - sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ - gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - &pcie0 { ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_1v8>; - status = "okay"; }; &pinctrl { @@ -416,31 +53,6 @@ }; }; - sdmmc { - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = - <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>, - <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>, - <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>, - <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>; - }; - }; - pcie { pcie_drv: pcie-drv { rockchip,pins = @@ -448,23 +60,6 @@ }; }; - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 21 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = - <1 17 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = - <1 14 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - usb2 { host_vbus_drv: host-vbus-drv { rockchip,pins = @@ -473,127 +68,18 @@ }; }; -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - clock-frequency = <100000000>; - clock-freq-min-max = <100000 100000000>; - disable-wp; - sd-uhs-sdr104; - vqmmc-supply = <&vcc_sd>; - card-detect-delay = <800>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - &usbdrd_dwc3_0 { - status = "okay"; dr_mode = "host"; }; -&usbdrd3_1 { - status = "okay"; -}; - &usbdrd_dwc3_1 { - status = "okay"; dr_mode = "host"; }; -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; +&vcc3v3_pcie { + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; }; -&vopl_mmu { - status = "okay"; +&vcc5v0_host { + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi new file mode 100644 index 000000000000..cc9c373f3a37 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi @@ -0,0 +1,541 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2018 Linaro Ltd. + */ + +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + vcc1v8_s0: vcc1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-boot-on; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 0>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + status = "okay"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v0_sd: LDO_REG5 { + regulator-name = "vcc3v0_sd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 17 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 14 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + clock-frequency = <100000000>; + clock-freq-min-max = <100000 100000000>; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; + card-detect-delay = <800>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; From patchwork Thu Sep 13 18:05:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 146638 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp892915ljw; Thu, 13 Sep 2018 11:06:20 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZFzcL9ELsPdXcdAx7XoCzWZT2zBT251Oo1n/j0v6bFBdlJlsL/woyrAxKQJAa9Nswkhxf/ X-Received: by 2002:a63:8f17:: with SMTP id n23-v6mr6437805pgd.131.1536861979972; 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[209.132.180.67]) by mx.google.com with ESMTP id l9-v6si4774683pfe.11.2018.09.13.11.06.19; Thu, 13 Sep 2018 11:06:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jybs0AEE; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728272AbeIMXQy (ORCPT + 6 others); Thu, 13 Sep 2018 19:16:54 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:44047 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728240AbeIMXQx (ORCPT ); Thu, 13 Sep 2018 19:16:53 -0400 Received: by mail-pf1-f195.google.com with SMTP id k21-v6so3019445pff.11 for ; Thu, 13 Sep 2018 11:06:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UhWsM1uFegA3yqM6IdX1PUXA06hwvmU505oKPVKDDYw=; b=Jybs0AEEia4rbecGeVTRjb3+rZjXXZ9udToUg2BmfazsCMZbWAY8uqe/0H20VRQwLf hDSVlj8V4Ly3MDH1Wk+zgAsC0rAnJ2yH0TzdXv0UiNE4qWUAQ5YTxiBn3RNDmKPIjsf1 TltrxCtcxPR7vz6lhG8e8xexa4OFphNJQGj44= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UhWsM1uFegA3yqM6IdX1PUXA06hwvmU505oKPVKDDYw=; b=ZIDqNZmwTsLlYTJAASgwsYXq/zZQD1XHhDUpmmKv1nq5PuznB3GGa/S3MelC9xjSGY TTzVuFwMl4TWEqcMqGudRQykNaJG2L5bSG/chO2y4O85MJL5lDgo3YmUJG4BpygSqnWT KKKwp8GJTMXdx1H30njXKwNen9C7HlfvD5kCGK3LDVMJS7dUVJkybHwzzYH56lepc2vi 7QsyZ22Phkx1nufCbbGd2IHF8fIWQ+iBql03ULoMQhe7vG82eVPyUBbZZTUjfpCWs2zD zTPKPy45La6CVxM8hjql70dYRRdQPEA7pROMMs3LpPO8F/z5J0z+526iIvt6mrSpY0pe F3Hw== X-Gm-Message-State: APzg51B5YaNhSTJO/mu2fHH2KTJvk53dbfjWjs8EZzEMRZFhACGMpw1w dItQwJp/gEoQNM4NbGkVqdL7 X-Received: by 2002:a63:906:: with SMTP id 6-v6mr7958352pgj.92.1536861978297; Thu, 13 Sep 2018 11:06:18 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:6115:a36e:955b:f94d:4607:e9b9]) by smtp.gmail.com with ESMTPSA id u184-v6sm8856802pgd.46.2018.09.13.11.06.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Sep 2018 11:06:17 -0700 (PDT) From: Manivannan Sadhasivam To: heiko@sntech.de, robh+dt@kernel.org Cc: vicencb@gmail.com, shawn.lin@rock-chips.com, ezequiel@collabora.com, enric.balletbo@collabora.com, pbrobinson@gmail.com, tom@vamrs.com, dev@vamrs.com, stephen@vamrs.com, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 2/4] dt-bindings: arm: rockchip: Add binding for Rock960 board Date: Thu, 13 Sep 2018 23:35:43 +0530 Message-Id: <20180913180545.29756-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180913180545.29756-1-manivannan.sadhasivam@linaro.org> References: <20180913180545.29756-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree binding for Rock960 board from Vamrs Limited. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index acfd3c773dd0..4b6888a21db2 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -5,6 +5,10 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "vamrs,ficus", "rockchip,rk3399"; +- 96boards RK3399 Rock960 (ROCK960 Consumer Edition) + Required root node properties: + - compatible = "vamrs,rock960", "rockchip,rk3399"; + - Amarula Vyasa RK3288 board Required root node properties: - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; From patchwork Thu Sep 13 18:05:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 146639 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp893119ljw; Thu, 13 Sep 2018 11:06:31 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZjdFgZDiJ9ppyvFRb49xSWWNh3ExI3WOgpzN4Djy6rVrcfsaMrLE1oMH3WWwZhyiX1om7r X-Received: by 2002:a62:c8d2:: with SMTP id i79-v6mr8493108pfk.35.1536861991162; Thu, 13 Sep 2018 11:06:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536861991; cv=none; d=google.com; s=arc-20160816; b=rFU31f3CsmrZ992NIwzY+QM75re0l7U5/va7Rqgg7u6I655F956mPhLkqnlNrciKcR XsEghpeG8jwFTIkjrkpvtUehH2ZuunBwtvbk01AXUV64LHx7pPs6jGZzbVMfP3/ANelM rA720MbAnh5zo89WqNEn6AWNEa0BASCLYLbZG2B+M/wb71RZ/r0nZ4r+fQDdbdpvnv5T WpD+lF3VsY+q3PsR46j15LMd6eNyRnwH2cp+a8Iy3NG7faO+AleKP7xlPfwFPfzuXT8h 0FzLj9GiHmEzLAMbPEiJKj248ZY9wz3HoYEVMwPvW+IAiba0LARs+RzO2FtrGt7R2KHC 4GJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=mcD3Gsw2jnJovjOLBdoMu6xKaPO6ftrBI9PWwdc6lAA=; b=rQaboDD4jjiPOmqFm5sg+NpBvn+X37CtFQyxcOLlMZkbf93Vjs14eCGqIbPS5TaslJ cpqLzTvXz83BBAaLY8dfsubN7E5AqfV1TR6ptfP5+hY4cln4Vy3KsVOHXgfKfmcLtX6R 7D9fKk2NweNE3PSPnr+GhPXN6dbspjOVmbN5RUCZo3YwE9C4S0JKR+xS/wJn7Eq7T1TP LFm9VQSJwPLis6P2Xi7jfWVGiBPzQbT8HNJzmnXVtMHKjOeBa4ROr7R6loJGPm+q0cRm 4Ljj4YAWDP/TBP+yNQms1eqSOB3EJJe7jkwaqY+E5qxJ5cGfEiaZoONuzF4CYi32I1Xf QeqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dYVeaEjH; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r69-v6si4472497pfl.260.2018.09.13.11.06.30; Thu, 13 Sep 2018 11:06:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dYVeaEjH; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727999AbeIMXRF (ORCPT + 6 others); Thu, 13 Sep 2018 19:17:05 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:42084 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727811AbeIMXRE (ORCPT ); Thu, 13 Sep 2018 19:17:04 -0400 Received: by mail-pf1-f193.google.com with SMTP id l9-v6so3017332pff.9 for ; Thu, 13 Sep 2018 11:06:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mcD3Gsw2jnJovjOLBdoMu6xKaPO6ftrBI9PWwdc6lAA=; b=dYVeaEjHus1bM2c+C4F4blFVr+BbAzeNR6AoTfS3UuP/T5UpbNpgfy1mjWFbgSOlR6 np+IrjZitgA0UydwXxPNXDRUYB+r3oELexUMaAq2RCiBYzDHa2adEjMuyFJsPmGU5GFY hLoDgXdXZyht9kpzdcSJ1kW9outArXsHq16L0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mcD3Gsw2jnJovjOLBdoMu6xKaPO6ftrBI9PWwdc6lAA=; b=qUJ2iVbOlVPSDSooq9b2eIGrucHBjjf9cY4O9jYtq07Ko2wayJm4Vp20jPje4Xo91j NLWGueG1VoW9i7/6SXHnAgLzeVRrdR7mTSuuwW8vfbH86mYglVxCF7eQjnMJnb/GG/jr wNOvUKnPYFm1LjmasW/7497k5kLJvnMi+s+bFrTfrQ1HKTPTW78XG2jU5VSnC74LV7DA 0PvT7bXiK+xCAMwJtQIdz7x7qmgK+5nx+S7FOk7X5WcLfxY5oc0iL4zc8cXR+E1TxuFP QHWbFquK7zuDYruD+FV9d/nyhN6oCwZEVxyGEoUfbnjbRpsqV0CQ//FRNdPXkjh3metB FWtw== X-Gm-Message-State: APzg51AfyQGOypXktHMWhyzTLGYyNJrEZhZNXmnrHWiBO1fbgQ/cLmYB E/4kwuvWdbel0zeZ6m/J/Pkq X-Received: by 2002:a65:608b:: with SMTP id t11-v6mr8257556pgu.259.1536861988847; Thu, 13 Sep 2018 11:06:28 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:6115:a36e:955b:f94d:4607:e9b9]) by smtp.gmail.com with ESMTPSA id u184-v6sm8856802pgd.46.2018.09.13.11.06.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Sep 2018 11:06:28 -0700 (PDT) From: Manivannan Sadhasivam To: heiko@sntech.de, robh+dt@kernel.org Cc: vicencb@gmail.com, shawn.lin@rock-chips.com, ezequiel@collabora.com, enric.balletbo@collabora.com, pbrobinson@gmail.com, tom@vamrs.com, dev@vamrs.com, stephen@vamrs.com, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 3/4] arm64: boot: dts: rockchip: Add support for Rock960 board Date: Thu, 13 Sep 2018 23:35:44 +0530 Message-Id: <20180913180545.29756-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180913180545.29756-1-manivannan.sadhasivam@linaro.org> References: <20180913180545.29756-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree support for Rock960 board, one of the Consumer Edition boards of the 96Boards family. This board support utilizes the common Rock960 family board support that includes Ficus 96Board. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3399-rock960.dts | 52 +++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock960.dts -- 2.17.1 diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index b0092d95b574..57c0d76458e6 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -14,5 +14,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts new file mode 100644 index 000000000000..3c3308daec98 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Linaro Ltd. + */ + +/dts-v1/; +#include "rk3399-rock960.dtsi" + +/ { + model = "96boards Rock960"; + compatible = "vamrs,rock960", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; + +&vcc3v3_pcie { + gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host { + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; +}; From patchwork Thu Sep 13 18:05:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 146640 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp893256ljw; Thu, 13 Sep 2018 11:06:40 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYXwdp3AlnLWv3G1bGw4iA4Vx7w8nGCn/Xx+gWA4OELkTxHSP2R+ojFJuVRJnGvLrPUg98w X-Received: by 2002:a62:be03:: with SMTP id l3-v6mr8571410pff.138.1536862000163; Thu, 13 Sep 2018 11:06:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536862000; cv=none; d=google.com; s=arc-20160816; b=PwZJTjfFMwy5PGidJOi8ltKcnCuKjpGfS+LHAixuhgok81ZraWB2EKQLlkwh1pkXmY mD/KBKUvTzMXYAYyRcKh3QxvxzJVD4hkUnskQ8Vj3VBANUx/ZXcWAqgC6PkC58b8aWzM QRCKwPw9255gOcMLYaGKqZTH+MhU6TNiOy530mLXAlp6g0/O8BJ1xe1Tnau7bK6mY+i4 9sXn2WAKepH9R2KrgH5E+LKLSXyycprpk0H0Jrxe3bDCfpENrZrDnYS5PdsRaFHBdt5f 4XFbHb+v2LDpLei0DWx0c8zFDoedRyCwthT88f31FgWx2qQVGsw4APTyJRQ3ewSN/OG3 9yvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=8GR756oMPzkgi0jaNNzmFs58kYiZa/AVR98KWjBKvlE=; b=wfH+3hdSl5hKarzTI1SKPL4GwBxk1qIq+Wg8UNA23tkYkdqtR+eiAbviX7tX9saFIv dV5QNtqxKnakWfAWoBfCvZUjTznw89P1+sfU8BSzK5ZGMwNpoX+VdUB3OmQa7XfNvclO UqUG2tVwfcApWtqtyeJ9PkKnH7O0AlUpQYE2LJGJkJeI69y9PGwOpy3uFJF4SYPW0Kid u9O9jXk2IlHe/923OABXIy3cEYZhFtFCxLZdPWpMENOHxAcP1tbHKVnRYBt8WRL7fZdG Z4XyIs8q6DUUA7jRuDqhE1jmlF5kQbGocqZudilIjjxDZNr/DDpGVLXJ81Cg370ZTQV8 wOww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XYoqmiXu; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b7-v6si4815768pfj.245.2018.09.13.11.06.39; Thu, 13 Sep 2018 11:06:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XYoqmiXu; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728257AbeIMXRO (ORCPT + 6 others); Thu, 13 Sep 2018 19:17:14 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:42665 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727953AbeIMXRN (ORCPT ); Thu, 13 Sep 2018 19:17:13 -0400 Received: by mail-pg1-f196.google.com with SMTP id y4-v6so3103940pgp.9 for ; Thu, 13 Sep 2018 11:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8GR756oMPzkgi0jaNNzmFs58kYiZa/AVR98KWjBKvlE=; b=XYoqmiXu03cT6iyfSLsIMUKfM8cZ2rZtwRGnI+M6bm0ytEbjrZf9owv0FTNxC3tNr2 ksjIaBL/E8NI5PbJos5Ebtam9KQfn4RVq8Hvc24Weyu9zQMNmcbySc+j6WfjMhYpGpOM WQoM17rBNVj9JjeNTZzz4E0GbfJC/gvY87AkE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8GR756oMPzkgi0jaNNzmFs58kYiZa/AVR98KWjBKvlE=; b=fPl/WKJ5Z1Srq/CJiUoGv2UZogpQvATE0hVgbSqHJ2/+Ub5QOTXJ5u9B3WQ1GXvuco KmskwvriksPDBt/LUtN6hrSLH9FzZGagPG+JyGh9qQjdQk6HA53ZroikhrAK1DeUe24j vBYURRKiDFL3bAwTPH80SSTkFVIJ2SP1b/VJaTopdW8Majyuu/ohLXvTM1pUwWI71E34 HCcMSKOTiVSkHe9myiAXkb1AUwJSJAZJwchocCQ76IR1oItq/3725TPOrXNayV6/mrtc RXSg/7qKJwizSLO26adQhIAOcVhtotbn+1rKMVMwSESKJzkpK4SyseR0tm3em5gIWtYo tBJQ== X-Gm-Message-State: APzg51BcBvOQ2Lavj81eBpZ6qCBN21/iNBqBv2+KkfAmOnBRXog6Vybf so5IDKxHn7sWpUzWkPILc6dF X-Received: by 2002:a62:90d4:: with SMTP id q81-v6mr8558264pfk.37.1536861998084; Thu, 13 Sep 2018 11:06:38 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:6115:a36e:955b:f94d:4607:e9b9]) by smtp.gmail.com with ESMTPSA id u184-v6sm8856802pgd.46.2018.09.13.11.06.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Sep 2018 11:06:37 -0700 (PDT) From: Manivannan Sadhasivam To: heiko@sntech.de, robh+dt@kernel.org Cc: vicencb@gmail.com, shawn.lin@rock-chips.com, ezequiel@collabora.com, enric.balletbo@collabora.com, pbrobinson@gmail.com, tom@vamrs.com, dev@vamrs.com, stephen@vamrs.com, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 4/4] arm64: dts: rockchip: Enable SD card detection for Rock960 boards Date: Thu, 13 Sep 2018 23:35:45 +0530 Message-Id: <20180913180545.29756-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180913180545.29756-1-manivannan.sadhasivam@linaro.org> References: <20180913180545.29756-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For proper working of SD cards, let's add the Card Detect GPIO property to the common devicetree for Rock960 family boards. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi index cc9c373f3a37..6c8c4ab044aa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi @@ -439,6 +439,7 @@ cap-sd-highspeed; clock-frequency = <100000000>; clock-freq-min-max = <100000 100000000>; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; disable-wp; sd-uhs-sdr104; vqmmc-supply = <&vcc_sd>;