From patchwork Wed Jul 28 13:55:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488096 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5194C432BE for ; Wed, 28 Jul 2021 13:55:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A1DC360F45 for ; Wed, 28 Jul 2021 13:55:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234107AbhG1Nz4 (ORCPT ); Wed, 28 Jul 2021 09:55:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233254AbhG1Nzz (ORCPT ); Wed, 28 Jul 2021 09:55:55 -0400 Received: from mail-qk1-x733.google.com (mail-qk1-x733.google.com [IPv6:2607:f8b0:4864:20::733]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BE05C061764; Wed, 28 Jul 2021 06:55:54 -0700 (PDT) Received: by mail-qk1-x733.google.com with SMTP id 190so2206447qkk.12; Wed, 28 Jul 2021 06:55:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p0c/IyLNYUcFRUNhIkMuU0AI+TpmMpaReD0iwylBw/k=; b=lI4HE7O3xfbrLZHlZEm6CLq8NrFgzrcXzQ+FCqH4bMco4nV+Hvz5agyILutqUHegUn o/Bjv/EaB5qT2qnagUeroiQWSXrMpTP6U12EHVinFY8m8E9ABcYNZlznekse8OFtpNTq t3oFf6NxAUCyBCOUO9UtD+/cJODji4nbwykjNY24dUPxbY/YaTTnjF+r+NTBdziyRRJB M17Q1QZZCJUAOVjylL/t4f4sv19oMepslZ1RZ+xLwjKNl0INSPXFtCRcdXwMKLPB7MnL CBhJ2vQoafmjKj0sqQ2i3HEfknj+CtwZ6pAEAMXJBjTI9Ancuu5gyLgdCAiyevy6lAUf N1ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p0c/IyLNYUcFRUNhIkMuU0AI+TpmMpaReD0iwylBw/k=; b=pYJoec0JojxNfUQE26G9zxalXHoabs1Og2eMT8cz76PfbyIHtjshjQ1Z1KZkJINqsq 7erE0ebgUORIPieSNd89vzxWKmBJZ20d++p2udaVeC4sRuXE8UhJkHU9hJ7pcoiUgETt LLSzV/8dLtKDy2cLoYaQLXiNBSVBUkKan2NS+hxe+clljV2m0alhlH/PG0I9jF3iqCkO rzJC/eEJhtzpLoKd6eDjIjDsaLfFJS3Jf3EI7jAibGQ+a3iRXeR+yKOmNnDbvmXoDOgE +ZsEK9kcLiS2AV1nMR7xT/vnTr5MM1W6tlQw+IX+0sTTxf8aQ7PGg00inmFggM7JFgwc xphA== X-Gm-Message-State: AOAM532dn9yMw+Xy1CH0uB0xCRPgTV1Otc+C5adTb9YQgrN2LaeTqMh0 +vnrG6zkmNTkRanBUA54sDQ= X-Google-Smtp-Source: ABdhPJzoNpKc+OhcYe2emeCQDQYmrYhrUprg7KEWryMcCF76OXmFd+tXGIlTeIs5GjwINx54kLx8gg== X-Received: by 2002:a37:62d2:: with SMTP id w201mr15042275qkb.318.1627480553423; Wed, 28 Jul 2021 06:55:53 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id t64sm27202qkd.71.2021.07.28.06.55.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 06:55:52 -0700 (PDT) From: Peter Geis To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH 1/9] dt-bindings: gpio: rockchip, gpio-bank: increase max clocks Date: Wed, 28 Jul 2021 09:55:26 -0400 Message-Id: <20210728135534.703028-2-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728135534.703028-1-pgwipeout@gmail.com> References: <20210728135534.703028-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The rk356x adds a debounce clock to the gpio devices. Increase the maximum clocks to account for it. Signed-off-by: Peter Geis --- Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml index d993e002cebe..489a5263a7a1 100644 --- a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml +++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml @@ -22,7 +22,7 @@ properties: maxItems: 1 clocks: - maxItems: 1 + maxItems: 2 gpio-controller: true From patchwork Wed Jul 28 13:55:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1CC4C19F31 for ; Wed, 28 Jul 2021 13:55:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BEE4761038 for ; Wed, 28 Jul 2021 13:55:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233254AbhG1Nz6 (ORCPT ); Wed, 28 Jul 2021 09:55:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236292AbhG1Nz4 (ORCPT ); Wed, 28 Jul 2021 09:55:56 -0400 Received: from mail-qk1-x72c.google.com (mail-qk1-x72c.google.com [IPv6:2607:f8b0:4864:20::72c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 111FAC061757; Wed, 28 Jul 2021 06:55:55 -0700 (PDT) Received: by mail-qk1-x72c.google.com with SMTP id az7so2246667qkb.5; Wed, 28 Jul 2021 06:55:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vXk/J4q5mPEjnLuepFqEKq93BJsZukmkkBYD3V+Z3Tk=; b=FMHCoImVFrprWfhN8LCCWjfLHbL6/mwjUYPLJrawre3JFTHn4wzbqn05g3hX5vP42x 5B56hqiX7ej/9k4CjBcisgJMI+iAmJdkc4jIm/lJtVQ4TrbYWvEPy1EgtvMAKRgp1xkA bDlm9XRdoJ2o5Zr+RFnCxhwG+Xclsyd3mSaS8lulGeXwIrLmHCQfBqA4QRLT2kVqrPKo Pb2SOa30d457++7mwzRkEgo4L05L9ZMCXa8LLtAJi+LIyQUgdWneKqp9rkAmZMyOPxEp 5qgB1rRKUpfCrUd3sYdoZg7NRE2MpkKQmOiHnhQY0eTxeVatCP0fIj/Ek7tI4xZu3vAo FBZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vXk/J4q5mPEjnLuepFqEKq93BJsZukmkkBYD3V+Z3Tk=; b=kTfUJIXB6FIaYHWIEtfFAN3B1ZxuljHJX/5ilKQPRu6i7+wzGjit6bVwnowOWW9ssU nVgdeGiJJwXw+wLCZzUFSQcCccQNBUb21aUC0/KxvB2us8fQ+AL40yNMOZqucAUKgrM3 RFy99WtRMWD3qP2kouTgoAIX72THbbfxFQRTvB34zTs4uK1nS8akZusx96S8EgfsSeaZ xRMKOhWG4L8VfpymwWUjStKRvG18upLjT5k9drgu5kfCbJm1ofgIKwtqKokAbcz5Ai2H h9RjIVsTA7+Rka+M2vATPsuuGkSjk7A14VPp3D+MVuXLi8Ro0BOi2AaVb7j9upp8E4hU ibDg== X-Gm-Message-State: AOAM530BD1ko8gjkgoUOjqv8F3B64dZY74Me7p1GxFaNoDc/MIQtPB40 QPRwco/AcMNWytOXzvJQcXs= X-Google-Smtp-Source: ABdhPJz6f8hVcTQd5Bpdw7dmeHdhawQ5NdaItj5fYAXgvjQHsKkaWbMr6OGvUs/d0SCvBFkFtwwQTQ== X-Received: by 2002:a05:620a:5f6:: with SMTP id z22mr27262899qkg.195.1627480554191; Wed, 28 Jul 2021 06:55:54 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id t64sm27202qkd.71.2021.07.28.06.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 06:55:53 -0700 (PDT) From: Peter Geis To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH 2/9] arm64: dts: rockchip: fix rk3568 mbi-alias Date: Wed, 28 Jul 2021 09:55:27 -0400 Message-Id: <20210728135534.703028-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728135534.703028-1-pgwipeout@gmail.com> References: <20210728135534.703028-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The mbi-alias incorrectly points to 0xfd100000 when it should point to 0xfd410000. This fixes MSIs on rk3568. Fixes: a3adc0b9071d ("arm64: dts: rockchip: add core dtsi for RK3568 SoC") Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 322971318d5a..f7ecdfd66f86 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -195,7 +195,7 @@ gic: interrupt-controller@fd400000 { interrupts = ; interrupt-controller; #interrupt-cells = <3>; - mbi-alias = <0x0 0xfd100000>; + mbi-alias = <0x0 0xfd410000>; mbi-ranges = <296 24>; msi-controller; }; From patchwork Wed Jul 28 13:55:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19424C43216 for ; Wed, 28 Jul 2021 13:55:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 06EAA60EC0 for ; Wed, 28 Jul 2021 13:55:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236444AbhG1Nz6 (ORCPT ); Wed, 28 Jul 2021 09:55:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236327AbhG1Nz5 (ORCPT ); Wed, 28 Jul 2021 09:55:57 -0400 Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A44FFC061764; Wed, 28 Jul 2021 06:55:55 -0700 (PDT) Received: by mail-qk1-x730.google.com with SMTP id f22so2230571qke.10; Wed, 28 Jul 2021 06:55:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S56htb9vVkDrFmzApk71DTCJizGCv0+IZp82FWSdz/g=; b=E8cuFmXqjHfLllE6yR7g1E34dMT/0iPJZw6DLYh6lm8kZm7xOuai4TWh4DiCAfglld OnkhoLtHVQ8XVSiuL/R44vrYuoaW3wS8lMUnEpQvQfKyx7afA/Up7DR5NvctljZKJw4N mN2Nzyls+8dn9LasQQcI13VTAcI69c29GUtW8qh9LIHm9ApYX9X541+w8x9wGMFZvhGG Z3Ft6wrgHRbdps4jgahEOwTJ9n/BZ6TtaqSV/yy4Rr4TKansQQIKCPGasrLclgIP//tS bw5+DddVYToqrUiyuFnSTI1MmbgNgirAUzId+NDL8UazYC3m0YeJ1rIQtq/kIkZNugG1 JYhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S56htb9vVkDrFmzApk71DTCJizGCv0+IZp82FWSdz/g=; b=icTHoF9rzzF+kXLKTik0yqJdQoo5jpudH0ZNukUglyCx0w3l3ykHEWnbqo7cRewPIL eJ/AEwn57GqR5I4g0WwubODxeBPvJFq7o9cD6G/I6uD6kPrY5wry9cyW4iLa7rjrvAy7 if/xuSqEJMNGxJPsN+9mGFMKoUoIEmyQSjq1K+rJgkN5vgmLB2K4bpIg/DfXt0uDWqrP jyY4lGSpmZiKjsNJZBkc7ArbWCDI0L50RcJjSd3mmR6L7tjfYkitiyrpwJAajy7Ihl0g wCIZJQsxK9/isrRv8EL3qWt8Nqt4tZ2fe7VpuBGDYeOnKpnG5DFFUq8tFVfy+yz6+ha5 qWOw== X-Gm-Message-State: AOAM533Q2Q0K2+Km1qapsWlR+5XQcN2pAMoBBNVh7eCISDRouQdDd8rf 93H/3fQvskSaYxilJ6Cgsec= X-Google-Smtp-Source: ABdhPJwP81NA2r+kZGDYStvsEpwYxM6uFEq0jWx5yFJXsrySE3baKz0WlLBBJ3XVPEOBZmyn58D0XQ== X-Received: by 2002:a05:620a:537:: with SMTP id h23mr7409375qkh.361.1627480554839; Wed, 28 Jul 2021 06:55:54 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id t64sm27202qkd.71.2021.07.28.06.55.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 06:55:54 -0700 (PDT) From: Peter Geis To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH 3/9] arm64: dts: rockchip: add rk356x gpio debounce clocks Date: Wed, 28 Jul 2021 09:55:28 -0400 Message-Id: <20210728135534.703028-4-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728135534.703028-1-pgwipeout@gmail.com> References: <20210728135534.703028-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The rk356x added a debounce clock to the gpio devices. This clock is necessary for the new v2 gpio driver to bind. Add the clocks to the rk356x device tree. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index f7ecdfd66f86..c2aa7aeec58d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -750,7 +750,7 @@ gpio0: gpio@fdd60000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfdd60000 0x0 0x100>; interrupts = ; - clocks = <&pmucru PCLK_GPIO0>; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -761,7 +761,7 @@ gpio1: gpio@fe740000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe740000 0x0 0x100>; interrupts = ; - clocks = <&cru PCLK_GPIO1>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -772,7 +772,7 @@ gpio2: gpio@fe750000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe750000 0x0 0x100>; interrupts = ; - clocks = <&cru PCLK_GPIO2>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -783,7 +783,7 @@ gpio3: gpio@fe760000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe760000 0x0 0x100>; interrupts = ; - clocks = <&cru PCLK_GPIO3>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -794,7 +794,7 @@ gpio4: gpio@fe770000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe770000 0x0 0x100>; interrupts = ; - clocks = <&cru PCLK_GPIO4>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; From patchwork Wed Jul 28 13:55:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F354C4320E for ; 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Wed, 28 Jul 2021 06:55:55 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id t64sm27202qkd.71.2021.07.28.06.55.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 06:55:55 -0700 (PDT) From: Peter Geis To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH 4/9] arm64: dts: rockchip: add rk356x gmac1 node Date: Wed, 28 Jul 2021 09:55:29 -0400 Message-Id: <20210728135534.703028-5-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728135534.703028-1-pgwipeout@gmail.com> References: <20210728135534.703028-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the gmac1 controller to the rk356x device tree. This is the controller common to both the rk3568 and rk3566. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 48 ++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index c2aa7aeec58d..77c679304916 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -18,6 +18,7 @@ / { #size-cells = <2>; aliases { + ethernet1 = &gmac1; gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; @@ -344,6 +345,53 @@ sdmmc2: mmc@fe000000 { status = "disabled"; }; + gmac1: ethernet@fe010000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe010000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, + <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + snps,mixed-burst; + snps,tso; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + qos_gpu: qos@fe128000 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe128000 0x0 0x20>; From patchwork Wed Jul 28 13:55:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2936AC19F37 for ; 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Wed, 28 Jul 2021 06:55:56 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id t64sm27202qkd.71.2021.07.28.06.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 06:55:55 -0700 (PDT) From: Peter Geis To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH 5/9] arm64: dts: rockchip: add rk3568 tsadc nodes Date: Wed, 28 Jul 2021 09:55:30 -0400 Message-Id: <20210728135534.703028-6-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728135534.703028-1-pgwipeout@gmail.com> References: <20210728135534.703028-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the thermal and tsadc nodes to the rk3568 device tree. There are two sensors, one for the cpu, one for the gpu. Signed-off-by: Peter Geis --- .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi index a588ca95ace2..b464c7bda1f7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 { }; tsadc { + /omit-if-no-ref/ + tsadc_gpio: tsadc-gpio { + rockchip,pins = + <0 RK_PA1 0 &pcfg_pull_none>; + }; + /omit-if-no-ref/ tsadcm0_shut: tsadcm0-shut { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 77c679304916..0905fac0726a 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -51,6 +51,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0x0 0x0>; clocks = <&scmi_clk 0>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -59,6 +60,7 @@ cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -67,6 +69,7 @@ cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x200>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -75,6 +78,7 @@ cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x300>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 { status = "disabled"; }; + thermal_zones: thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + }; + }; + + tsadc: tsadc@fe710000 { + compatible = "rockchip,rk3568-tsadc"; + reg = <0x0 0xfe710000 0x0 0x100>; + interrupts = ; + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; + assigned-clock-rates = <17000000>, <700000>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, + <&cru SRST_TSADCPHY>; + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <95000>; + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_gpio>; + pinctrl-1 = <&tsadc_shutorg>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + saradc: saradc@fe720000 { compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; reg = <0x0 0xfe720000 0x0 0x100>; From patchwork Wed Jul 28 13:55:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0373C432BE for ; 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Wed, 28 Jul 2021 06:55:56 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id t64sm27202qkd.71.2021.07.28.06.55.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 06:55:56 -0700 (PDT) From: Peter Geis To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH 6/9] arm64: dts: rockchip: add missing rk3568 cru phandles Date: Wed, 28 Jul 2021 09:55:31 -0400 Message-Id: <20210728135534.703028-7-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728135534.703028-1-pgwipeout@gmail.com> References: <20210728135534.703028-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The grf and pmugrf phandles are necessary for the pmucru and cru to modify clocks. Add these phandles to permit adjusting the clock rates and muxes. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 0905fac0726a..8ba0516eedd8 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -218,6 +218,8 @@ grf: syscon@fdc60000 { pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; + rockchip,grf = <&grf>; + rockchip,pmugrf = <&pmugrf>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -225,6 +227,7 @@ pmucru: clock-controller@fdd00000 { cru: clock-controller@fdd20000 { compatible = "rockchip,rk3568-cru"; reg = <0x0 0xfdd20000 0x0 0x1000>; + rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; }; From patchwork Wed Jul 28 13:55:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 842A0C43214 for ; Wed, 28 Jul 2021 13:56:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6FFBA61052 for ; Wed, 28 Jul 2021 13:56:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236837AbhG1N4F (ORCPT ); Wed, 28 Jul 2021 09:56:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236694AbhG1N4A (ORCPT ); Wed, 28 Jul 2021 09:56:00 -0400 Received: from mail-qt1-x82b.google.com (mail-qt1-x82b.google.com [IPv6:2607:f8b0:4864:20::82b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66EB6C0613C1; Wed, 28 Jul 2021 06:55:58 -0700 (PDT) Received: by mail-qt1-x82b.google.com with SMTP id d2so1371567qto.6; Wed, 28 Jul 2021 06:55:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mtzKWmPijMY1PkSSMWpn9rhjG/EXg2m1sprhHLtLltY=; b=Ds9SlqnSQ3e3fcKqaRkJ0UBsYCEXFeCsoK/gP94FjQfyOLD9OI2NvBjMSlQViW8OKf VxSZ5e25UdFaWFo8m8cczHQ0+GST0yAPONjulMZBc1qaq6yKyarmQSvmVrAHK9hfTVMs xkJIUdAFPp1xX6mmtjuLSc7XLinwwate3C4fSIM6zc3Z1Gk0yISSBtG4gO26vCLMZvuc BCNtERzYLGYJhaSqXauYAmR2Cc+sm4ioRAXAvghPuU7X7+Ne2EC7aJopsWKvqjcsSqvM Bo0GeEuaRoXbAhZBgBOmAdbGtzMxeNvs9c5eRketSBn+H3cbzBudi3CKXzi3MzOlLD+K b91g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mtzKWmPijMY1PkSSMWpn9rhjG/EXg2m1sprhHLtLltY=; b=uV9KaAnbLm3Yd2oYz00E8Iea4nB7XVxGsVgzOkdS1JkBROdEWdsApZD1NkthFScXUy 9JBRpOy35/GEFXJ1TT8/v6CGGM0yv4QCaqZqRvAT/mZbQP/wYCPqGCmwTq/CROarHHCH 4J1/Z3IEuao9WXKruwzxp1XLXOCLki/5pldTKRvXYFhmvyEelrxIEhuJMXjCymXfx6bL +PC7ksYqZKlWnoATm9DzqES3Jm59FWzR94DOv7DCYVX5p+t9ri12/hHfMXt3VhKQZ6UG mQRDU1KUsaQ0hQjx0Bi1kzOvBQoQQSTVG/gp56MPJSyQHVXGS/7EbXEE/7vBGR2NwJZz SC0A== X-Gm-Message-State: AOAM533ljuIjiWX9kka7hnxkO3ZJ6nAbtxpMEFPekmyNIf8aGERGCa1J RSsAKc6OW4w+LE1L1SDBq1w= X-Google-Smtp-Source: ABdhPJw+0ngqSvWhIMBN4gmqVswUOrVO/FRrq/+gqt92d9BWChoIXD856tbFqSB/Suln+UdV5QfE+g== X-Received: by 2002:ac8:5b8a:: with SMTP id a10mr4851669qta.235.1627480557540; Wed, 28 Jul 2021 06:55:57 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id t64sm27202qkd.71.2021.07.28.06.55.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 06:55:57 -0700 (PDT) From: Peter Geis To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH 7/9] arm64: dts: rockchip: adjust rk3568 pll clocks Date: Wed, 28 Jul 2021 09:55:32 -0400 Message-Id: <20210728135534.703028-8-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728135534.703028-1-pgwipeout@gmail.com> References: <20210728135534.703028-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz. These are set incorrectly by the bootloader, so fix them here. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 8ba0516eedd8..91ae3c541c1a 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -230,6 +230,8 @@ cru: clock-controller@fdd20000 { rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; + assigned-clock-rates = <1200000000>, <200000000>; }; i2c0: i2c@fdd40000 { From patchwork Wed Jul 28 13:55:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6309C43216 for ; Wed, 28 Jul 2021 13:56:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9FABD60184 for ; Wed, 28 Jul 2021 13:56:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236808AbhG1N4E (ORCPT ); Wed, 28 Jul 2021 09:56:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236691AbhG1N4A (ORCPT ); Wed, 28 Jul 2021 09:56:00 -0400 Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01CBFC061765; Wed, 28 Jul 2021 06:55:59 -0700 (PDT) Received: by mail-qv1-xf30.google.com with SMTP id w6so1551680qvh.3; Wed, 28 Jul 2021 06:55:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rg5BgE/uGT7G9Q0TLIac/vS9ZXh8BbNch3GcxmLfwSM=; b=KCMf4446wjqkcLAvYc/vbvupqGYrOHZZ1b02HVjhPcRI1c6i7NsQaGzfkq1QnfTT31 2YKT54nBCT6qx31A1U62D7cYJLst9iGtgFl6GlTWuuJeR31jSGibVdt0akxtzC+WvfKk UMzycK+q3Oj2QCgKtVMCysTOssh9c5XXnbQq4HLgtZpDl80b2IVvGdJ2lYIqMUSA8ijP A2owYG8DvECR7B6mux0+ZiX+whWSAm9poS7pQp0++qrg5bXJYdJzIPjMCfI2ChemRP/n wQ+0ggx1uDKhckqHt2AT+eXPbFLR9UmMM7MwD8g7ES8/ZHw97N+Y4VMhteaeRBZ+BiW9 Sd+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rg5BgE/uGT7G9Q0TLIac/vS9ZXh8BbNch3GcxmLfwSM=; b=qtbDFDO7oXO2mXclzCHbv8uAcdCGdrdQsIoXAJ0UcSWiwcj7nU5v/sNqtyTl0vsdMj fO0O5bZNi7Qn3iLMBYL9uLq5v0UO4E6elD7rvCiIpTrU13/GuBBC5Ttuk/LZU+2Wki6g 1f6a5dBgP1eFl7SkQ5u4nD4Jxya/84+mrJY+WiYnZa85gdgkpSgP8xKMmg5u8eea1kTZ 3ypeDZ1DAVm78bDIRkbwSVR7e3jY1X0W8OEq899vNdCe9NOsP8YALeBbcQhbLpwjvRYR 9LIjx33GVEfDXjfnj9KgvMHCy7xasGcC79UsCMqrnTwB1FPE1ynRlkn2FPJP5Izpy8Cs Hr/A== X-Gm-Message-State: AOAM533iasASpk//zHysSfCf04qDEBOzubCl/YCrCc+qXgjsO5gW/0NT c/FdBmf2JhW4HM/b1maXp3Y= X-Google-Smtp-Source: ABdhPJx8XWhJEjfq2Fvj726/Hw5wJ13Qv7bdtDwqT3fTu3+dsAeyAiYP3xpg2dW5kECYjUuFPVmy1w== X-Received: by 2002:a05:6214:188c:: with SMTP id cx12mr30649qvb.7.1627480558176; Wed, 28 Jul 2021 06:55:58 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id t64sm27202qkd.71.2021.07.28.06.55.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 06:55:57 -0700 (PDT) From: Peter Geis To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH 8/9] arm64: dts: rockchip: enable gmac node on quartz64-a Date: Wed, 28 Jul 2021 09:55:33 -0400 Message-Id: <20210728135534.703028-9-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728135534.703028-1-pgwipeout@gmail.com> References: <20210728135534.703028-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable the gmac controller on the Pine64 Quartz64 Model A. Signed-off-by: Peter Geis --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index a3cdb6c2bec6..90cdabfac86b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -19,6 +19,13 @@ chosen: chosen { stdout-path = "serial2:1500000n8"; }; + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + leds { compatible = "gpio-leds"; @@ -116,6 +123,29 @@ &cpu3 { cpu-supply = <&vdd_cpu>; }; +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -336,6 +366,13 @@ regulator-state-mem { }; }; +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { From patchwork Wed Jul 28 13:55:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E58AC4338F for ; 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Wed, 28 Jul 2021 06:55:58 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id t64sm27202qkd.71.2021.07.28.06.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 06:55:58 -0700 (PDT) From: Peter Geis To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH 9/9] arm64: dts: rockchip: add thermal support to Quartz64 Model A Date: Wed, 28 Jul 2021 09:55:34 -0400 Message-Id: <20210728135534.703028-10-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728135534.703028-1-pgwipeout@gmail.com> References: <20210728135534.703028-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the thermal nodes for the Quartz64 Model A. The Model A supports a single speed gpio fan. Signed-off-by: Peter Geis --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 90cdabfac86b..eb311ea19f6a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -26,6 +26,14 @@ gmac1_clkin: external-gmac1-clock { #clock-cells = <0>; }; + fan: gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 4500 1>; + #cooling-cells = <2>; + }; + leds { compatible = "gpio-leds"; @@ -123,6 +131,23 @@ &cpu3 { cpu-supply = <&vdd_cpu>; }; +&cpu_thermal { + trips { + cpu_hot: cpu_hot { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_hot>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; @@ -432,6 +457,10 @@ &sdmmc0 { status = "okay"; }; +&tsadc { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>;