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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:26 -0700 Message-Id: <20180915161738.25257-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 01/13] target/arm: Add ARM_FEATURE_SWP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These insns have been removed from the ISA, but are also not present on some cpus with V7VE. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + linux-user/elfload.c | 3 ++- target/arm/cpu.c | 10 ++++++++++ target/arm/translate.c | 4 ++++ 4 files changed, 17 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65c0fa0a65..acfb2f9104 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1495,6 +1495,7 @@ enum arm_features { ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ + ARM_FEATURE_SWP, /* implements swp/swpb */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 8638612aec..fcac2563f1 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -450,7 +450,6 @@ static uint32_t get_elf_hwcap(void) ARMCPU *cpu = ARM_CPU(thread_cpu); uint32_t hwcaps = 0; - hwcaps |= ARM_HWCAP_ARM_SWP; hwcaps |= ARM_HWCAP_ARM_HALF; hwcaps |= ARM_HWCAP_ARM_THUMB; hwcaps |= ARM_HWCAP_ARM_FAST_MULT; @@ -458,7 +457,9 @@ static uint32_t get_elf_hwcap(void) /* probe for the extra features */ #define GET_FEATURE(feat, hwcap) \ do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0) + /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ + GET_FEATURE(ARM_FEATURE_SWP, ARM_HWCAP_ARM_SWP); GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 258ba6dcaa..3bc7a16327 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1075,6 +1075,7 @@ static void arm926_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); set_feature(&cpu->env, ARM_FEATURE_JAZELLE); + set_feature(&cpu->env, ARM_FEATURE_SWP); cpu->midr = 0x41069265; cpu->reset_fpsid = 0x41011090; cpu->ctr = 0x1dd20d2; @@ -1089,6 +1090,7 @@ static void arm946_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_SWP); cpu->midr = 0x41059461; cpu->ctr = 0x0f004006; cpu->reset_sctlr = 0x00000078; @@ -1105,6 +1107,7 @@ static void arm1026_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); set_feature(&cpu->env, ARM_FEATURE_JAZELLE); + set_feature(&cpu->env, ARM_FEATURE_SWP); cpu->midr = 0x4106a262; cpu->reset_fpsid = 0x410110a0; cpu->ctr = 0x1dd20d2; @@ -1139,6 +1142,7 @@ static void arm1136_r2_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_SWP); cpu->midr = 0x4107b362; cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; @@ -1171,6 +1175,7 @@ static void arm1136_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_SWP); cpu->midr = 0x4117b363; cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; @@ -1204,6 +1209,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_SWP); cpu->midr = 0x410fb767; cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; @@ -1235,6 +1241,7 @@ static void arm11mpcore_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VAPA); set_feature(&cpu->env, ARM_FEATURE_MPIDR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_SWP); cpu->midr = 0x410fb022; cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; @@ -1378,6 +1385,7 @@ static void cortex_r5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_PMSA); + set_feature(&cpu->env, ARM_FEATURE_SWP); cpu->midr = 0x411fc153; /* r1p3 */ cpu->id_pfr0 = 0x0131; cpu->id_pfr1 = 0x001; @@ -1426,6 +1434,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_SWP); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; @@ -1500,6 +1509,7 @@ static void cortex_a9_initfn(Object *obj) */ set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_CBAR); + set_feature(&cpu->env, ARM_FEATURE_SWP); cpu->midr = 0x410fc090; cpu->reset_fpsid = 0x41033090; cpu->mvfr0 = 0x11110222; diff --git a/target/arm/translate.c b/target/arm/translate.c index c6a5d2ac44..2688380ae6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9390,6 +9390,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) TCGv taddr; TCGMemOp opc = s->be_data; + if (!arm_dc_feature(s, ARM_FEATURE_SWP)) { + goto illegal_op; + } + rm = (insn) & 0xf; if (insn & (1 << 22)) { From patchwork Sat Sep 15 16:17:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146779 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1938926ljw; Sat, 15 Sep 2018 09:18:22 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaohqmLLwW3ht6oN+Tex7ujkYJVlwe+fbK1tzMPLJ4lihjM/1fpYH01Dj3P4nU4ULiozKQO X-Received: by 2002:a37:9e46:: with SMTP id h67-v6mr12415794qke.329.1537028301992; Sat, 15 Sep 2018 09:18:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028301; cv=none; d=google.com; s=arc-20160816; b=a1abWRfF8Qyvtc3GFQ3dKsfCx+RSiUPTTx60IQl78R1H8MFlTqhOpNbOLpFomYbw9K DMTTTO/xIwv5+7SMbAdyuXJAAHqsP21ejG9qiMkXKoMkc4cuGG5AucUY8KDc9gSBfEV/ 2mDX7k2ebj1IFP6oHs0VeoRDh2lmrP4aXQ7gGwZ7bQ3mhv0JFbq4ExB0sQSd0Z3gs35q vUbIllo528v9fa/RW5itz4uie5v8X6LeD6mIvapalFNyHKbwga+3G+dnlEGfhYBK6gmV nE6VbCcNjbsR/vOHP1xwi+3CoyMXxKD69ko8wFf1dWMbm5q2clcoIadpazGzeEBkgSB/ 1sRg== ARC-Message-Signature: i=1; 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:27 -0700 Message-Id: <20180915161738.25257-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52b Subject: [Qemu-devel] [PATCH 02/13] target/arm: Derive id_isar0 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? Test with -machine none -cpu foo. ??? The assertion does fire for quite a lot of cpus, ??? but quite a few of them appear to be existing bugs. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3bc7a16327..44483e3dea 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -756,6 +756,50 @@ static void arm_cpu_finalizefn(Object *obj) } } +static uint32_t resolve_id_isar0(CPUARMState *env, uint32_t orig) +{ + uint32_t ret = 0; + + if (arm_feature(env, ARM_FEATURE_SWP)) { + ret = deposit32(ret, 0, 4, 1); /* Swap */ + } + if (arm_feature(env, ARM_FEATURE_V5)) { + ret = deposit32(ret , 4, 4, 1); /* BitCount */ + } + if (arm_feature(env, ARM_FEATURE_THUMB2)) { + ret = deposit32(ret, 8, 4, 1); /* BitField */ + ret = deposit32(ret, 12, 4, 1); /* CmpBranch */ + } + + /* + * Coproc -- generically, v5te has mcrr (3), v6 has mcrr2 (4), + * and v8 requires none (0). There does not appear to be a way + * to guess the value though, as some v6 and v7 cores also use none. + */ + ret |= orig & MAKE_64BIT_MASK(16, 4); + + if (arm_feature(env, ARM_FEATURE_V5)) { + ret = deposit32(ret, 20, 4, 1); /* Debug */ + } + /* Divide */ + if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { + ret = deposit32(ret, 24, 4, 2); + } else if (arm_feature(env, ARM_FEATURE_THUMB_DIV)) { + ret = deposit32(ret, 24, 4, 1); + } + + return ret; +} + +static void resolve_id_regs(ARMCPU *cpu) +{ + CPUARMState *env = &cpu->env; + uint64_t orig; + + cpu->id_isar0 = resolve_id_isar0(env, orig = cpu->id_isar0); + g_assert_cmphex(cpu->id_isar0, ==, orig); +} + static void arm_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -1003,6 +1047,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) set_feature(env, ARM_FEATURE_VBAR); } + resolve_id_regs(cpu); register_cp_regs_for_features(cpu); arm_cpu_register_gdb_regs_for_features(cpu); From patchwork Sat Sep 15 16:17:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146780 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1938935ljw; Sat, 15 Sep 2018 09:18:22 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaRcFGrKrguY8xP5DNwQrb0ymFjezVuge+3HwWU6ryhMUzYFheKLUogxzsjxSW44ri1UERY X-Received: by 2002:a0c:eac3:: with SMTP id y3-v6mr12253359qvp.89.1537028302717; Sat, 15 Sep 2018 09:18:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028302; cv=none; d=google.com; s=arc-20160816; b=VAaQBTVZQ9dWMw45Vj3bjT3wj9w2m4+MJwxPeYN9T/ZGrL68CvG1sH0kaFVOvYZUP2 FLyo11u7twjYfDoVCacjrfIhI33A8OJSV9VqCafc6YNdlGiiFoPhJkAvORNv9LxDaJss TKxLMFirGKCIqf9uqtQgqvni11zRuw9jd/n2wQhszWrYuhetCw8ABrkGk4GXDONSstVH xt99MrB0BfY7bgLg5FMaEUp9gQUdY7Lp5u86+gm3CuKrv6ppHT6RUqeWQLw7lHGcqyHk gTvYxJcLepWvTmK2k/bvs8SGd2DxCwv74Q68JZjae7Wk1N6ggQiD5dNb/LUdRwfvTqDO oGjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=KmfQb6CgWMOtHBBehbdrq8gACsfnGvLxYEnfidsiT6o=; b=cpBIE7yNgKIRopOejObfPlLeKRIaAnjS65XFYrwpMVsGgqCLC+3LdxHDbNcgAdZi4J 2wRVLEx5DS22HVZ9pv/iXPAddqEwj3RYP/3kNjTKsk1wAc4OY9vlH/dIZNAiiVYVyBKW rGESY6FaLd4FPOL5ZPI32NxFW36tD9kS/BFJCQzhyCGXNwypkoywgzRL3Ti/CNcCq2C5 fN2XAU/mLQvwcxSOyONiOgIvfGACh39u8OrdkvhvYTVYqqlZ6SC1d/k30VVhdptoR8P4 a4rHZnGdLGPFk4OFyzvGHCGKnpvpJqPWWj6c9Ih0ieygD4SSrOKx9Va1B/g5oxCMy5IA LrWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cg0g8gFl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:28 -0700 Message-Id: <20180915161738.25257-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 03/13] target/arm: Derive id_isar1 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? The assertion does fire for quite a lot of cpus, ??? but quite a few of them appear to be existing bugs. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 44483e3dea..a477e722af 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -791,13 +791,48 @@ static uint32_t resolve_id_isar0(CPUARMState *env, uint32_t orig) return ret; } +static uint32_t resolve_id_isar1(CPUARMState *env) +{ + uint32_t ret = 0; + + if (arm_feature(env, ARM_FEATURE_V6)) { + ret = deposit32(ret, 0, 4, 1); /* Endian */ + if (!arm_feature(env, ARM_FEATURE_M)) { + ret = deposit32(ret, 4, 4, 1); /* Except */ + ret = deposit32(ret, 8, 4, 1); /* Except_AR */ + } + /* Extend */ + ret = deposit32(ret, 12, 4, + arm_feature(env, ARM_FEATURE_THUMB_DSP) ? 2 : 1); + } + if (arm_feature(env, ARM_FEATURE_THUMB2)) { + ret = deposit32(ret, 16, 4, 1); /* IfThen */ + ret = deposit32(ret, 20, 4, 1); /* Immediate */ + } + /* Interwork -- note we don't support pre-armv4t. */ + ret = deposit32(ret, 24, 4, + arm_feature(env, ARM_FEATURE_V7) + && !arm_feature(env, ARM_FEATURE_M) ? 3 : + arm_feature(env, ARM_FEATURE_V5) ? 2 : 1); + if (arm_feature(env, ARM_FEATURE_JAZELLE)) { + ret = deposit32(ret, 28, 4, 1); /* Jazelle */ + } + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; uint64_t orig; - cpu->id_isar0 = resolve_id_isar0(env, orig = cpu->id_isar0); + orig = cpu->id_isar0; + cpu->id_isar0 = resolve_id_isar0(env, orig); g_assert_cmphex(cpu->id_isar0, ==, orig); + + orig = cpu->id_isar1; + cpu->id_isar1 = resolve_id_isar1(env); + g_assert_cmphex(cpu->id_isar1, ==, orig); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat Sep 15 16:17:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146783 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1941366ljw; Sat, 15 Sep 2018 09:21:25 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdbr/IOsw46USmw2MOnWdjISyAttDOUjgzZXO9bYwYiilufjggUi9m6ii6aBFM/IrVRLMpgf X-Received: by 2002:aed:3ec5:: with SMTP id o5-v6mr12688477qtf.270.1537028485034; Sat, 15 Sep 2018 09:21:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028485; cv=none; d=google.com; s=arc-20160816; b=I34nb63fBWpdzDeLZsju3UqBBm8g4uxP5NTnOjMSnwxhCCxy72MXeWMkHAsbK880KV xHV1T4uXFhXl1JZ5ra/AEkIuiVaoiAQgDL71l8IDlWUgmq9RwRSbp2yhUTrBBIh0142I EN3yq2k2mYI7W+GSei/hj6ab3UBzO0rsCr/BlSgE+kjPMBEYUhnpeU3JFeTN6F2wSMyk IsSoH69mwr5Y2nyYTnLsGc+94x0VwKR0MgUxkempPSkXkA8SnZhybNROzwyeeo6bLJeM lfPkFVK92/3M0yYOfJBIzl++7URV3cDCDsTDXc9zVjwhE8uRI4+663zgdjTSSkhmqykU w9nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=8tq7ljLEg+ZEL7FdvFxOiLdkjOjupm3VfXgk7BqhQxQ=; b=L0OpUCDcWq9u1/X1IdoIdydQLAg2L2c1CHW1A+hduYgz1+01b3cqc6Yeoa7jao4q2u WjjPcdCbGpWrOiUpUozNmTnNija7jyuZbLZTbuiRhXQRTikcGp1DYNfNADeXHXOgiw8h d15g5eCVAhRxGasTKDbPmTGDA3pgEoxpLOzTWZLx7IEPuOD+J14ZgPWUBawL2g/X9kyC PRhQCanLgpOIiuyhqK48Jx8wqfsTr06uzCqarT+35gJ0M8T1JvS+1OZpB7OqAVd8fEOH GnM2NavRFVcLCXEvhNryX2kqyIwiuWYI7rkmP9x8CFaq7ixERFYXiWcJ2FFPUw83G8Vd v5AQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IMwrJE7w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:29 -0700 Message-Id: <20180915161738.25257-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PATCH 04/13] target/arm: Derive id_isar2 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? The assertion does fire for the old cpus; they may be existing bugs. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a477e722af..379d6a08a4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -821,6 +821,40 @@ static uint32_t resolve_id_isar1(CPUARMState *env) return ret; } +static uint32_t resolve_id_isar2(CPUARMState *env, uint32_t orig) +{ + uint32_t ret = 0; + + /* LoadStore */ + ret = deposit32(ret, 0, 4, + arm_feature(env, ARM_FEATURE_V8) ? 2 : + arm_feature(env, ARM_FEATURE_V5) ? 1 : 0); + /* + * MemHint -- v7mp has pldw (4), v7 has pli (3), but values 1 & 2 + * mean the same thing, and there does not seem to be a way to tell + * them apart for v5 & v6. + */ + ret |= orig & MAKE_64BIT_MASK(4, 4); + /* MultiAccessInt -- micro-architectural detail. */ + ret |= orig & MAKE_64BIT_MASK(8, 4); + /* Mult -- note we don't support pre-armv4t. */ + ret = deposit32(ret, 12, 4, arm_feature(env, ARM_FEATURE_THUMB2) ? 2 : 1); + /* MultS -- note we don't support pre-armv4t. */ + ret = deposit32(ret, 16, 4, + arm_feature(env, ARM_FEATURE_V6) ? 3 : + arm_feature(env, ARM_FEATURE_V5) ? 2 : 1); + /* MultU -- note we don't support pre-armv4t. */ + ret = deposit32(ret, 20, 4, arm_feature(env, ARM_FEATURE_V6) ? 2 : 1); + /* PSR_AR */ + ret = deposit32(ret, 24, 4, arm_feature(env, ARM_FEATURE_M) ? 0 : 1); + /* Reversal */ + ret = deposit32(ret, 28, 4, + arm_feature(env, ARM_FEATURE_THUMB2) ? 2 : + arm_feature(env, ARM_FEATURE_V6) ? 1 : 0); + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -833,6 +867,10 @@ static void resolve_id_regs(ARMCPU *cpu) orig = cpu->id_isar1; cpu->id_isar1 = resolve_id_isar1(env); g_assert_cmphex(cpu->id_isar1, ==, orig); + + orig = cpu->id_isar2; + cpu->id_isar2 = resolve_id_isar2(env, orig); + g_assert_cmphex(cpu->id_isar2, ==, orig); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat Sep 15 16:17:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146782 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1940901ljw; Sat, 15 Sep 2018 09:20:53 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYgKzVEi7Daiqs8f3sbZGAwJArF1EERqk7pdgHbwxP+BohxOgrUniiGzp5+hgEfxdU5Z5dK X-Received: by 2002:ac8:2a78:: with SMTP id l53-v6mr12753046qtl.154.1537028453697; Sat, 15 Sep 2018 09:20:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028453; cv=none; d=google.com; s=arc-20160816; b=X6EzvrcLgATdAZHX01kd14jZFN3R5M8MhHqpkBrNJupTNF6WEnkfkVTsxI9UwlI0R9 pwbsmchra43Vl7H2LRqHKB1qx1r+O8kGxqKK67aCxe7yc3unZp5sixLIznIsH8k71Lkr Y2a/2vSAsmAN0RpOGbPDrCl92+6fS3DZJPht5WoenROefLdhwBWn68X+im+VrE41tlu7 00tbeRfGDcqjU4WZPvC5bKuGaNzfUOEDBbPF+QRDtJsoTcF1rsP4s/G6lYs472romJ+A YXEJFCTJ6QM7CQLfWAjJ2HDZuUTGHFwl+0WlXdlpb+ctKpadLNqWzNq+QgL9bfvH3j1g /rEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=tvi/mbA94iRKAk5mttQm6rCEMmYUp5dXIsY8p9CRUYY=; b=y6unBwSa3cPaIpWO4VrR7R5qAi2jEJ300R/wft8+U4e5wtlbPIxAD6c8KkAdFq3B6W kjUIt2NX9V+5skZutLrhpDd0S+EdSIR69VQEw4BBw0NWPUE2ZgsS2zBd9STfZrsIMAsL 8kn9wXh7TpkebMBvxN/ki+GxCIVQ4wv75f8/A4ElF1U2pSGpL1jYVJof5EqXyZ3n+WAK 9eEb/tnHLjYO7NFjzscdFa62rcorE4Dd/DxBIviY2nyml5AVP++/HiozozVBgoVW4kT7 eOV3CK3BZm5zRexfYCPneDJCbz4FBeriM7yrU+BDxALJZcY0/0JKm9RZ9L4ntt8Jc8lk Nz0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TYY+fSxt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:30 -0700 Message-Id: <20180915161738.25257-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62b Subject: [Qemu-devel] [PATCH 05/13] target/arm: Derive id_isar3 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? The assertion does fire for the old cpus; they may be existing bugs. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 379d6a08a4..2b199845fc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -855,6 +855,38 @@ static uint32_t resolve_id_isar2(CPUARMState *env, uint32_t orig) return ret; } +static uint32_t resolve_id_isar3(CPUARMState *env) +{ + uint32_t ret = 0; + + if (arm_feature(env, ARM_FEATURE_V5)) { + ret = deposit32(ret, 0, 4, 1); /* Saturate */ + } + if (arm_feature(env, ARM_FEATURE_V6)) { + ret = deposit32(ret, 4, 4, 3); /* SIMD */ + } + ret = deposit32(ret, 8, 4, 1); /* SVC -- no pre-armv4t */ + /* SynchPrim */ + if (arm_feature(env, ARM_FEATURE_V6K)) { + ret = deposit32(ret, 12, 4, 2); /* ldrex, ldrexb, ldrexd */ + } else if (arm_feature(env, ARM_FEATURE_V6)) { + ret = deposit32(ret, 12, 4, 1); /* ldrex only */ + } + if (arm_feature(env, ARM_FEATURE_THUMB2)) { + ret = deposit32(ret, 16, 4, 1); /* TabBranch */ + ret = deposit32(ret, 20, 4, 1); /* T32Copy */ + } + if (arm_feature(env, ARM_FEATURE_THUMB2) || + arm_feature(env, ARM_FEATURE_V6K)) { + ret = deposit32(ret, 24, 4, 1); /* TrueNOP */ + } + if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + ret = deposit32(ret, 28, 4, 1); /* T32EE */ + } + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -871,6 +903,10 @@ static void resolve_id_regs(ARMCPU *cpu) orig = cpu->id_isar2; cpu->id_isar2 = resolve_id_isar2(env, orig); g_assert_cmphex(cpu->id_isar2, ==, orig); + + orig = cpu->id_isar3; + cpu->id_isar3 = resolve_id_isar3(env); + g_assert_cmphex(cpu->id_isar3, ==, orig); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat Sep 15 16:17:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146785 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1943206ljw; Sat, 15 Sep 2018 09:23:45 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYlxggDtWdbAO6GxZRMjcmvk16sr94uFBEqHXdW31kucvWdfo7WjVyy7wic9bv5pn0pP1Ku X-Received: by 2002:a0c:da0c:: with SMTP id x12-v6mr12469931qvj.123.1537028625025; Sat, 15 Sep 2018 09:23:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028625; cv=none; d=google.com; s=arc-20160816; b=qTLBEWkJdWeopPbxeKiI9AHhj04jYQFK5ZS+HcY9lJThw0NoNvihHiduxrq3spBkcL fS+EGSeSkuk5Qz+dEWE/OTP3CzuLvmbou2yZFzWa4jxjlJzxUZDOyyuKjOcgahPz9U1s M+qHkty6qjo6YSGumtHx7tiN+yRgfphAwiryy2S/xF3NeT5XluGO8L7fCQm3sK2b3giJ iXNBK3vy5Y1DWLUdHNst0gzrfNAQkXxwd3L8+nE9mB4GI6tijsTSKKIaxqvxOWW8FrdA KacA2XVe52SUw6WjLYQokN0ZLsUUv4/3PVeaIT2yoife+D2mv2HMevXChE4IhI/AD6a9 dQgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=VMUIk1o86kq7ilsu3dulB0Zcq4Bgif0IEpo1hy0Ljxs=; b=S+8k/MEFfdpNKTfL9wQaFjWZSQOeLARCWn/s2xO8sMziEUcueFNU9nFDkTZ/Vm66oA Zj8a3STVwsycFAZI4PnKY4jTL7ivh1zx3lgQozton/GtlaaMtXrdV9m+o+UGSze7TcKm i1FYdoBGdaetmVhBL5KTigH7EcwyBr5OAys/DC42QbQP/AH24/w4YprO5t5be6g8qnoG 8JKCygZVQFt1MOEzL/Tofkcv0ez8pqDGNDopsmPNSZ8lukND5CK+QcspVIHwmY/nX1yz gRLE6/S0g03A75fintouiIu8F/LC2FxhODehCae5wydC2tJeBASxqbZL3kU9WK8hSgGr +PBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EkbN+nuE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:31 -0700 Message-Id: <20180915161738.25257-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62b Subject: [Qemu-devel] [PATCH 06/13] target/arm: Derive id_isar4 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? The assertion does fire for the old cpus; they may be existing bugs. ??? Willfully provide a value for SWP_frac that matches our implementation. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2b199845fc..3c6ddd6532 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -887,6 +887,45 @@ static uint32_t resolve_id_isar3(CPUARMState *env) return ret; } +static uint32_t resolve_id_isar4(CPUARMState *env) +{ + uint32_t ret = 0; + + /* Unpriv -- note we don't support pre-armv4t. */ + ret = deposit32(ret, 0, 4, arm_feature(env, ARM_FEATURE_THUMB2) ? 2 : 1); + /* WithShifts */ + if (!arm_feature(env, ARM_FEATURE_M)) { + ret = deposit32(ret, 4, 4, 4); + } else if (arm_feature(env, ARM_FEATURE_V8)) { + ret = deposit32(ret, 4, 4, 3); + } + ret = deposit32(ret, 8, 4, 1); /* Writeback */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* Note that EL3 indicates Security Extensions. */ + /* ??? In translate.c we check V6K instead. */ + ret = deposit32(ret, 12, 4, 1); /* SMC */ + } + if (arm_feature(env, ARM_FEATURE_V7)) { + ret = deposit32(ret, 16, 4, 1); /* Barrier */ + } + if (!arm_feature(env, ARM_FEATURE_V6K) && + arm_feature(env, ARM_FEATURE_V6)) { + ret = deposit32(ret, 20, 4, 3); /* SyncPrim_frac */ + } + if (arm_feature(env, ARM_FEATURE_M)) { + ret = deposit32(ret, 24, 4, 1); /* PSR_M */ + } + /* + * SWP_frac -- Value 1 indicates that SWP and SWPB only work in a + * uniprocessor context. Looking at ARM_FEATURE_SWP, we will have + * already set ID_ISAR0.Swap to 1, which means that SWP_frac must + * be ignored. While leaving this field 0 may not match certain + * real cpus, it is correct with respect to our implementation. + */ + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -907,6 +946,11 @@ static void resolve_id_regs(ARMCPU *cpu) orig = cpu->id_isar3; cpu->id_isar3 = resolve_id_isar3(env); g_assert_cmphex(cpu->id_isar3, ==, orig); + + orig = cpu->id_isar4; + cpu->id_isar4 = resolve_id_isar4(env); + /* Willfully ignore the SWP_frac field. */ + g_assert_cmphex(cpu->id_isar4 & 0x0fffffff, ==, orig & 0x0fffffff); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat Sep 15 16:17:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146789 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1945326ljw; Sat, 15 Sep 2018 09:26:32 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdbq6pV2jI3DFHr26JvAr2Vhl4FVhq/Komj4DQg6prpo9q3eYMkz0AZXeq2+PHRgLj1mf9/V X-Received: by 2002:a37:6d44:: with SMTP id i65-v6mr12163773qkc.142.1537028792641; Sat, 15 Sep 2018 09:26:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028792; cv=none; d=google.com; s=arc-20160816; b=eqLw8eHRUUherVHqgUwfJCkYkgi40Qhd0Rkto77WSuc1KKz2TGYUPywsV61dlAppky G648v/CTiGpLMD5e9DIkoD7/N1LutMdyqsN2ZsRwg5HsPP5NngKKPklEwYb8S1nc3Aaf HTIyPhyVViCq2wEuj/aenj/mQgx/CqcDZu76a82RQz++DnpZa80nzi5FUzpnPtlA9033 EqOsgNIBauDFY1Bn0ggWMXr8Jxr2giwaZsykxk/n5P1pxofQjrRD7pX5sqgcUwb0/NmL cIYEosH+2J7IlDCZwf9g8HiWvSi3NDO2sx32m28HXTYPvfGVl3Itn/SLaZNYCn/hVcl6 xPQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=b6nRAODSj3A+njpmEvkKG6MZDCxoqpBC7OBUkW09dQw=; b=xd3i0eNXvFMGts+g/AqfrLNrWu5nR/kFLzL1ysuvJkgE3EXgNzGLeiMvkL5ShPXHmW /dELhrYHIzubcZkFWnn3lv6a+kWJnGtiocT9+dk7koUJ9Tn9RMfxKKFyNGTv5nSoZHyA p5UdY/ZrgKLhsnnsRX9LoF6LqvOEm9I0RVLlPDUA/BrkX0rmy/9/VGf1eHY2UJuYOdgv n3mi8f9+tzG2KJKw9+DGkKhX0H4pwhINl+J8htzmlzpVxYZOMwlrpHMHs2swAtJlijnU a602f0dkif7+93cn1b0M2RE9k90105ISNQXvamXFis7DHPh+N2GGemn/8Kb4aXLs/SCN 9low== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Dm91mEnT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:32 -0700 Message-Id: <20180915161738.25257-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 07/13] target/arm: Derive id_isar5 and id_isar6 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unlike the other id_sar registers, these contain post-v8.0 features that are not included with any existing cpu models. They would be enabled by -cpu max when we enable them for system mode. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3c6ddd6532..c227044946 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -926,6 +926,49 @@ static uint32_t resolve_id_isar4(CPUARMState *env) return ret; } +static uint32_t resolve_id_isar5(CPUARMState *env) +{ + uint32_t ret = 0; + + /* SEVL -- we always implement as NOP. */ + /* AES */ + if (arm_feature(env, ARM_FEATURE_V8_PMULL)) { + ret = deposit32(ret, 4, 4, 2); + } else if (arm_feature(env, ARM_FEATURE_V8_AES)) { + ret = deposit32(ret, 4, 4, 1); + } + if (arm_feature(env, ARM_FEATURE_V8_SHA1)) { + ret = deposit32(ret, 8, 4, 1); /* SHA1 */ + } + if (arm_feature(env, ARM_FEATURE_V8_SHA256)) { + ret = deposit32(ret, 12, 4, 1); /* SHA2 */ + } + if (arm_feature(env, ARM_FEATURE_CRC)) { + ret = deposit32(ret, 16, 4, 1); /* CRC32 */ + } + if (arm_feature(env, ARM_FEATURE_V8_RDM)) { + ret = deposit32(ret, 24, 4, 1); /* RDM */ + } + if (arm_feature(env, ARM_FEATURE_V8_FCMA)) { + ret = deposit32(ret, 28, 4, 1); /* VCMA */ + } + + return ret; +} + +static uint32_t resolve_id_isar6(CPUARMState *env) +{ + uint32_t ret = 0; + + /* JSCVT -- not implemented yet */ + /* FHM -- not implemented yet */ + if (arm_feature(env, ARM_FEATURE_V8_DOTPROD)) { + ret = deposit32(ret, 4, 4, 1); /* DP */ + } + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -951,6 +994,9 @@ static void resolve_id_regs(ARMCPU *cpu) cpu->id_isar4 = resolve_id_isar4(env); /* Willfully ignore the SWP_frac field. */ g_assert_cmphex(cpu->id_isar4 & 0x0fffffff, ==, orig & 0x0fffffff); + + cpu->id_isar5 = resolve_id_isar5(env); + cpu->id_isar6 = resolve_id_isar6(env); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat Sep 15 16:17:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146786 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1943263ljw; Sat, 15 Sep 2018 09:23:50 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZ2XtSIzJXBurGgM3lp0VopNzquuYxapmcuc/sI8b9XygO1b6bKdZmwz8afuxasd68KLm4P X-Received: by 2002:a37:6292:: with SMTP id w140-v6mr12285691qkb.258.1537028630513; Sat, 15 Sep 2018 09:23:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028630; cv=none; d=google.com; s=arc-20160816; b=ciiuaEuirURPFPiCRZcWzQKDdgR4Gxih+zFW9X0VyJU4jXuc3gcqrk1HwMMBAyTkhY Z1cmZLEEeZDti9SzvJGawz0D8GDZid4YvThYCumXO9oH4/E6reaMfgMYs8rJYGEZMSzW rcRbJsXCUsPx41rCCkwltSYSXFifC8es3M4NFBbyBwLVl+g3PoK62I9kYS8LfSfPLAud fp5p8sq4xv++1UADLIDaUyzh8pZvEgKoRaBDvby1AxdDfYhaF3jOIc3GjgP4mkw5vKQr mhqRnzKbh2EW2WcqaBrkAn6p6q+nV3lGULcjrAy4NSE7qljrYy5oPXh9Xa0oxZS49wUj MhLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=k+TNqtjUjOGSK55CCIwBJa0g8BPa9U7tdVQTrJqAV3A=; b=0BKbT5V82II6DqJEWhlINXf5bT10yJNuKZRhdDjJBugLEg7jZJkeZzqMuud+oGrjmJ eKdJeCHP14f0cbaRsSYDbcJX8jl2sOUjjcpu3QCGn57wvb95UiB1JLUMCYt+f7nXmL6k fHfJ4vQA1ihFrak/VYTt7ldh1TsReENp0UudWKc054IFsaVhhMK0TyMrLOxLCQX088Ng 9p1zXfRRodODxagb2HF/Jv4gd5iy8va/HZemXWdwjlHlRsOn7Ku31PfbyQobcp5KkNj9 1o7dxtXEJHw0ef1ZnGKo+kSXjBpeU6zrD5GTNIyi6ojqm8XSUJ9a/80ojuM9WldfjJKg ONdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cFBRopNE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:33 -0700 Message-Id: <20180915161738.25257-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62c Subject: [Qemu-devel] [PATCH 08/13] target/arm: Derive id_pfr0 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? The assertion does fire for old cpus; they may be existing bugs. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c227044946..0151c278e8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -969,6 +969,29 @@ static uint32_t resolve_id_isar6(CPUARMState *env) return ret; } +static uint32_t resolve_id_pfr0(CPUARMState *env) +{ + uint32_t ret = 0; + + if (!arm_feature(env, ARM_FEATURE_M)) { + ret = deposit32(ret, 0, 4, 1); /* State0 -- A32 */ + } + if (arm_feature(env, ARM_FEATURE_THUMB2)) { + ret = deposit32(ret, 4, 4, 3); /* State1 -- T32 */ + } else if (arm_feature(env, ARM_FEATURE_V5)) { + ret = deposit32(ret, 4, 4, 1); /* State1 -- bl/blx only */ + } + if (arm_feature(env, ARM_FEATURE_JAZELLE)) { + ret = deposit32(ret, 8, 4, 1); /* State2 -- Jazelle */ + } + if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + ret = deposit32(ret, 12, 4, 1); /* State3 -- T32EE */ + } + /* RAS -- not implemented yet */ + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -997,6 +1020,10 @@ static void resolve_id_regs(ARMCPU *cpu) cpu->id_isar5 = resolve_id_isar5(env); cpu->id_isar6 = resolve_id_isar6(env); + + orig = cpu->id_pfr0; + cpu->id_pfr0 = resolve_id_pfr0(env); + g_assert_cmphex(cpu->id_pfr0, ==, orig); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat Sep 15 16:17:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146787 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1943500ljw; Sat, 15 Sep 2018 09:24:08 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZvLUhPfP6FkzmoY8ab7/EaLc6yj3ADjEvSfDILljI53BA73uEP+QcqHM1Y66kbus0LaX2x X-Received: by 2002:a0c:c78c:: with SMTP id k12-v6mr12068464qvj.99.1537028648154; Sat, 15 Sep 2018 09:24:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028648; cv=none; d=google.com; s=arc-20160816; b=kOXRdS/xiNKDnffnuyFPzTsilFihMQII2JRY22mftDPaX3v/6faEdH3mK4Z6ZU3eAG qx55fW3kZViKqia+joeaRTLPyQXjb4qVv6OBBwqSre9q65k7p7m+p4AT240IBDVZt7RV 6dJUzIbL2DPlQ5+O93grhsFoz4leeQoQzUMipD/S1nX+Gg/hZAycprfgWdAe5zT8+jxn HWw4lZmGUBSD8mRZqQk9PPJ/+7+F4FSqkb2TML3hHKnkGJEECdjboYpp0gtTzhjbbZbT r4/K7YwiHxMGHZd4zaiGlyxqyIUm80YffuWkF5HZQH60DsmvhaOXQvYSr/dz4/uc6hMI qcXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=pLO73eoAwsD8yr0Blf5mlHEU8DCO0XukLLz4TVq1v2U=; b=dldLMsPNGH8v61ge3nQC0BxiRlx+6nDukvgnKK1m01LnMX5yD5DpvkkDKtJnmkYeWM xbxoORMrvVNnobWFdX1CPYaRBZWuoTUvgKDXwQhcZqmwB2RzJKtzLJvjwQeCVBUIEeNW L1jEnFr0Y+sH/LZMVnicxTlMKW5Jzr/S0oPT1yrOIllTCEx4bkjygsoP6QrYbyPII0xg 2/EYVNFJj3AE2lmGI5jZgI34cQXISyLsl3ZoC4wdKBM3/ea9DuMmX2MSvIlDohZ3m++y JW6F3sde8+jNdjYZSqbiHJn4y+yVG0DPpA9EKCUADw/iEz+zBRKE9Q/GM8X/4AlJX6/z czEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=D8s2gGdD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:34 -0700 Message-Id: <20180915161738.25257-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PATCH 09/13] target/arm: Derive id_pfr1 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0151c278e8..4fb3e0a9ea 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -992,6 +992,31 @@ static uint32_t resolve_id_pfr0(CPUARMState *env) return ret; } +static uint32_t resolve_id_pfr1(CPUARMState *env) +{ + uint32_t ret = 0; + + if (arm_feature(env, ARM_FEATURE_M)) { + ret = deposit32(ret, 8, 4, 2); /* MProgMod */ + } else { + ret = deposit32(ret, 0, 4, 1); /* ProgMod */ + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + ret = deposit32(ret, 4, 4, 1); /* Security */ + } + if (arm_feature(env, ARM_FEATURE_EL2)) { + ret = deposit32(ret, 12, 4, 1); /* Virtualization */ + } + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { + ret = deposit32(ret, 16, 4, 1); /* GenTimer */ + } + /* Sec_frac -- no partial features implemented without EL3 */ + /* Virt_frac -- no partial features implemented without EL2 */ + /* GIC -- info not available yet; filled in by id_pfr1_read */ + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -1024,6 +1049,10 @@ static void resolve_id_regs(ARMCPU *cpu) orig = cpu->id_pfr0; cpu->id_pfr0 = resolve_id_pfr0(env); g_assert_cmphex(cpu->id_pfr0, ==, orig); + + orig = cpu->id_pfr1; + cpu->id_pfr1 = resolve_id_pfr1(env); + g_assert_cmphex(cpu->id_pfr1, ==, orig); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat Sep 15 16:17:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146791 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1945606ljw; Sat, 15 Sep 2018 09:26:54 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZBtc/enuALbx5lXAtyBx28J8gPPwnhAmHsLjAngraFGkB8F8zjRbZ/tkjAijKtGNdZOOG6 X-Received: by 2002:a37:b12:: with SMTP id 18-v6mr12351726qkl.167.1537028814664; Sat, 15 Sep 2018 09:26:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028814; cv=none; d=google.com; s=arc-20160816; b=UgG60n4AbjlE1GZD+ZKMTHP6MgtGNPJUYU0uOoQ22i2RiyMSPxKLY4l2pjnODqLH96 iDgSjV0HoGE2DPBx+cFqOzveT9sWeZW5AdFwzYfX8UdYhb/LqiY2/xRwrdrSc5SiTWxa xQ77bAktOYE8gveBkL3IyAy07AwMIX+IvRHkMGvPXNvv4MSlVNUfxirmVFqjBhYqQNVZ UvF2lI7zsQzjoHszGTiQiM0PpUGkd8wwLqJQItwzK/Rt5z6yXrUZJBnjngguIOQkjAER YbGzDiYXPtp/kHpACN0qfvnhW4njceMVzjF2JulWwXrjub2LCZ3ZVBCU7oTqAMNDGAyk lYhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=jgmkTEluYq/Qp7SO+CS3JMwIujLwX/BOHR5l9U0Ukbw=; b=bg32EjqzWuHLMvfQg2pBvjYFRTP5ZAOGzrCcNKrYPWrWTOcXLTcnQQmfS49Mid6WNM qX1QG5TAdpiiA7nA0gkVwwFyYpgsYZrngWqd0FbOQw5hPbAAsvezSZoPm2g87fjb8war 2awB0yC0bmq7/c55L1MvmA8xObwCF/t0pOj984hAxturxG+fxcpXjlpQZgOBIqOPytbr +PIr5YCPvkM0ezEb2oL01cMvGmfthD1KPDZMVzQAYEhSe6LN4pQVslqlpZaFP1YdAYPS CzOXqYwxoANfdPh3WWh2F2YcJtkig/LpvUzWSDmpzd3scX7ib1wnQsRc6RqRGUOkIbNb HqQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ary9sSbH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:35 -0700 Message-Id: <20180915161738.25257-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::433 Subject: [Qemu-devel] [PATCH 10/13] target/arm: Derive id_aa64isar0 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4fb3e0a9ea..1c51b9f631 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1017,6 +1017,51 @@ static uint32_t resolve_id_pfr1(CPUARMState *env) return ret; } +static uint64_t resolve_id_aa64isar0(CPUARMState *env) +{ + uint64_t ret = 0; + + /* AES */ + if (arm_feature(env, ARM_FEATURE_V8_PMULL)) { + ret = deposit64(ret, 4, 4, 2); + } else if (arm_feature(env, ARM_FEATURE_V8_AES)) { + ret = deposit64(ret, 4, 4, 1); + } + if (arm_feature(env, ARM_FEATURE_V8_SHA1)) { + ret = deposit64(ret, 8, 4, 1); /* SHA1 */ + } + /* SHA2 */ + if (arm_feature(env, ARM_FEATURE_V8_SHA512)) { + ret = deposit64(ret, 12, 4, 2); + } else if (arm_feature(env, ARM_FEATURE_V8_SHA256)) { + ret = deposit64(ret, 12, 4, 1); + } + if (arm_feature(env, ARM_FEATURE_CRC)) { + ret = deposit64(ret, 16, 4, 1); /* CRC32 */ + } + if (arm_feature(env, ARM_FEATURE_V8_ATOMICS)) { + ret = deposit64(ret, 20, 4, 2); /* Atomic */ + } + if (arm_feature(env, ARM_FEATURE_V8_RDM)) { + ret = deposit64(ret, 28, 4, 1); /* RDM */ + } + if (arm_feature(env, ARM_FEATURE_V8_SHA3)) { + ret = deposit64(ret, 32, 4, 1); /* SHA3 */ + } + if (arm_feature(env, ARM_FEATURE_V8_SM3)) { + ret = deposit64(ret, 36, 4, 1); /* SM3 */ + } + if (arm_feature(env, ARM_FEATURE_V8_SM4)) { + ret = deposit64(ret, 40, 4, 1); /* SM4 */ + } + if (arm_feature(env, ARM_FEATURE_V8_DOTPROD)) { + ret = deposit64(ret, 44, 4, 1); /* DP */ + } + /* FHM -- not implemented yet */ + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -1053,6 +1098,10 @@ static void resolve_id_regs(ARMCPU *cpu) orig = cpu->id_pfr1; cpu->id_pfr1 = resolve_id_pfr1(env); g_assert_cmphex(cpu->id_pfr1, ==, orig); + + orig = cpu->id_aa64isar0; + cpu->id_aa64isar0 = resolve_id_aa64isar0(env); + g_assert_cmphex(cpu->id_aa64isar0, ==, orig); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat Sep 15 16:17:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146790 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1945338ljw; Sat, 15 Sep 2018 09:26:33 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZe/aF90HgciIHFbTz36S3RgS7ht9rI7Qz38vxIN58t8C6DAow+nGpO4o89tcRQgDGdzCg9 X-Received: by 2002:a37:b446:: with SMTP id d67-v6mr12144609qkf.104.1537028793851; Sat, 15 Sep 2018 09:26:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028793; cv=none; d=google.com; s=arc-20160816; b=VH21hfXpXsw8sVX5YjfpvhSGJ2glJ5reM71xqew2CRMbqQL+PDKghSNDZQWyqcxork 84PLC8MKsM3O2K+DrxLqPYAj5GEhSGYAjNjvNZpSTmeVja07nflupFeBQTB5RLKn7XBK DCiIf7H8ldZCnk1aaa+CGipyx4EAR9KeZ9n+2IRnb9ZLY1OOMLEZWWP8A+PjdsPqiNnv ziyw1R0/CafqIi42uzBdNoyfFw2iV45TjToBW+mYkW3qy8J+h9Bq/ZtCOnC+hSFqFUw/ CoDbYgreyYx2sD9gAgz+XnCcPn1C+A6mNBvXvrBAYf97egvvW3VmFHRzCFHeuMz/cm0u II+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=SHjTofhC/zwswvOaMPM1hKLJnu4qclwgjX/edGpstDc=; b=zXu2IS9Mv3WmyI/izqKexwU9RDRMdiNp4OlwoS+m5FjDp5NhVECT7GWyyOXw6ZOWnd 18Gsi2naXzf1EIZHPfPK8PJxu32v1TZtILQUe1I/jVU9RB4Ibol2MbeJb1lxkbNcDl6i 0jxP/rcKUGuHbgSpdTBpCuCebF5lGVq49l53keSxM3NnNRzHzCe8JsRWtslreh6WqN0M 5Jfogzbc30bkNXvgazv6JVCgaQjjQZhOYseNo+rQlzd9FNV7qaL+YBV8bDbQc9rqqr6F 2j1mZILd8EhJydEyeK29SJdE71K79Co70Np6XQVZpnwaD0gEqd0fU+rma8+H8Rmn3bpP 7/Yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jNmnuajw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:36 -0700 Message-Id: <20180915161738.25257-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52f Subject: [Qemu-devel] [PATCH 11/13] target/arm: Derive id_aa64isar1 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1c51b9f631..a9724f3bb1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1062,6 +1062,24 @@ static uint64_t resolve_id_aa64isar0(CPUARMState *env) return ret; } +static uint64_t resolve_id_aa64isar1(CPUARMState *env) +{ + uint64_t ret = 0; + + /* DPB -- not implemented yet */ + /* APA -- not implemented yet */ + /* API -- not implemented yet */ + /* JSCVT -- not implemented yet */ + if (arm_feature(env, ARM_FEATURE_V8_FCMA)) { + ret = deposit64(ret, 16, 4, 1); + } + /* LRCPC -- not implemented yet */ + /* GPA -- not implemented yet */ + /* GPI -- not implemented yet */ + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -1102,6 +1120,8 @@ static void resolve_id_regs(ARMCPU *cpu) orig = cpu->id_aa64isar0; cpu->id_aa64isar0 = resolve_id_aa64isar0(env); g_assert_cmphex(cpu->id_aa64isar0, ==, orig); + + cpu->id_aa64isar1 = resolve_id_aa64isar1(env); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat Sep 15 16:17:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146792 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1947009ljw; Sat, 15 Sep 2018 09:28:44 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZ87n+3JHBR7q2dkrR2GCw/mLayh9fo9+Kb3y+/eun9teLZ1foCqQiGefgmwUqaf31LMpQl X-Received: by 2002:a37:9f0c:: with SMTP id i12-v6mr12461861qke.122.1537028924842; Sat, 15 Sep 2018 09:28:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028924; cv=none; d=google.com; s=arc-20160816; b=v4/WgPGt5J1Z1SWey7OtiHG9YdsIQRVCd6Lv44uxleTu5/sV+1Jl3xWXCxd8VetczP BWYqJaexh75yZ5UwOSkKRonRkgouxDQnzJb4T4xsbwhXyYFoDN4HgMKF2JH8fSAJ0AjI +sE7ywSgnog2RvSfZJm0AmD5qKyI/9iCjJlHSl6BotkSSyMIB7U4HJWywyuyCmOtBoQ1 AdZ0sN8iIRU9kWLe7oER4EdHOSHlG3+t1M55Ov/bcEAryfASM/1vHZiWfjgfGHnluiPc VgPM8gTft3AHw4wbgqG5soyRfDLCeDO/dEaFQcWwuJz4bPb98/87lLMhSyvtVFnHGCYl DMoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=QMWvxDHtEK366CXihsxXzYlxa+9KZq9t/nbEwvVlLXc=; b=qf4/wormt7F0g+IDqdcLCoPKaJwa2gjXIKI6ZSBgX0t2bg0HBcazxZD6V6ZG1mzkyS xWkz2x3jAqkNc25WgpFLdTJy32+OND6CFSFR0iybUrsuESTIkThXPxzhsHb4dmKnlZi6 b/as3xuFidp/FYM1LmW+Ct9Px4W6dLMaZEuF6IngxNjH+In0SY3WoJ89jKWe1VVTDHah Si+eOoVqmM+NRIiPKdv4O8LeoE21qScRlc4LnS1iIsZ3GH3RDbhT1DW+4jChpAPvOS0w O8e0xa7tFtaZOPv87IBr6xP89K7595bOYmJppcZhedsO4ieicdJacDjhmpuFmyvngD0J m8JA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PgVppPpp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:37 -0700 Message-Id: <20180915161738.25257-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::534 Subject: [Qemu-devel] [PATCH 12/13] target/arm: Derive id_aa64pfr0 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a9724f3bb1..2ec71104c9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1080,6 +1080,31 @@ static uint64_t resolve_id_aa64isar1(CPUARMState *env) return ret; } +static uint64_t resolve_id_aa64pfr0(CPUARMState *env) +{ + uint64_t ret = 0; + + ret = deposit64(ret, 0, 4, 2); /* EL0 */ + ret = deposit64(ret, 4, 4, 2); /* EL1 */ + if (arm_feature(env, ARM_FEATURE_EL2)) { + ret = deposit64(ret, 8, 4, 2); /* EL2 */ + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + ret = deposit64(ret, 12, 4, 2); /* EL3 */ + } + if (arm_feature(env, ARM_FEATURE_V8_FP16)) { + ret = deposit64(ret, 16, 4, 1); /* FP */ + ret = deposit64(ret, 20, 4, 1); /* AdvSIMD */ + } + /* GIC -- info not available yet; filled in by id_aa64pfr0_read */ + /* RAS -- not implemented yet */ + if (arm_feature(env, ARM_FEATURE_SVE)) { + ret = deposit64(ret, 32, 4, 1); /* SVE */ + } + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -1122,6 +1147,10 @@ static void resolve_id_regs(ARMCPU *cpu) g_assert_cmphex(cpu->id_aa64isar0, ==, orig); cpu->id_aa64isar1 = resolve_id_aa64isar1(env); + + orig = cpu->id_aa64pfr0; + cpu->id_aa64pfr0 = resolve_id_aa64pfr0(env); + g_assert_cmphex(cpu->id_aa64pfr0, ==, orig); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat Sep 15 16:17:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 146788 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1943649ljw; Sat, 15 Sep 2018 09:24:18 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYqwJuqypII86kUcMwneZZ8uTnWyE5gILM48N+kM10GftoRm/y+2XA8tYTB7M6tC0D4qUB4 X-Received: by 2002:a37:1968:: with SMTP id k101-v6mr12031220qkh.270.1537028658902; Sat, 15 Sep 2018 09:24:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537028658; cv=none; d=google.com; s=arc-20160816; b=BVxFq7snPmE4v8mI3cOxVYE7jKQxAFp/GeZML4lINViLzenNlXSzodIVQcZCZ92xyG zvEvLij0Q/4aFpfFzGneTL1b5ooITKy+Ae2ug0/EWX2/NVSaDOOCi1FugjtidYtgZmsK GdCGsT+QiJy+1B8P5W6MPuSxMcwafFXLWkTjU34evgpXlm5PUPlDGUcDe0C7j8KsrpEN tcyCPRsUp8Fo37M2EIoiH5rOzbcUepmd78bqbS9s6CX1ylX/8rFkdCMFh4UQzhXdIbyk 0BVRTlSaQRd7QAgrHTyK6DvtV4vWSB5K03O8pTJYFW1oegXvdL8r0TRxMRRQ5Pu2tqPV fPLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=X4EBL1pJUwLy43RkKPhPWRfdseJ9dJR7+HfbclZf6GE=; b=sNt+wEay6b5yFyyUbakwywdVwrNw/54DdfIT78HG4WTLwqmNpLjqGV+1aTH3J7p1lz NhM8UdARXEcq71u6nuwGzCc6Z4p4UZKfi3CoNmLnaKTGaRvqckJ/aa6IFNX/j7ctMFkX DPWQ7qZtYoxZxqHEBqkHFjLBMsVtXlNgdLaBVllN0E+Q/EtIb7PMdoqPP8sW/ZZyCt1l wdkpvvAVsatMBjhu9nzBoEMNgTyWGaTaSFI3j/5VCERcV9shzlLpefaGnjdFNELPqHYY +Elr2QIc8J1dUAuXj4FqGbfF8HdnD1nLAvokBYxk7g3QkPKjsmge+6cKAEkiDxKA7H2i YXZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fY+nUk7e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:38 -0700 Message-Id: <20180915161738.25257-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 13/13] target/arm: Remove assertions from resolve_id_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a prerequisite to removing the now-redundant initializations from within the individual cpus. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 41 +++++++---------------------------------- 1 file changed, 7 insertions(+), 34 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2ec71104c9..79103926a4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1108,49 +1108,22 @@ static uint64_t resolve_id_aa64pfr0(CPUARMState *env) static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; - uint64_t orig; - orig = cpu->id_isar0; - cpu->id_isar0 = resolve_id_isar0(env, orig); - g_assert_cmphex(cpu->id_isar0, ==, orig); - - orig = cpu->id_isar1; + cpu->id_isar0 = resolve_id_isar0(env, cpu->id_isar0); cpu->id_isar1 = resolve_id_isar1(env); - g_assert_cmphex(cpu->id_isar1, ==, orig); - - orig = cpu->id_isar2; - cpu->id_isar2 = resolve_id_isar2(env, orig); - g_assert_cmphex(cpu->id_isar2, ==, orig); - - orig = cpu->id_isar3; + cpu->id_isar2 = resolve_id_isar2(env, cpu->id_isar2); cpu->id_isar3 = resolve_id_isar3(env); - g_assert_cmphex(cpu->id_isar3, ==, orig); - - orig = cpu->id_isar4; cpu->id_isar4 = resolve_id_isar4(env); - /* Willfully ignore the SWP_frac field. */ - g_assert_cmphex(cpu->id_isar4 & 0x0fffffff, ==, orig & 0x0fffffff); - cpu->id_isar5 = resolve_id_isar5(env); cpu->id_isar6 = resolve_id_isar6(env); - - orig = cpu->id_pfr0; cpu->id_pfr0 = resolve_id_pfr0(env); - g_assert_cmphex(cpu->id_pfr0, ==, orig); - - orig = cpu->id_pfr1; cpu->id_pfr1 = resolve_id_pfr1(env); - g_assert_cmphex(cpu->id_pfr1, ==, orig); - orig = cpu->id_aa64isar0; - cpu->id_aa64isar0 = resolve_id_aa64isar0(env); - g_assert_cmphex(cpu->id_aa64isar0, ==, orig); - - cpu->id_aa64isar1 = resolve_id_aa64isar1(env); - - orig = cpu->id_aa64pfr0; - cpu->id_aa64pfr0 = resolve_id_aa64pfr0(env); - g_assert_cmphex(cpu->id_aa64pfr0, ==, orig); + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + cpu->id_aa64isar0 = resolve_id_aa64isar0(env); + cpu->id_aa64isar1 = resolve_id_aa64isar1(env); + cpu->id_aa64pfr0 = resolve_id_aa64pfr0(env); + } } static void arm_cpu_realizefn(DeviceState *dev, Error **errp)