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[81.169.180.215]) by mx.google.com with ESMTP id c1-v6si112213edn.411.2018.09.19.15.58.59; Wed, 19 Sep 2018 15:58:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EiXLzyF0; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 76070C21DCA; Wed, 19 Sep 2018 22:58:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E794EC21E1E; Wed, 19 Sep 2018 22:58:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6E561C21C93; Wed, 19 Sep 2018 22:58:19 +0000 (UTC) Received: from mail-it0-f68.google.com (mail-it0-f68.google.com [209.85.214.68]) by lists.denx.de (Postfix) with ESMTPS id B539EC21C2C for ; Wed, 19 Sep 2018 22:58:18 +0000 (UTC) Received: by mail-it0-f68.google.com with SMTP id f14-v6so10639984ita.4 for ; Wed, 19 Sep 2018 15:58:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yVc43a1lgOiM2RGHAKWp1w9uzNFTNrVECOHqjQK2sso=; b=EiXLzyF0HJp0/fz5Kxr/SruGzIuYiMr5fbzsnUDZViQP/QP3IEKRmXbDHqv3FSAOfw Ae4anh5pfTnnviNFLUGbTfh2kyGDSLrr/4wt/A7vMkVFCm1okJnY5RsuiSVNGRdahKWg dVziZ+53H4bjO5OdQZPBaroha3tEAi/N8Zr3w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yVc43a1lgOiM2RGHAKWp1w9uzNFTNrVECOHqjQK2sso=; b=EaH6V97NS3sSK4YKPakOPIwreIZmy0V2fnPK76FxIgtzl9TSVc+fvGe87rHi85OcQ0 +6HZS1VYkWfkk/B6BsWZkBdJT4TvDdCHXvzyZNUF7fhcVUWEX+CI2LIrMAPq0paC/2lI kklbfGOzKBhvNGpLZdb06VbkLBjWdZXBQGzo/bPdk1g9bIt0e9zF40BScwQrWyPLbIVI kkHfpboqbs3Ts/Uc9kusAA2BHqewCHa5O0YcqCkowhlcUfSsxGmSQU8dRa5sLHBL2z2V JsFhPx9wnA8Anfyhd05w0mFqNGY3cqrAnToZd47l+/jASRHDpIc6yqxzMv6fEW92u2T+ giCQ== X-Gm-Message-State: APzg51BJrV5+jSUnhV9HQ+7hT5lBLEezaYhsbXNbvEZVB2Ys2Fdgy2cd oxGHY1QPQlAVkMrpTnpx1iws X-Received: by 2002:a24:118f:: with SMTP id 137-v6mr138458itf.30.1537397897194; Wed, 19 Sep 2018 15:58:17 -0700 (PDT) Received: from localhost.localdomain ([209.82.80.116]) by smtp.gmail.com with ESMTPSA id a63-v6sm52951itc.38.2018.09.19.15.58.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Sep 2018 15:58:16 -0700 (PDT) From: Manivannan Sadhasivam To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Wed, 19 Sep 2018 15:58:01 -0700 Message-Id: <20180919225804.14375-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180919225804.14375-1-manivannan.sadhasivam@linaro.org> References: <20180919225804.14375-1-manivannan.sadhasivam@linaro.org> Cc: tom@vamrs.com, Randy Li , amit.kucheria@linaro.org, dev@vamrs.com, u-boot@lists.denx.de, Manivannan Sadhasivam , stephen@vamrs.com Subject: [U-Boot] [PATCH 1/4] arm: dts: rockchip: add some common pin-settings to rk3399 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Randy Li Those pins would be used by many boards. Commit grabbed from Linux: commit b41023282d07b61a53e2c9b9508912b1e7ce7b4f Author: Randy Li Date: Thu Jun 21 21:32:10 2018 +0800 arm64: dts: rockchip: add some common pin-settings to rk3399 Those pins would be used by many boards. Signed-off-by: Randy Li Signed-off-by: Heiko Stuebner Acked-by: Philipp Tomsich Signed-off-by: Randy Li Signed-off-by: Heiko Stuebner Signed-off-by: Ezequiel Garcia --- arch/arm/dts/rk3399.dtsi | 55 +++++++++++++++++++++++++++++++++++----- 1 file changed, 49 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 83c257b1228..8349451b03d 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -1602,19 +1602,49 @@ drive-strength = <12>; }; + pcfg_pull_none_13ma: pcfg-pull-none-13ma { + bias-disable; + drive-strength = <13>; + }; + + pcfg_pull_none_18ma: pcfg-pull-none-18ma { + bias-disable; + drive-strength = <18>; + }; + + pcfg_pull_none_20ma: pcfg-pull-none-20ma { + bias-disable; + drive-strength = <20>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + pcfg_pull_up_8ma: pcfg-pull-up-8ma { bias-pull-up; drive-strength = <8>; }; + pcfg_pull_up_18ma: pcfg-pull-up-18ma { + bias-pull-up; + drive-strength = <18>; + }; + + pcfg_pull_up_20ma: pcfg-pull-up-20ma { + bias-pull-up; + drive-strength = <20>; + }; + pcfg_pull_down_4ma: pcfg-pull-down-4ma { bias-pull-down; drive-strength = <4>; }; - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; + pcfg_pull_down_8ma: pcfg-pull-down-8ma { + bias-pull-down; + drive-strength = <8>; }; pcfg_pull_down_12ma: pcfg-pull-down-12ma { @@ -1622,9 +1652,22 @@ drive-strength = <12>; }; - pcfg_pull_none_13ma: pcfg-pull-none-13ma { - bias-disable; - drive-strength = <13>; + pcfg_pull_down_18ma: pcfg-pull-down-18ma { + bias-pull-down; + drive-strength = <18>; + }; + + pcfg_pull_down_20ma: pcfg-pull-down-20ma { + bias-pull-down; + drive-strength = <20>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; }; clock { From patchwork Wed Sep 19 22:58:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 147066 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1261986ljw; Wed, 19 Sep 2018 16:00:28 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZ2/I1TgSnvgVyBK7SUeOtfdD1WoxuNd+/b38INYfDmEn1aZZobCT/PSqGcYTMHwlgnN9di X-Received: by 2002:a50:af03:: with SMTP id g3-v6mr215515edd.220.1537398027977; Wed, 19 Sep 2018 16:00:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537398027; cv=none; d=google.com; s=arc-20160816; b=lPOd11NNTyoRCYhGpsOOvVD9n0IDnPj9kgPEcLYrSpQh7KRbyMCsYnYU+E1eZJbCBF eCWdZaSBXK57y+vUb4z0+skjo7Xzrl9+oDovZ5461hswxIk1IcsFGrW9dkrLSdCKYqvg IkIuzv+o6+Jy1RCNebkJuYh3EMzf9U/3VmeFZPMHAGRyv4F3UDt53fvgKKPbVbGa3sBa gS7qkBp69hfTGe9KSPPDAqAx+n3L//fxSSK6hJpFT+r4znj1HpFu93+4hA0lN5EdfrhN vvYllCx4+C4Av4aDd+5Adt68EJL0uMJj0bWT0rW7rxTZimWOHt5BQ4XMH38B38JrF6ei gJLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=xA4t7lq+tWDST7rYqDc7kMuSw65hMwpHX80VWNsM2lM=; b=CfnRtDdlz9CHVShd0GjKir7adv/kUudNHoe7vdmi9Uw8Ugvj0pVXSxjmNGjYD5l5Mo P6Oqbmu/+oMf31ugEMDEEvO3skfxu8RZAoXAXFk62A5MRWlUX+4cbDUTj+p0ES9c6Z1K QI6aAh5aw9lmLGAtdrQG4fhuhuJ47qKK5VJ3zSVL68u7lEeicyj8+y8Cxc5hKN7e459c ilY37fcnheuIo/a9LvYT5xSBc/pqjmSyYPf1peW4LoFyFniAYfz2K70lk06fsG6YMf5g W645fw6Kwq9Cctux4DamKyp4Zsp7iHlN3yi39UDlIXNLI9Tc+eZtKwtSLIoXcrOMbeaj DjbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PiUXnVCD; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id m17-v6si107320edm.387.2018.09.19.16.00.27; Wed, 19 Sep 2018 16:00:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PiUXnVCD; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 951D2C21E74; Wed, 19 Sep 2018 22:59:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=LOTS_OF_MONEY, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 074B6C21E45; Wed, 19 Sep 2018 22:58:35 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7CE14C21CB6; Wed, 19 Sep 2018 22:58:24 +0000 (UTC) Received: from mail-io1-f68.google.com (mail-io1-f68.google.com [209.85.166.68]) by lists.denx.de (Postfix) with ESMTPS id 873CCC21DA2 for ; Wed, 19 Sep 2018 22:58:20 +0000 (UTC) Received: by mail-io1-f68.google.com with SMTP id l14-v6so5865722iob.7 for ; Wed, 19 Sep 2018 15:58:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oGj973POmiqDWs0KODlc+z+ZyZOggiaqHfc3Ce6ljcE=; b=PiUXnVCDOd5XAkEI6mMBijXlc5Sf+F533NmhdbAV8oEjTydijIIwjgvvJdtSLzfQtf w8kaDwZt/H7kQkY/L81MOaV+JrQN9egZycpVOsHoX8SlfufzhQwUruU8nogPNZWw0jAe ZtxQkLU+/SotXOuzgkAFQ/PwgrmyynuPHyf80= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oGj973POmiqDWs0KODlc+z+ZyZOggiaqHfc3Ce6ljcE=; b=mPuFQKTKOeto/A5aLu31NVHPydiukedF5L0QJSZYrqvBIrFwzNqsMJfLycBLOAgTSm iI2Gc/BaGTsPjCBXFasCJeshKcR0nG71KUj9jtiCvjOXJ+B882tdwBO96AOUmGjvHthu qOUp3OAcqI/HFwEgXMaNHigSqAIModsegKqtme+8VSP9hFZdMEiONzOT6TKQlntbkToq 8foEo+Mf0wqDDKEQUJKKYfVpW1+Wr3gKgm//y0WCJhMRLIZqTiynzN/8X6paNSxIlDc2 Lwuokeg4nVwn8NHYqb5NU+WPcrlgiG2t/o8hGb/UsZbjFadtWIPd0cHLwGfbcmYc3PwT /SYA== X-Gm-Message-State: APzg51A7FD9vhT7FgptgTtUvVKC9fLyGbrDJZuU+veUdOgS1wO2DyEP6 /95IW/Gx3qyQmPTGN8CFMgMd X-Received: by 2002:a6b:fe06:: with SMTP id x6-v6mr32165502ioh.159.1537397898806; Wed, 19 Sep 2018 15:58:18 -0700 (PDT) Received: from localhost.localdomain ([209.82.80.116]) by smtp.gmail.com with ESMTPSA id a63-v6sm52951itc.38.2018.09.19.15.58.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Sep 2018 15:58:18 -0700 (PDT) From: Manivannan Sadhasivam To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Wed, 19 Sep 2018 15:58:02 -0700 Message-Id: <20180919225804.14375-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180919225804.14375-1-manivannan.sadhasivam@linaro.org> References: <20180919225804.14375-1-manivannan.sadhasivam@linaro.org> Cc: tom@vamrs.com, amit.kucheria@linaro.org, dev@vamrs.com, u-boot@lists.denx.de, Manivannan Sadhasivam , stephen@vamrs.com Subject: [U-Boot] [PATCH 2/4] rockchip: rk3399: Add common Rock960 family from Vamrs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Rock960 is a family of boards based on Rockchip RK3399 SoC from Vamrs. It consists of Rock960 (Consumer Edition) and Ficus (Enterprise Edition) 96Boards. Below are some of the key differences between both Rock960 and Ficus boards: 1. Different host enable GPIO for USB 2. Different power and reset GPIO for PCI-E 3. No Ethernet port on Rock960 The common board support will be utilized by both boards. The device tree has been organized in such a way that only the properties which differ between both boards are placed in the board specific dts and the reset of the nodes are placed in common dtsi file. Signed-off-by: Manivannan Sadhasivam [Added instructions for SD card boot] Signed-off-by: Ezequiel Garcia --- arch/arm/dts/rk3399-rock960.dtsi | 506 ++++++++++++++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 26 + board/vamrs/rock960_rk3399/Kconfig | 15 + board/vamrs/rock960_rk3399/MAINTAINERS | 6 + board/vamrs/rock960_rk3399/Makefile | 6 + board/vamrs/rock960_rk3399/README | 151 ++++++ board/vamrs/rock960_rk3399/rock960-rk3399.c | 50 ++ include/configs/rock960_rk3399.h | 15 + 8 files changed, 775 insertions(+) create mode 100644 arch/arm/dts/rk3399-rock960.dtsi create mode 100644 board/vamrs/rock960_rk3399/Kconfig create mode 100644 board/vamrs/rock960_rk3399/MAINTAINERS create mode 100644 board/vamrs/rock960_rk3399/Makefile create mode 100644 board/vamrs/rock960_rk3399/README create mode 100644 board/vamrs/rock960_rk3399/rock960-rk3399.c create mode 100644 include/configs/rock960_rk3399.h diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi new file mode 100644 index 00000000000..51644d6d02d --- /dev/null +++ b/arch/arm/dts/rk3399-rock960.dtsi @@ -0,0 +1,506 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2018 Linaro Ltd. + */ + +#include +#include +#include "rk3399.dtsi" + +/ { + vcc1v8_s0: vcc1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-boot-on; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 0>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + status = "okay"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v0_sd: LDO_REG5 { + regulator-name = "vcc3v0_sd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 17 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 14 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + clock-frequency = <100000000>; + clock-freq-min-max = <100000 100000000>; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; + card-detect-delay = <800>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 415466a49bb..8f18e33c76f 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -28,6 +28,31 @@ config TARGET_PUMA_RK3399 * HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI * SPI, I2C, I2S, UART, GPIO, ... +config TARGET_ROCK960_RK3399 + bool "Vamrs Limited Rock960 board family" + help + Support for Rock960 board family by Vamrs Limited. This board + family consists of Rock960 (Consumer Edition) and Ficus + (Enterprise Edition) 96Boards. + + Common features implemented on both boards: + * Rockchip RK3399 SoC (2xCortex A72, 4xCortex A53, ARM Mali T860MP4) + * 16/32GB eMMC, uSD slot + * HDMI/DP/MIPI + * 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons + + Additional features of Rock960: + * 2GiB/4GiB LPDDR3 RAM + * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only), + 1x USB 3.0 type C OTG + + Additional features of Ficus: + * 2GiB/4GiB DDR3 RAM + * Ethernet + * Dual SATA + * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), + 1x USB 3.0 type C OTG + endchoice config SYS_SOC @@ -38,5 +63,6 @@ config SYS_MALLOC_F_LEN source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" +source "board/vamrs/rock960_rk3399/Kconfig" endif diff --git a/board/vamrs/rock960_rk3399/Kconfig b/board/vamrs/rock960_rk3399/Kconfig new file mode 100644 index 00000000000..cacc53f3780 --- /dev/null +++ b/board/vamrs/rock960_rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ROCK960_RK3399 + +config SYS_BOARD + default "rock960_rk3399" + +config SYS_VENDOR + default "vamrs" + +config SYS_CONFIG_NAME + default "rock960_rk3399" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/vamrs/rock960_rk3399/MAINTAINERS b/board/vamrs/rock960_rk3399/MAINTAINERS new file mode 100644 index 00000000000..9f3fe75f4fb --- /dev/null +++ b/board/vamrs/rock960_rk3399/MAINTAINERS @@ -0,0 +1,6 @@ +ROCK960-RK3399 +M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org +S: Maintained +F: board/rockchip/rock960_rk3399 +F: include/configs/rock960_rk3399.h +F: configs/rock960-rk3399_defconfig diff --git a/board/vamrs/rock960_rk3399/Makefile b/board/vamrs/rock960_rk3399/Makefile new file mode 100644 index 00000000000..6c3e475b3a8 --- /dev/null +++ b/board/vamrs/rock960_rk3399/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Manivannan Sadhasivam +# + +obj-y += rock960-rk3399.o diff --git a/board/vamrs/rock960_rk3399/README b/board/vamrs/rock960_rk3399/README new file mode 100644 index 00000000000..f3389520b08 --- /dev/null +++ b/board/vamrs/rock960_rk3399/README @@ -0,0 +1,151 @@ +Contents +======== + +1. Introduction +2. Get the Source and prebuild binary +3. Compile the U-Boot +4. Compile the rkdeveloptool +5. Package the image + 5.1. Package the image for U-Boot SPL(option 1) + 5.2. Package the image for Rockchip miniloader(option 2) +6. Bootloader storage options +7. Flash the image to eMMC + 7.1. Flash the image with U-Boot SPL(option 1) + 7.2. Flash the image with Rockchip miniloader(option 2) +8. Create a bootable SD/MMC +9. And that is it + +Introduction +============ + +Rock960 board family consists of Rock960 (Consumer Edition) and +Ficus (Enterprise Edition) 96Boards featuring Rockchip RK3399 SoC. + +Common features implemented on both boards: + * CPU: ARMv8 64bit Big-Little architecture, + * Big: dual-core Cortex-A72 + * Little: quad-core Cortex-A53 + * IRAM: 200KB + * eMMC: 16/32GB eMMC 5.1 + * PMU: RK808 + * SD/MMC + * Display: HDMI/DP/MIPI + * Low Speed Expansion Connector + * High Speed Expansion Connector + +Additional features of Rock960: + * DRAM: 2GB/4GB LPDDR3 @ 1866MHz + * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only), + 1x USB 3.0 type C OTG + +Additional features of Ficus: + * DRAM: 2GB/4GB DDR3 @ 1600MHz + * Ethernet + * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), + 1x USB 3.0 type C OTG + +Here is the step-by-step to boot to U-Boot on Rock960 boards. + +Get the Source and prebuild binary +================================== + + > git clone https://github.com/96rocks/rkbin.git + > git clone https://github.com/rockchip-linux/rkdeveloptool.git + +Compile the U-Boot +================== + + > cd ../u-boot + > export ARCH=arm64 + > export CROSS_COMPILE=aarch64-linux-gnu- + > make rock960-rk3399_defconfig + > make + > make u-boot.itb + +Compile the rkdeveloptool +========================= + +Follow instructions in latest README + > cd ../rkdeveloptool + > autoreconf -i + > ./configure + > make + > sudo make install + +Package the image +================= + +Package the image for U-Boot SPL(option 1) +-------------------------------- + > cd .. + > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin idbspl.img + + Get idbspl.img in this step. + +Package the image for Rockchip miniloader(option 2) +------------------------------------------ + > cd ../rkbin + > ./tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img 0x200000 + + > ../u-boot/tools/mkimage -n rk3399 -T rksd -d rk3399_ddr_933MHz_v1.08.bin idbloader.img + > cat ./rk33/rk3399_miniloader_v1.06.bin >> idbloader.img + + Get uboot.img and idbloader.img in this step. + +Bootloader storage options +========================== + +There are a few different storage options for the bootloader. +This document explores two of these: eMMC and removable SD/MMC. + +Flash the image to eMMC +======================= + +Flash the image with U-Boot SPL(option 1) +------------------------------- +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin + > rkdeveloptool wl 64 u-boot/idbspl.img + > rkdeveloptool wl 0x4000 u-boot/u-boot.itb + > rkdeveloptool rd + +Flash the image with Rockchip miniloader(option 2) +---------------------------------------- +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin + > rkdeveloptool wl 0x40 idbloader.img + > rkdeveloptool wl 0x4000 uboot.img + > rkdeveloptool wl 0x6000 ./img/rk3399/trust.img + > rkdeveloptool rd + +Create a bootable SD/MMC +======================== + +The idbspl.img contains the first stage, and the u-boot.img the second stage. +As explained in the Rockchip partition table reference [1], the first stage +(aka loader1) start sector is 64, and the second stage start sector is 16384. + +Each sector is 512 bytes, which means the first stage offset is 32 KiB, +and the second stage offset is 8 MiB. + +Note: the second stage location is actually not as per the spec, +but defined by the SPL. Mainline SPL defines an 8 MiB offset for the second +stage. + +Assuming the SD card is exposed by device /dev/mmcblk0, the commands +to write the two stages are: + + > dd if=idbspl.img of=/dev/mmcblk0 bs=1k seek=32 + > dd if=u-boot.itb of=/dev/mmcblk0 bs=1k seek=8192 + +Setting up the kernel and rootfs is beyond the scope of this document. + +And that is it +============== + +You should be able to get U-Boot log in console/UART2(baurdrate 1500000) + +For more detail, please reference [2]. + +[1] http://opensource.rock-chips.com/wiki_Partitions +[2] http://opensource.rock-chips.com/wiki_Boot_option diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c new file mode 100644 index 00000000000..d3775b22191 --- /dev/null +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include + +int board_init(void) +{ + int ret; + + ret = regulators_enable_boot_on(false); + if (ret) + debug("%s: Cannot enable boot on regulator\n", __func__); + + return 0; +} + +void spl_board_init(void) +{ + struct udevice *pinctrl; + int ret; + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + goto err; + } + + preloader_console_init(); + return; +err: + printf("%s: Error %d\n", __func__, ret); + + /* No way to report error here */ + hang(); +} diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h new file mode 100644 index 00000000000..746d24cbff5 --- /dev/null +++ b/include/configs/rock960_rk3399.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#ifndef __ROCK960_RK3399_H +#define __ROCK960_RK3399_H + +#include + +#define CONFIG_SYS_MMC_ENV_DEV 1 + +#define SDRAM_BANK_SIZE (2UL << 30) + +#endif From patchwork Wed Sep 19 22:58:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 147065 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp1261692ljw; Wed, 19 Sep 2018 16:00:08 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZ5PM2bqv4dh51t2+c/Yvd9ZPcVWM7D5rmNBzR5qdhwsTxJnhyxXBoqpBZCxmd6MMo65QBT X-Received: by 2002:aa7:d884:: with SMTP id u4-v6mr154067edq.223.1537398008029; Wed, 19 Sep 2018 16:00:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537398008; cv=none; d=google.com; s=arc-20160816; b=NARCctj7oYyMfrvs3Fef9ZVveHITFLGkP24ovT7n7d42oJ7Q+A1QiA5H8r6/OOP5Gx cf06aF6LICmJwUu1zwf0qpAHSyeJCsvzj6ri0Lu3HC47ZfMz2YVBV2s1ZOHoxOD1zHJI pvW48uE4qqlIwZ2BM44cN2mEphsKlKI3F7QEpy5bLdm/TfbjarfBR2JnS9CS53asr55I FHwipGdwBX7IilW9HVxDYCgtTSD1dRKP4dY/5xU2SOHIP41jPlzjSsKjptIjoNMUnGsY YldJ3EAbXeM+VSdZcD1AjenLjoEy82dKH/QOJ4DQmBdQQHjwrRoGKqaV+DPIpO929V9y 5emA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=p2E9RdNipxq08yWbEHkfIvtHSt3R+3uzdF12tX73I68=; b=hZC/XRXZ7GusU+kDdZrUqLuUugJtKYzpahC+jSCCyl2d8G3GYCxhDvL8Qnsd1BZcVR +AD7ah3Clm/Ub0QLYaXxFqyQT8na14q/TTeMBJcVrTcOLh1+P4f8Xk58kaX2QRnN874Z fYwZbzvUbm79psnC2XjRv1Xm+Wb4722S0owcr/tn5ksFqy33+4FOWf07gBMIgB8403EU 0zrGh4RXYhCY2pVgAecIueE5YMAziY7WTsnSHvNZUHDr111RZ7qzJzu6jXXghpeGw1M4 DnrA3G49p0u8IL4x6wOk+XbNXNElIkPqByKL+bH/cYVsgkusmQ834e9V0A0OMxfsTaVJ jj0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="CLIN/soU"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id c15-v6si118642edf.218.2018.09.19.16.00.07; Wed, 19 Sep 2018 16:00:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="CLIN/soU"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 890A0C21E68; Wed, 19 Sep 2018 22:59:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D079CC21E96; Wed, 19 Sep 2018 22:58:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5A535C21E44; Wed, 19 Sep 2018 22:58:26 +0000 (UTC) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by lists.denx.de (Postfix) with ESMTPS id 71E37C21DED for ; Wed, 19 Sep 2018 22:58:22 +0000 (UTC) Received: by mail-io1-f67.google.com with SMTP id c22-v6so5880015iob.1 for ; Wed, 19 Sep 2018 15:58:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NPCl3YgKKhP1xo4tNpd/aQqAHxs0B3+N50pS9T/5c2U=; b=CLIN/soUr3YvjZSYXyaqyYvWtg9CJdohQ8RxCr4Si94GBS4BqIP+cRHuf4BtOf3OCC OFyuWnWOJURnhNGvq/lX2Z5Q7BHojXuNxmWVF7s0vPtKGAQgPqxI7rttwqCN6CcvAmod WifHAwwLfj2GSL/bdr33Lg5nyFEeIj8UX1VeE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NPCl3YgKKhP1xo4tNpd/aQqAHxs0B3+N50pS9T/5c2U=; b=i7UqKeF5kw7moiQURJg5oE1pCHEdtKWTcAIUxy+dDSsyWz4pv470xg3VgbuPFPRrgS mHY1QTlOFYHNCv/I8xfQIXo0D35lAfp8bQu7G0kKZXQCtKrFNGC9oK9aui5sXOj3o3ek DKQPk7MdR1wOPBBSf/12txaaW92es7ondOIZ66s/Fe3NMKe9rQdMM6JB5HxzGnFV+YJy 4yTMQlUyd1haO+51qBf6dO5WsmDcI5ajp8emh1prCr92A9lKpfxXeNh/Awwmg6TXWMi7 3vUhP8e2xin3sFWZ09Y9hL5XhwDEhURMj6uUQM9v2w1SSEAZ0p5tNRo1bOd2WU3Y7JmX RBGQ== X-Gm-Message-State: APzg51Aihv1lPQYiFoqrkkyGAEKrKAZ5RHZ9XagJdVtaxTAZFeLdVFT0 r574ctfyF6XKGe2X+tlVqFdL X-Received: by 2002:a6b:c389:: with SMTP id t131-v6mr32556113iof.157.1537397900604; Wed, 19 Sep 2018 15:58:20 -0700 (PDT) Received: from localhost.localdomain ([209.82.80.116]) by smtp.gmail.com with ESMTPSA id a63-v6sm52951itc.38.2018.09.19.15.58.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Sep 2018 15:58:20 -0700 (PDT) From: Manivannan Sadhasivam To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Wed, 19 Sep 2018 15:58:03 -0700 Message-Id: <20180919225804.14375-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180919225804.14375-1-manivannan.sadhasivam@linaro.org> References: <20180919225804.14375-1-manivannan.sadhasivam@linaro.org> Cc: tom@vamrs.com, amit.kucheria@linaro.org, dev@vamrs.com, u-boot@lists.denx.de, Manivannan Sadhasivam , stephen@vamrs.com Subject: [U-Boot] [PATCH 3/4] rockchip: rk3399: Add Rock960 CE board support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add board support for Rock960 CE board from Vamrs. This board utilizes common Rock960 family support. Following peripherals are tested and known to work: * USB 2.0 * MMC This commit also adds DDR configuration for LPDDR3-2GiB-1866MHz. Signed-off-by: Manivannan Sadhasivam --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rock960.dts | 45 + .../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 1536 +++++++++++++++++ configs/rock960-rk3399_defconfig | 62 + 4 files changed, 1644 insertions(+) create mode 100644 arch/arm/dts/rk3399-rock960.dts create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi create mode 100644 configs/rock960-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ebfa2272627..9b891826b73 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ + rk3399-rock960.dtb \ rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts new file mode 100644 index 00000000000..25c58b42611 --- /dev/null +++ b/arch/arm/dts/rk3399-rock960.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "rk3399-rock960.dtsi" +#include "rk3399-sdram-lpddr3-2GB-1600.dtsi" + +/ { + model = "96boards Rock960"; + compatible = "vamrs,rock960", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc3v3_pcie { + gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host { + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi new file mode 100644 index 00000000000..d14e833d228 --- /dev/null +++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi @@ -0,0 +1,1536 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2018 Manivannan Sadhasivam + */ + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + 0x1d191519 + 0x14040808 + 0x00000002 + 0x00006226 + 0x00000054 + 0x00000000 + 0x1 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + 0x1d191519 + 0x14040808 + 0x00000002 + 0x00006226 + 0x00000054 + 0x00000000 + 800 + 6 + 2 + 9 + 1 + 0x00000700 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000050 + 0x00027100 + 0x00000320 + 0x00001f40 + 0x00000050 + 0x00027100 + 0x00000320 + 0x00001f40 + 0x00000050 + 0x00027100 + 0x00000320 + 0x01001f40 + 0x00000000 + 0x00000101 + 0x00020100 + 0x000000a0 + 0x00000190 + 0x00000000 + 0x06180000 + 0x00061800 + 0x04000618 + 0x33080004 + 0x280f0622 + 0x22330800 + 0x00280f06 + 0x06223308 + 0x0600280f + 0x00000a0a + 0x0600dac0 + 0x0a0a060c + 0x0600dac0 + 0x0a0a060c + 0x0600dac0 + 0x0203000c + 0x0f0c0f00 + 0x040c0f0c + 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b/configs/rock960-rk3399_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_TARGET_ROCK960_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_BAUDRATE=1500000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" +CONFIG_SYS_PROMPT="rock960 => " +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3399=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_SYSRESET=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y From patchwork Wed Sep 19 22:58:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 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This board utilizes common Rock960 family support. Following peripherals are tested and known to work: * Gigabit Ethernet * USB 2.0 * MMC Signed-off-by: Ezequiel Garcia [Reworked based on common Rock960 family support] Signed-off-by: Manivannan Sadhasivam --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-ficus.dts | 78 ++++++++++++++++++++++++++++++++++ configs/ficus-rk3399_defconfig | 71 +++++++++++++++++++++++++++++++ 3 files changed, 150 insertions(+) create mode 100644 arch/arm/dts/rk3399-ficus.dts create mode 100644 configs/ficus-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9b891826b73..e2bd9822aa2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-minnie.dtb \ rk3288-vyasa.dtb \ rk3328-evb.dtb \ + rk3399-ficus.dtb \ rk3368-lion.dtb \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts new file mode 100644 index 00000000000..de934cd61ab --- /dev/null +++ b/arch/arm/dts/rk3399-ficus.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + * + * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw + */ + +/dts-v1/; +#include "rk3399-rock960.dtsi" +#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" + +/ { + model = "96boards RK3399 Ficus"; + compatible = "vamrs,ficus", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_sys>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + gmac { + rgmii_sleep_pins: rgmii-sleep-pins { + rockchip,pins = + <3 15 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <1 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 27 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc3v3_pcie { + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host { + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; +}; diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig new file mode 100644 index 00000000000..e890bc25238 --- /dev/null +++ b/configs/ficus-rk3399_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_ROCK960_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_RGMII=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3399=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y