From patchwork Fri May 19 04:25:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 100146 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp140994qge; Thu, 18 May 2017 21:26:46 -0700 (PDT) X-Received: by 10.99.124.94 with SMTP id l30mr8072094pgn.55.1495168006335; Thu, 18 May 2017 21:26:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495168006; cv=none; d=google.com; s=arc-20160816; b=Fr2iSpyVvG+mTgj2N0a8/TcC3Awosbr4CLQXOED6poE6lsrCW8Or97tlmwLviWgH6v bgG4o5eN1P2GBX8vIPGr/H2tDLow+DFApAHqyiURvT5HvuLY50GwiAZEpzxduBCoFaCq lXTvL9fVhMtRTD7KdBjkfRahfTR2heUd81A8s615aJg1VdHW18BK+1ZOdB8N70EUJm+k i5z9V3XsXvwo28C+EX7LUX8HnqjVM9mAFvAXThrH5UTK745pbQcWaKQsk25Q6u7H0gFh RwELsLN/xXaXpgMBYDWCp9HnDpcSKoaKuSHPgsftapi2mblX4CuT+tPWjfZ1D9rUOCTV sT5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=C2MVggQI5FIxB7AFkJBKKdd6ewELSNqFg/FqKXCWlDc=; b=brVqYHb93UUDYZqr2dNNed9wHl27sT+YFHmxGO5NzlScJq1kMT1O5tmhIs58DYdnwM ik1soMmOyLOE6krxkVVi7sqNoY6MfjlAczp1gzYKShbTnEcn/EQFLA79QMBsrO/dJsaF yuQ1aV9urCGfqChjAuwTxD0vvrDBK25bG89gjJncizxyBobdoX77wE+K2kH/usOjEjG6 cFwsI3Ab0GO1dxcUAYc0MC3A/dggXWkMZCOo6DPQLTRJeMR1L056vRJ9mdppKXYUqZuW US1WfdQ+tQETbXVMFLu9rBwtoCEoUia36TkjNDWP73VSLFD4vqyUCMkqE7TcWkwoQpFs dPxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[106.186.117.108]) by smtp.gmail.com with ESMTPSA id c29sm5823259pfj.101.2017.05.18.21.26.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 21:26:27 -0700 (PDT) From: Leo Yan To: Jonathan Corbet , Mathieu Poirier , Rob Herring , Mark Rutland , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Catalin Marinas , Will Deacon , Wei Xu , Andy Gross , David Brown , Greg Kroah-Hartman , Suzuki K Poulose , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Stephen Boyd , Mike Leach Cc: Leo Yan Subject: [PATCH v10 01/10] coresight: bindings for CPU debug module Date: Fri, 19 May 2017 12:25:48 +0800 Message-Id: <1495167957-14923-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> References: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to APB clock; and also need specify the CPU node which the debug module is dedicated to specific CPU. Suggested-by: Mike Leach Reviewed-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Acked-by: Rob Herring Signed-off-by: Leo Yan --- .../bindings/arm/coresight-cpu-debug.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt new file mode 100644 index 0000000..2982912 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt @@ -0,0 +1,49 @@ +* CoreSight CPU Debug Component: + +CoreSight CPU debug component are compliant with the ARMv8 architecture +reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The +external debug module is mainly used for two modes: self-hosted debug and +external debug, and it can be accessed from mmio region from Coresight +and eventually the debug module connects with CPU for debugging. And the +debug module provides sample-based profiling extension, which can be used +to sample CPU program counter, secure state and exception level, etc; +usually every CPU has one dedicated debug module to be connected. + +Required properties: + +- compatible : should be "arm,coresight-cpu-debug"; supplemented with + "arm,primecell" since this driver is using the AMBA bus + interface. + +- reg : physical base address and length of the register set. + +- clocks : the clock associated to this component. + +- clock-names : the name of the clock referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk" and the clock is + mandatory. The interface between the debug logic and the + processor core is clocked by the internal CPU clock, so it + is enabled with CPU clock by default. + +- cpu : the CPU phandle the debug module is affined to. When omitted + the module is considered to belong to CPU0. + +Optional properties: + +- power-domains: a phandle to the debug power domain. We use "power-domains" + binding to turn on the debug logic if it has own dedicated + power domain and if necessary to use "cpuidle.off=1" or + "nohlt" in the kernel command line or sysfs node to + constrain idle states to ensure registers in the CPU power + domain are accessible. + +Example: + + debug@f6590000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; From patchwork Fri May 19 04:25:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 100147 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp140996qge; Thu, 18 May 2017 21:26:46 -0700 (PDT) X-Received: by 10.99.99.134 with SMTP id x128mr7902236pgb.46.1495168006702; Thu, 18 May 2017 21:26:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495168006; cv=none; d=google.com; s=arc-20160816; b=o8oPKVzuFva27E9+VwyjBSdxVY6Xl3roXNwVypUFOrCyJt1WgGs48DCY5lHNf8sihA CXnczAhfM5pLrFp4xanlICW9kZk9QgI9BkgAUgnRcCONApAgoBeavXPGjh/I7ztPr47x Fyi8sh/IFC2uJC0Rwx7EcqKsqwOIn6jX3d8fQW5svi7pf0+3UtWkuP0ad9Kz3zHqXKOg 1r7ORY3YU7HLza41YketiXZee2o3VVVjZBQEtgcWIqc75cwo/6+PApjLpyDAdgu1V6yp LGo5yYRSVgVruoItshyIAe+kZktUgsN649C8rpEr/8OO7ulcvVshhx/U9oNUxkvo+Cde O2hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Qq15D1C1g7mX2slvGymWhGWg6mspVxHvR4d1WAiKQ3o=; b=lShnEIWkBvHEZrJ9e68DEJ+HUliG1ffBAnGHflA5jiBouTIT5TIOMvXKSGTwFBFWLe q6Dl9bW/O4W8734cn1lXK9be7ZRb58yoQk1FTzMKHMvl4FVz6VnvPah/+iWiftvpEA5Y m4cSZg2eEsHtmQPSBk4SondTRRxKKtzmDR6EW2BS/5rScnhCfg7AIahxPH/l3IpRZlYt BDH3l5bPY++DUHO1ljCOq0IjDdVUrh0g/KYpPkcycBUiV1hu7LnrsvPWvpT/mwzse4Cl k6Z8sSQEd3ldgEebIoOzwdh7fixhAw5Xk2OTQkw1esgEx3FBv66ZkeU3VsEOvdLXM0HH kBWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[106.186.117.108]) by smtp.gmail.com with ESMTPSA id c29sm5823259pfj.101.2017.05.18.21.26.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 21:26:36 -0700 (PDT) From: Leo Yan To: Jonathan Corbet , Mathieu Poirier , Rob Herring , Mark Rutland , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Catalin Marinas , Will Deacon , Wei Xu , Andy Gross , David Brown , Greg Kroah-Hartman , Suzuki K Poulose , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Stephen Boyd , Mike Leach Cc: Leo Yan Subject: [PATCH v10 02/10] doc: Add documentation for Coresight CPU debug Date: Fri, 19 May 2017 12:25:49 +0800 Message-Id: <1495167957-14923-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> References: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add detailed documentation for Coresight CPU debug driver, which contains the info for driver implementation, Mike Leach excellent summary for "clock and power domain". At the end some examples on how to enable the debugging functionality are provided. Suggested-by: Mike Leach Reviewed-by: Mathieu Poirier Signed-off-by: Leo Yan --- Documentation/trace/coresight-cpu-debug.txt | 174 ++++++++++++++++++++++++++++ 1 file changed, 174 insertions(+) create mode 100644 Documentation/trace/coresight-cpu-debug.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight-cpu-debug.txt new file mode 100644 index 0000000..f0c3f0f --- /dev/null +++ b/Documentation/trace/coresight-cpu-debug.txt @@ -0,0 +1,174 @@ + Coresight CPU Debug Module + ========================== + + Author: Leo Yan + Date: April 5th, 2017 + +Introduction +------------ + +Coresight CPU debug module is defined in ARMv8-a architecture reference manual +(ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate +debug module and it is mainly used for two modes: self-hosted debug and +external debug. Usually the external debug mode is well known as the external +debugger connects with SoC from JTAG port; on the other hand the program can +explore debugging method which rely on self-hosted debug mode, this document +is to focus on this part. + +The debug module provides sample-based profiling extension, which can be used +to sample CPU program counter, secure state and exception level, etc; usually +every CPU has one dedicated debug module to be connected. Based on self-hosted +debug mechanism, Linux kernel can access these related registers from mmio +region when the kernel panic happens. The callback notifier for kernel panic +will dump related registers for every CPU; finally this is good for assistant +analysis for panic. + + +Implementation +-------------- + +- During driver registration, use EDDEVID and EDDEVID1 two device ID + registers to decide if sample-based profiling is implemented or not. On some + platforms this hardware feature is fully or partialy implemented; and if + this feature is not supported then registration will fail. + +- When write this doc, the debug driver mainly relies on three sampling + registers. The kernel panic callback notifier gathers info from EDPCSR + EDVIDSR and EDCIDSR; from EDPCSR we can get program counter, EDVIDSR has + information for secure state, exception level, bit width, etc; EDCIDSR is + context ID value which contains the sampled value of CONTEXTIDR_EL1. + +- The driver supports CPU running mode with either AArch64 or AArch32. The + registers naming convention is a bit different between them, AArch64 uses + 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses + 'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to + use AArch64 naming convention. + +- ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different + register bits definition. So the driver consolidates two difference: + + If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented; + but ARMv7-a defines "PCSR samples are offset by a value that depends on the + instruction set state". For ARMv7-a, the driver checks furthermore if CPU + runs with ARM or thumb instruction set and calibrate PCSR value, the + detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter + C11.11.34 "DBGPCSR, Program Counter Sampling Register". + + If PCSROffset=0b0010, ARMv8-a defines "EDPCSR implemented, and samples have + no offset applied and do not sample the instruction set state in AArch32 + state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates + in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64 + state EDPCSR is sampled and no offset are applied. + + +Clock and power domain +---------------------- + +Before accessing debug registers, we should ensure the clock and power domain +have been enabled properly. In ARMv8-a ARM (ARM DDI 0487A.k) chapter 'H9.1 +Debug registers', the debug registers are spread into two domains: the debug +domain and the CPU domain. + + +---------------+ + | | + | | + +----------+--+ | + dbg_clk -->| |**| |<-- cpu_clk + | Debug |**| CPU | + dbg_pd -->| |**| |<-- cpu_pd + +----------+--+ | + | | + | | + +---------------+ + +For debug domain, the user uses DT binding "clocks" and "power-domains" to +specify the corresponding clock source and power supply for the debug logic. +The driver calls the pm_runtime_{put|get} operations as needed to handle the +debug power domain. + +For CPU domain, the different SoC designs have different power management +schemes and finally this heavily impacts external debug module. So we can +divide into below cases: + +- On systems with a sane power controller which can behave correctly with + respect to CPU power domain, the CPU power domain can be controlled by + register EDPRCR in driver. The driver firstly writes bit EDPRCR.COREPURQ + to power up the CPU, and then writes bit EDPRCR.CORENPDRQ for emulation + of CPU power down. As result, this can ensure the CPU power domain is + powered on properly during the period when access debug related registers; + +- Some designs will power down an entire cluster if all CPUs on the cluster + are powered down - including the parts of the debug registers that should + remain powered in the debug power domain. The bits in EDPRCR are not + respected in these cases, so these designs do not support debug over + power down in the way that the CoreSight / Debug designers anticipated. + This means that even checking EDPRSR has the potential to cause a bus hang + if the target register is unpowered. + + In this case, accessing to the debug registers while they are not powered + is a recipe for disaster; so we need preventing CPU low power states at boot + time or when user enable module at the run time. Please see chapter + "How to use the module" for detailed usage info for this. + + +Device Tree Bindings +-------------------- + +See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details. + + +How to use the module +--------------------- + +If you want to enable debugging functionality at boot time, you can add +"coresight_cpu_debug.enable=1" to the kernel command line parameter. + +The driver also can work as module, so can enable the debugging when insmod +module: +# insmod coresight_cpu_debug.ko debug=1 + +When boot time or insmod module you have not enabled the debugging, the driver +uses the debugfs file system to provide a knob to dynamically enable or disable +debugging: + +To enable it, write a '1' into /sys/kernel/debug/coresight_cpu_debug/enable: +# echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable + +To disable it, write a '0' into /sys/kernel/debug/coresight_cpu_debug/enable: +# echo 0 > /sys/kernel/debug/coresight_cpu_debug/enable + +As explained in chapter "Clock and power domain", if you are working on one +platform which has idle states to power off debug logic and the power +controller cannot work well for the request from EDPRCR, then you should +firstly constraint CPU idle states before enable CPU debugging feature; so can +ensure the accessing to debug logic. + +If you want to limit idle states at boot time, you can use "nohlt" or +"cpuidle.off=1" in the kernel command line. + +At the runtime you can disable idle states with below methods: + +Set latency request to /dev/cpu_dma_latency to disable all CPUs specific idle +states (if latency = 0uS then disable all idle states): +# echo "what_ever_latency_you_need_in_uS" > /dev/cpu_dma_latency + +Disable specific CPU's specific idle state: +# echo 1 > /sys/devices/system/cpu/cpu$cpu/cpuidle/state$state/disable + + +Output format +------------- + +Here is an example of the debugging output format: + +ARM external debug module: +coresight-cpu-debug 850000.debug: CPU[0]: +coresight-cpu-debug 850000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock) +coresight-cpu-debug 850000.debug: EDPCSR: [] handle_IPI+0x174/0x1d8 +coresight-cpu-debug 850000.debug: EDCIDSR: 00000000 +coresight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0) +coresight-cpu-debug 852000.debug: CPU[1]: +coresight-cpu-debug 852000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock) +coresight-cpu-debug 852000.debug: EDPCSR: [] debug_notifier_call+0x23c/0x358 +coresight-cpu-debug 852000.debug: EDCIDSR: 00000000 +coresight-cpu-debug 852000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0) From patchwork Fri May 19 04:25:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 100148 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp141020qge; Thu, 18 May 2017 21:26:51 -0700 (PDT) X-Received: by 10.99.124.68 with SMTP id l4mr8197783pgn.175.1495168010928; Thu, 18 May 2017 21:26:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495168010; cv=none; d=google.com; s=arc-20160816; b=s8jq+mySCxbZAE3OlH2XNmfDvl42NECc/MQiB45oANq5TrsHeGewZKXBTK14F0BYjz PJIgErW503hWh6+HW1eiLu9meR8/srNvUUKDezBE/Z/E8+BZoJ2iKqA2wVDSKAckUf7/ 2/pmcb1hM22LhbmeGPBfpRTZoR3FTIRqG9n+TIfSGsaTzvMahZcu5sWfpc4K0+PdVB7B 7B2vcVDx+6dq27lOEU/l8SYJbXkgXrMJ6fMJQ5PpUMRB2mSpghvY8rYo6LSd/i0uc2vB ID/LoH6YKRaKX6ZMS7PBE0b3vkStstNfCkiJhvn6bxSSBuWJ5eoMNCGGSWMvDY0FjX8T ZhFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=udC6FncqPU5gtkx8ADgdRpDI7c40ABVrkZIkfAVlqYY=; b=oMFYBcSQlzHfdZp5teOVHUIa61GlVCAF14Xc247ACATVblJgIqyIXaswW266PncPvV fUzmRvPjxbyAbLsg5lGe1YDLAcBkP0a0+IUzsRbDtO9XJZE2Vs0LFpGrNOxnnmn9537A pcMbtOhcNAtUTDeiml0ghxdDkaTktJ75XSCd0Am8wjCIpNC7cnEfE4Bi9AIy8iO7Z/nq dgNWzAK+YSwjWhvDwSqV2n964KgU+uuxK8QT3C9p06BbY7rVqYAoeAt+ycZ/J1/mJcyo 8KCZNem6lyNBQz/7mXyGbJQ+Sdv4z6uRICmzW47/jY8BigO2dNL9c+fHcwoOUJvwAAo+ alog== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z185si7237807pgb.292.2017.05.18.21.26.50; Thu, 18 May 2017 21:26:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753312AbdESE0t (ORCPT + 10 others); Fri, 19 May 2017 00:26:49 -0400 Received: from mail-pf0-f169.google.com ([209.85.192.169]:33869 "EHLO mail-pf0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753106AbdESE0r (ORCPT ); Fri, 19 May 2017 00:26:47 -0400 Received: by mail-pf0-f169.google.com with SMTP id 9so33735402pfj.1 for ; Thu, 18 May 2017 21:26:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KAEJxJlsQyVhwB4d8GGxsab6nI8NeyaoHh9oKfAyIsc=; b=YjgtMYqnmPCM69HRfoGgzy0HzvmUnDRral0LJUQ6YgDMEyDSB+dPwzHnJZA6TvmRnm 2tZaepbKoZIMpgYtOhwMNJIYcPyseVmW6j3+s7OlUoe4u3gKzjzvXFNt+7diNI4TQIAx zulWAAQ88LER/ZNFGxBpAtb7ezQTjQ8iBWbcU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KAEJxJlsQyVhwB4d8GGxsab6nI8NeyaoHh9oKfAyIsc=; b=iaq/qD5V03fn/nhcBr/cAHNfd1TUwlEGMuM3vrryngnazS3QgXJslFr9Gk/vtG0V5I T0B2FOowyfOk9wbsEls85jll6kyx2JDQ0bazuK8EoZJZXCrKtdqPasVgoF1t2zbIm/Jj apyAEKn/Fwg6L5Nq/omRxa6AZ7MbMvbMYiNhiPP9215MbuOa899lOrAs13bq6xR7Yexd FJ/CsC21+udqo0YZDaFmgYFW+KGnpmZ63Cfa2WgKkCFJidZxPo0Qwy4mXOV+uvIrHvAe OatBoJgFZMOXgfHKOroEMfjyKS/+TO8yMVpeTK3574CdZ74NCLxSEHwy2y3huhC/FR4P TBXw== X-Gm-Message-State: AODbwcC02DHhtDz3/veOdjj3Q/Z//iFTfBPrzuxarE6zf0fGe9POoJcO ek1Jkv3y9smz5a3P X-Received: by 10.84.217.218 with SMTP id d26mr9125224plj.47.1495168006699; Thu, 18 May 2017 21:26:46 -0700 (PDT) Received: from localhost.localdomain (li637-108.members.linode.com. [106.186.117.108]) by smtp.gmail.com with ESMTPSA id c29sm5823259pfj.101.2017.05.18.21.26.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 21:26:45 -0700 (PDT) From: Leo Yan To: Jonathan Corbet , Mathieu Poirier , Rob Herring , Mark Rutland , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Catalin Marinas , Will Deacon , Wei Xu , Andy Gross , David Brown , Greg Kroah-Hartman , Suzuki K Poulose , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Stephen Boyd , Mike Leach Cc: Leo Yan Subject: [PATCH v10 03/10] doc: Add coresight_cpu_debug.enable to kernel-parameters.txt Date: Fri, 19 May 2017 12:25:50 +0800 Message-Id: <1495167957-14923-4-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> References: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add coresight_cpu_debug.enable to kernel-parameters.txt, this flag is used to enable/disable the CPU sampling based debugging. Reviewed-by: Mathieu Poirier Signed-off-by: Leo Yan --- Documentation/admin-guide/kernel-parameters.txt | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 15f79c2..ff67ad7 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -649,6 +649,13 @@ /proc//coredump_filter. See also Documentation/filesystems/proc.txt. + coresight_cpu_debug.enable + [ARM,ARM64] + Format: + Enable/disable the CPU sampling based debugging. + 0: default value, disable debugging + 1: enable debugging at boot time + cpuidle.off=1 [CPU_IDLE] disable the cpuidle sub-system From patchwork Fri May 19 04:25:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 100151 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp141221qge; Thu, 18 May 2017 21:27:38 -0700 (PDT) X-Received: by 10.98.192.80 with SMTP id x77mr8353701pff.1.1495168058532; Thu, 18 May 2017 21:27:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495168058; cv=none; d=google.com; s=arc-20160816; b=zxSWiEO0C6T1hSGiCUYTA7sUBIbMDJj5Gu3PlB9H1UQvsrgmeXzFogyW/lVZxTWl+x qu9spt7TIflhUEGbg67twwNaNNhmIFsDWUKqgJM2UoKTy/VnBcXROoToMELx/dE9fxDA dnDbToqek9aSc00B9EK9w/8bGSRbGGvFhODAUHpwaqe2Uc4X4fnfc7q63frNuawVYbzR R1E6AgkyTPQeoTkqP+Y0SpmudxdX8Y7w2ck/yndD0hnq9OWUCUKoo+512U9sIJK41TaP dT5tAkStJsA6UEW//2Ca2seurbx0pH8G+UcjrGfaz5+Rdi4tbMNlE755pkYh6g+SIb6t TTfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=pQBhgBdAWMz2W1N5baOSR/Y3fVkFD+KZqlylO+zf+fU=; b=eXI8YXl2N0tkTu0wNMKaMIBB2eOWu9zd0N8J7cJXockcUlKScMSweI8Q7EVjhmiqmG 2ACN4iC35hrMJkRvEhtHqYl5XMCNgdDRunBACe1Ks1/4vdfJew8H0+iu48I1roczfaUe lhaT44o9PY3CtfCej9eK/dtodepvYK3oMNwBarNM/LafQkQ29+C8g6HaIN770kMnuhOQ SvL1AT77MkqOTESv6CNcAPl60zRur+jWzXgD+AkEt+T4liHES8NqCjaQTl4V+RsJJ10E LIfeNrs/BafEwpt5TCFWfWmKrBXKLmgdIfsgTpiJk5A9cS3e82qYfbpHp65jFMdriua0 SYjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[106.186.117.108]) by smtp.gmail.com with ESMTPSA id c29sm5823259pfj.101.2017.05.18.21.27.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 21:27:11 -0700 (PDT) From: Leo Yan To: Jonathan Corbet , Mathieu Poirier , Rob Herring , Mark Rutland , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Catalin Marinas , Will Deacon , Wei Xu , Andy Gross , David Brown , Greg Kroah-Hartman , Suzuki K Poulose , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Stephen Boyd , Mike Leach Cc: Leo Yan Subject: [PATCH v10 06/10] coresight: refactor with function of_coresight_get_cpu Date: Fri, 19 May 2017 12:25:53 +0800 Message-Id: <1495167957-14923-7-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> References: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This is refactor to add function of_coresight_get_cpu(), so it's used to retrieve CPU id for coresight component. Finally can use it as a common function for multiple places. Suggested-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/of_coresight.c | 43 +++++++++++++++++++----------- include/linux/coresight.h | 3 +++ 2 files changed, 31 insertions(+), 15 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c index 225b2dd..a187941 100644 --- a/drivers/hwtracing/coresight/of_coresight.c +++ b/drivers/hwtracing/coresight/of_coresight.c @@ -101,16 +101,40 @@ static int of_coresight_alloc_memory(struct device *dev, return 0; } +int of_coresight_get_cpu(const struct device_node *node) +{ + int cpu; + bool found; + struct device_node *dn, *np; + + dn = of_parse_phandle(node, "cpu", 0); + + /* Affinity defaults to CPU0 */ + if (!dn) + return 0; + + for_each_possible_cpu(cpu) { + np = of_cpu_device_node_get(cpu); + found = (dn == np); + of_node_put(np); + if (found) + break; + } + of_node_put(dn); + + /* Affinity to CPU0 if no cpu nodes are found */ + return found ? cpu : 0; +} +EXPORT_SYMBOL_GPL(of_coresight_get_cpu); + struct coresight_platform_data * of_get_coresight_platform_data(struct device *dev, const struct device_node *node) { - int i = 0, ret = 0, cpu; + int i = 0, ret = 0; struct coresight_platform_data *pdata; struct of_endpoint endpoint, rendpoint; struct device *rdev; - bool found; - struct device_node *dn, *np; struct device_node *ep = NULL; struct device_node *rparent = NULL; struct device_node *rport = NULL; @@ -177,18 +201,7 @@ of_get_coresight_platform_data(struct device *dev, } while (ep); } - dn = of_parse_phandle(node, "cpu", 0); - for_each_possible_cpu(cpu) { - np = of_cpu_device_node_get(cpu); - found = (dn == np); - of_node_put(np); - if (found) - break; - } - of_node_put(dn); - - /* Affinity to CPU0 if no cpu nodes are found */ - pdata->cpu = found ? cpu : 0; + pdata->cpu = of_coresight_get_cpu(node); return pdata; } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index bf0aa50..d950dad 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -263,10 +263,13 @@ static inline int coresight_timeout(void __iomem *addr, u32 offset, #endif #ifdef CONFIG_OF +extern int of_coresight_get_cpu(const struct device_node *node); extern struct coresight_platform_data * of_get_coresight_platform_data(struct device *dev, const struct device_node *node); #else +static inline int of_coresight_get_cpu(const struct device_node *node) +{ return 0; } static inline struct coresight_platform_data *of_get_coresight_platform_data( struct device *dev, const struct device_node *node) { return NULL; } #endif From patchwork Fri May 19 04:25:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 100155 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp141317qge; Thu, 18 May 2017 21:28:03 -0700 (PDT) X-Received: by 10.84.237.1 with SMTP id s1mr8983833plk.157.1495168083683; Thu, 18 May 2017 21:28:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495168083; cv=none; d=google.com; s=arc-20160816; b=KkAvaW8Zl2hGlcUXCrpPAbT87wV/Xy/ZZOpIeNXN8pUHTfyvuwzMgIYMEcrbLTrl9N bW3sAw0ROcNi6i/LbqRZc+4zolT4Sm1dCcs0E04PmEpgA1MbDzPApsT6jMsIgdze5/1H 1n18c89fjaEqw9Iun4dfTtGKslaxXcKgGy5e090qXq5VN0NlUK+ZToNM9zTg94GJLHyo Ca8cK85bcj02y7/dzCd2jOBhyEulqWmXI+gEEOY+EqSqSih8Q9910FURjQmV7Uv9ZNTT h6mYx1isNT0nlrRoLH5yhc1D1UqBUlnihPfnIfha20d/q2soCC9c69/ySR9H/Q/8zRFR Sk6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=qtlRKwqcMiC8NKiU3cbHWNppElMAQKRitr5QiIESGlg=; b=gTOx2gv8URbpsv1wVIwGvyUif8xHngxm8MMP/csvw0XYbxJjZXbH5BHdMzIlQpYLAU B232ChQqCjv9LQawl5RE+U5dUMMtyehocs1ZZcI1INan5FffRSOZwSNuvVXNxjCcsF9K tqxhIUkUyuZg/O0QNvTs4Rk0MpqREj4wmzef3HlDc1XA8X3vYMU/mlzHnRiUWIM6bLvY vl0FL786Gj0V0eDUkF1JmrRpbP1yKW6BY5CIR3N8KNufMihhPxmbSo4/3SXnlnuL2T8A D01dmm4gQX4HwqubEAxgdf3VE39yovHmXAxSRfnLpJ55FlPuCiEiSX7ArKS7O/E8XQ31 2JbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[106.186.117.108]) by smtp.gmail.com with ESMTPSA id c29sm5823259pfj.101.2017.05.18.21.27.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 21:27:47 -0700 (PDT) From: Leo Yan To: Jonathan Corbet , Mathieu Poirier , Rob Herring , Mark Rutland , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Catalin Marinas , Will Deacon , Wei Xu , Andy Gross , David Brown , Greg Kroah-Hartman , Suzuki K Poulose , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Stephen Boyd , Mike Leach Cc: Leo Yan , Mathieu Poirier Subject: [PATCH v10 10/10] arm64: dts: juno: Add Coresight CPU debug nodes Date: Fri, 19 May 2017 12:25:57 +0800 Message-Id: <1495167957-14923-11-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> References: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Suzuki K Poulose Add Coresight CPU debug nodes for Juno r0, r1 & r2. The CPU debug areas are mapped at the same address for all revisions, like the ETM, even though the CPUs have changed from r1 to r2. Cc: Sudeep Holla Cc: Leo Yan Cc: Mathieu Poirier Cc: Liviu Dudau Signed-off-by: Suzuki K Poulose --- arch/arm64/boot/dts/arm/juno-base.dtsi | 54 ++++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++++++++++++++ arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++++++++++++++ arch/arm64/boot/dts/arm/juno.dts | 24 +++++++++++++++ 4 files changed, 126 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index bfe7d68..784a80a 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -216,6 +216,15 @@ }; }; + cpu_debug0: cpu_debug@22010000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0x22010000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + funnel@220c0000 { /* cluster0 funnel */ compatible = "arm,coresight-funnel", "arm,primecell"; reg = <0 0x220c0000 0 0x1000>; @@ -266,6 +275,15 @@ }; }; + cpu_debug1: cpu_debug@22110000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0x22110000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + etm2: etm@23040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x23040000 0 0x1000>; @@ -280,6 +298,15 @@ }; }; + cpu_debug2: cpu_debug@23010000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0x23010000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + funnel@230c0000 { /* cluster1 funnel */ compatible = "arm,coresight-funnel", "arm,primecell"; reg = <0 0x230c0000 0 0x1000>; @@ -344,6 +371,15 @@ }; }; + cpu_debug3: cpu_debug@23110000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0x23110000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + etm4: etm@23240000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x23240000 0 0x1000>; @@ -358,6 +394,15 @@ }; }; + cpu_debug4: cpu_debug@23210000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0x23210000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + etm5: etm@23340000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x23340000 0 0x1000>; @@ -372,6 +417,15 @@ }; }; + cpu_debug5: cpu_debug@23310000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0x23310000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + replicator@20120000 { compatible = "qcom,coresight-replicator1x", "arm,primecell"; reg = <0 0x20120000 0 0x1000>; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index 0e8943a..aed6389 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -281,3 +281,27 @@ &stm_out_port { remote-endpoint = <&csys1_funnel_in_port0>; }; + +&cpu_debug0 { + cpu = <&A57_0>; +}; + +&cpu_debug1 { + cpu = <&A57_1>; +}; + +&cpu_debug2 { + cpu = <&A53_0>; +}; + +&cpu_debug3 { + cpu = <&A53_1>; +}; + +&cpu_debug4 { + cpu = <&A53_2>; +}; + +&cpu_debug5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index 405e2fb..b39b6d6 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -281,3 +281,27 @@ &stm_out_port { remote-endpoint = <&csys1_funnel_in_port0>; }; + +&cpu_debug0 { + cpu = <&A72_0>; +}; + +&cpu_debug1 { + cpu = <&A72_1>; +}; + +&cpu_debug2 { + cpu = <&A53_0>; +}; + +&cpu_debug3 { + cpu = <&A53_1>; +}; + +&cpu_debug4 { + cpu = <&A53_2>; +}; + +&cpu_debug5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index 0220494..c9236c4 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -268,3 +268,27 @@ }; }; }; + +&cpu_debug0 { + cpu = <&A57_0>; +}; + +&cpu_debug1 { + cpu = <&A57_1>; +}; + +&cpu_debug2 { + cpu = <&A53_0>; +}; + +&cpu_debug3 { + cpu = <&A53_1>; +}; + +&cpu_debug4 { + cpu = <&A53_2>; +}; + +&cpu_debug5 { + cpu = <&A53_3>; +};