From patchwork Fri Sep 21 10:21:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147188 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp627526ljw; Fri, 21 Sep 2018 03:22:49 -0700 (PDT) X-Google-Smtp-Source: ANB0VdY1kO7YMCD+k6jYXzUqZ7UEnrUMGSU7Hn5JQTsUEQDnn4IqQdDGxLz0YqXZiiFgsO8CjJBG X-Received: by 2002:a63:3dc6:: with SMTP id k189-v6mr40682406pga.191.1537525369400; Fri, 21 Sep 2018 03:22:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525369; cv=none; d=google.com; s=arc-20160816; b=AMQeAx4dMzb0RFAO1z/uRLssn4nipubqpu7x1NKnGyrWml24jPIyX09SgsBd5Ftuiz W767GU8baqHWx3EgiaMB/MFVcfGvT8ey8zBxec/236gA/ue/9lM1ImUv3/6u1iSMCoSy vGrkmfZzO/4dLEPg6KJdDuPn2F77+PgE0WEudeKwKCPdf0h4aGqwReY0M2tmELEoB5dV gQ0VlCIknGjRXrCHByymN0HCv2lYMbn/l4DEZIVhLV5+RYKzI4+2Oi+ofxic0I08ikXK 9V31H5CLFoMKauUHfMRO/HqRhVEKQQHOILv9zF5i2zi7fHgfJhKFkQLCS4thgTmpXBY1 4isA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=iBGFjwERlyNXfssV0mhi5P70SxiWNRCvnKhKGvOqAU0=; b=Qv2ujAY4Ho1GLK5AIJNf7BlrgsJSEZNy/s9lboxhXvKrEAVtIu3/DPPQoSYurCHmWt 2DbNkF+YkK976zzjC3swIFuYQYGJB2xNoErw2jlkr29XGrhEWn2J3D0jKQVapodEio3/ pDw8RAwFEGTfDWUbiBIGZgIaPV93XC1v8igUgSG2mP9EFapkVwdtbNy4v3Nie8MlM3wa L9V4PpMSznFiURrn3xQtWG3t59qR1NH/UYybXXBZesXjyfjflBMI/VUf9iJEkpgmv8Td KU9h6I9dcLqkXRcqH5iUk4fcMvEz391Y+3znSgCJb4sFKCad+oL3Y6nIslbsO8oNtQ9T qi1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="bUPipoG/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t71-v6si1571830pgd.352.2018.09.21.03.22.49; Fri, 21 Sep 2018 03:22:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="bUPipoG/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727681AbeIUQK7 (ORCPT + 6 others); Fri, 21 Sep 2018 12:10:59 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:34914 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727392AbeIUQK7 (ORCPT ); Fri, 21 Sep 2018 12:10:59 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAMOfM030289; Fri, 21 Sep 2018 05:22:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525344; bh=iBGFjwERlyNXfssV0mhi5P70SxiWNRCvnKhKGvOqAU0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bUPipoG/GPtwq55FxNqNDgbtTZGWgFlGmC9ZtO9hZw4DmQYrDP7V902xkJZuDL/N8 OUF/vqYlzPuYnWyHaNM+RBfPJtxLEDU2X4a8+XULSZykyhkBFvNoWSOBJEyDtAEOn+ SVTefYQGlUn6r04YzUAHQQZYEixLhoM9T39gt1Lo= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMOv4017403; Fri, 21 Sep 2018 05:22:24 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:22:24 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:22:24 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEt5032280; Fri, 21 Sep 2018 05:22:20 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 01/40] PCI: keystone: Use quirk to limit MRRS for K2G Date: Fri, 21 Sep 2018 15:51:16 +0530 Message-ID: <20180921102155.22839-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PCI controller in K2G also has a limitation that memory read request size (MRRS) must not exceed 256 bytes. Use the quirk to limit MRRS (added for K2HK, K2L and K2E) for K2G as well. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e88bd221fffe..7d43e10a03b0 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -36,6 +36,7 @@ #define PCIE_RC_K2HK 0xb008 #define PCIE_RC_K2E 0xb009 #define PCIE_RC_K2L 0xb00a +#define PCIE_RC_K2G 0xb00b #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) @@ -50,6 +51,8 @@ static void quirk_limit_mrrs(struct pci_dev *dev) .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, { 0, }, }; From patchwork Fri Sep 21 10:21:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147192 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp628158ljw; Fri, 21 Sep 2018 03:23:34 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbX4KbQq9F50bJX/WjpR3EEYyhF277DfE9LNjqxYTobGbxdSx2LXjqzeaBY1sStJRtxpIAu X-Received: by 2002:a65:4043:: with SMTP id h3-v6mr40528272pgp.207.1537525414420; Fri, 21 Sep 2018 03:23:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525414; cv=none; d=google.com; s=arc-20160816; b=elvOopSCqeRbXPGVRrZef/fLDTmqgs8m6DTxx6bJ19nViWN5L2Mhawbm4BWfPoWXfN DGGRyeT0+pYpUW4pNWkd0n0b37cpxt3WDsNPKc4Rloid4S6Jkc0IqZRUWgDkbZzNdvGe bBsv/BbhjGalsF4UPiprC6qdOSYkfdQ+b5HfIXhBsAtmAnOhhBIWYi7oWUotjwug4M7p EpHX/c77KePXJ5xonKRagJIgNgM7nG35mHLT18AG8DMHXyFT6b5vPrshPss8FPzv+c/L fToRK/bmlEEmivnbPh33pdUbQgpOP0JG9BNL713rAVOi5fep4blrBQELaqwnVn+5LHxu QJAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=CywUeyvOfH1tI2pu+soQCfVILjgvnQbtM9JU52QtGcs=; b=HGOq+dOefQNWx9DMDGhud+eGwIfIvIUEWOkqr32Jv88KLPrvgU94/0nIHbOX+n8kNK /FDzgNhSm57l1TW1rZfqE7TDLpJkSN6ZQqNxL1ERaGhok7WC30jjwi/72cY8lJk0zbaa zmu9Bednp1KZdy+ytIFfjebqISEkpASWysmXcEbqbRuDg5wCRUlVfFJDDGhLfNyfJwVU BCPY1AYwW70zYF5Hrj6R7nFkcOzwwmFaKD1n9UEvBftJIa4EHhkelzbEaJhoS+pCGx5D vPmyTEb9LCUc96GYSHarKVrxT0HIrEX9l7NnEZ7ZIJA854g8RoSwXa+RUlacGLARNhn9 ZC1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="wFwYP/Xk"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p62-v6si15307057pgp.648.2018.09.21.03.23.34; Fri, 21 Sep 2018 03:23:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="wFwYP/Xk"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389704AbeIUQLp (ORCPT + 6 others); Fri, 21 Sep 2018 12:11:45 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51284 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727554AbeIUQLp (ORCPT ); Fri, 21 Sep 2018 12:11:45 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAMTkQ032962; Fri, 21 Sep 2018 05:22:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525349; bh=CywUeyvOfH1tI2pu+soQCfVILjgvnQbtM9JU52QtGcs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wFwYP/Xk3sz1StpX7ghnIfAMb6wOVmYxfgydU/ffKXrc5CHFvc+XtY218mMjYpW2P ixlc/U49cJRNlSd/ODJwNoIHOKZMa2k9k2cqVl65r/4CXyh/+bt2eIYNvQkKQpcc+V QgNFsarw+ks/LgE2sXeI+EoiMtML4+VbosiJxlpI= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMTw4017448; Fri, 21 Sep 2018 05:22:29 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:22:29 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:22:29 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEt6032280; Fri, 21 Sep 2018 05:22:24 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 02/40] PCI: keystone: Use quirk to set MRRS for PCI host bridge Date: Fri, 21 Sep 2018 15:51:17 +0530 Message-ID: <20180921102155.22839-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Reuse the already existing quirk to set MRRS for PCI host bridge instead of explicitly setting MRRS in ks_pcie_host_init. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 37 +++++++++-------------- 1 file changed, 15 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 7d43e10a03b0..5d9c5d199ada 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -43,7 +43,7 @@ static void quirk_limit_mrrs(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; - struct pci_dev *bridge = bus->self; + struct pci_dev *bridge; static const struct pci_device_id rc_pci_devids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, @@ -57,7 +57,7 @@ static void quirk_limit_mrrs(struct pci_dev *dev) }; if (pci_is_root_bus(bus)) - return; + bridge = dev; /* look for the host bridge */ while (!pci_is_root_bus(bus)) { @@ -65,18 +65,19 @@ static void quirk_limit_mrrs(struct pci_dev *dev) bus = bus->parent; } - if (bridge) { - /* - * Keystone PCI controller has a h/w limitation of - * 256 bytes maximum read request size. It can't handle - * anything higher than this. So force this limit on - * all downstream devices. - */ - if (pci_match_id(rc_pci_devids, bridge)) { - if (pcie_get_readrq(dev) > 256) { - dev_info(&dev->dev, "limiting MRRS to 256\n"); - pcie_set_readrq(dev, 256); - } + if (!bridge) + return; + + /* + * Keystone PCI controller has a h/w limitation of + * 256 bytes maximum read request size. It can't handle + * anything higher than this. So force this limit on + * all downstream devices. + */ + if (pci_match_id(rc_pci_devids, bridge)) { + if (pcie_get_readrq(dev) > 256) { + dev_info(&dev->dev, "limiting MRRS to 256\n"); + pcie_set_readrq(dev, 256); } } } @@ -264,7 +265,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - u32 val; ks_pcie_establish_link(ks_pcie); ks_dw_pcie_setup_rc_app_regs(ks_pcie); @@ -275,13 +275,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) /* update the Vendor ID */ writew(ks_pcie->device_id, pci->dbi_base + PCI_DEVICE_ID); - /* update the DEV_STAT_CTRL to publish right mrrs */ - val = readl(pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); - val &= ~PCI_EXP_DEVCTL_READRQ; - /* set the mrrs to 256 bytes */ - val |= BIT(12); - writel(val, pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); - /* * PCIe access errors that result into OCP errors are caught by ARM as * "External aborts" From patchwork Fri Sep 21 10:21:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147190 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp627788ljw; Fri, 21 Sep 2018 03:23:08 -0700 (PDT) X-Google-Smtp-Source: ANB0VdattiRfsHmNooRU2GzMn2q35lxmg0dOvwaqqzbnWGYiaKNXfxqRjHizJg6I9Urykc4H5i4/ X-Received: by 2002:a62:398c:: with SMTP id u12-v6mr46394143pfj.9.1537525388846; Fri, 21 Sep 2018 03:23:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525388; cv=none; d=google.com; s=arc-20160816; b=Uem2mKHX9YeBX9v4eaF/1EEbo2tKAM2LwDBn/nuUHvBAP22EyNZ4vrNqqcfJg4h8jX bNRVDNsPP2hGnN6b+YVptIPmQdlxIAYSmh+ocN8g5WlCxZ6DCwM1R86EWhoezjZ6VXSF uKRh2fsj4lDpJvOJkxBjNuMeXuAJAKd0W/mEZIka/0L1VhQgd8vdazXpovGq58xAO/cj 9QT2JJcv2YHGh0lRYWQ9OyrmzX7YlCSIWZpHj0pxXWCozkDTDe3AOc8OfHUgpzPaUKfh PNd+uoi6iAn6lbLluasWy6YWfScbLSwer51RadtiX4SZJ8kWlFt0KlGTBgZre/NWX0h0 wWxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=RX26ORmS1FgERqoIVtPaM64hJYygEP3WZMWAU+e+Q4M=; b=m2I9GWG7+J9bU+KxLdAQ8BepACp+oq9aa3hH8US0JU1tMxj1wPwjIiBxHVhifnrO5b IZZmk13zEhN/ANVqXuoZ7Ch1ImoAZXCrhFD+PSwFbKKNOv2qMV6bpY9lI2Wthlg9HcOJ WRLWolTcAbQqvo3vBhSHsS4ACq4xIxuQz0AsiYsQgYo5nnQdv47R1+2Ur451+gfsUeom t5ue5zoPoQwCSw6UnLzxyEz6n99UDjF/QWqCIPWBcfcMP0NpwV0t3ohOedWRhyNjCqmp 6nGftt3Wo6WpK1ER5b/pukxFqcKYaul34tXUjrT64BcPSjXOB0T0g8cAXSUHVCsX9yLE sncA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=t7VKd7l1; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x18-v6si26806725pll.88.2018.09.21.03.23.08; Fri, 21 Sep 2018 03:23:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=t7VKd7l1; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389626AbeIUQLT (ORCPT + 6 others); Fri, 21 Sep 2018 12:11:19 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51240 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389547AbeIUQLT (ORCPT ); Fri, 21 Sep 2018 12:11:19 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAMYjT032972; Fri, 21 Sep 2018 05:22:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525354; bh=RX26ORmS1FgERqoIVtPaM64hJYygEP3WZMWAU+e+Q4M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=t7VKd7l1AKf2hsBrhgdLGMDZgeSYO8w490xa6AXszzTroZ9MtxVlTvMsAREIxea7W k4d43s32aafdnkMWRCBgsiDa8muQidL2TQFxV0bv0SjosVmcu6yGg1zORgWzzQynnI FvAB6kNNPCGYzRL5OMUJtCb5Zbi1R+P+MiYG3Dr0= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMXiP028864; Fri, 21 Sep 2018 05:22:33 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:22:33 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:22:34 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEt7032280; Fri, 21 Sep 2018 05:22:29 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 03/40] PCI: keystone: Move dw_pcie_setup_rc out of ks_pcie_establish_link() Date: Fri, 21 Sep 2018 15:51:18 +0530 Message-ID: <20180921102155.22839-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org No functional change. Move dw_pcie_setup_rc out of ks_pcie_establish_link() so that ks_pcie_establish_link only does what it is supposed to do. This will be required for adding EP support which will invoke ks_pcie_establish_link as part of start_link ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 5d9c5d199ada..fec46cfccba5 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -90,8 +90,6 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) struct device *dev = pci->dev; unsigned int retries; - dw_pcie_setup_rc(pp); - if (dw_pcie_link_up(pci)) { dev_info(dev, "Link already up\n"); return 0; @@ -266,6 +264,8 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + dw_pcie_setup_rc(pp); + ks_pcie_establish_link(ks_pcie); ks_dw_pcie_setup_rc_app_regs(ks_pcie); ks_pcie_setup_interrupts(ks_pcie); From patchwork Fri Sep 21 10:21:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147220 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp630567ljw; Fri, 21 Sep 2018 03:26:13 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZyrxzhWpeRJerkmTGlhlCvMTpIz/9PYuuU+5SFoFIP3nmBaCY8wqK6bQJcZp0ze2/Fvzxh X-Received: by 2002:a65:4d42:: with SMTP id j2-v6mr40103713pgt.232.1537525573857; Fri, 21 Sep 2018 03:26:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525573; cv=none; d=google.com; s=arc-20160816; b=T5T5DKZAXhsjJ1N7eTJq9ntz062x1TicG58AFVrK2Ee/lyuCIigN/h/JP4ttz2Uus8 BqSD5yguCg1/XSiLGyEpYS++ahcHkfO7viGW3Nf2G2oCxLlZ7N70ErGRuichJ4jxqag1 N4EN3HdHa4BxUpmGMj0VdEJ3KT1Qz7gZkIFEkcQ3FxyTy1NpzxhwSjVEjEFX36N3Doer Ko+OMm8gg8df6QT9PTCQ/VAa6M+aCMwXRjeQS7xI4ACBR+f+MqRSAmehlGT7nKZUrFa8 Uwb5fSDyRADJckU9zKV4tb//t7+2XA4GGEBE2+YeGdPXVgFFwnAukev317cAJGNjw4MN Rz0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=oDF6ndAYJvQk5lqs0pyCrinasCIrID1DOTXjY2ayVww=; b=lWfHo3upnfKcoQiaq8UKLkh7soOSXU9oX9H8OWEzyUxdJTJ782qd6ZLOEfWvdYHnV6 G+aoP4UBvdvCgbjawCT3Bi7IC+JA4EMf4j1aiBF5xtS1RoPu+7MFMylrhAYObfkArIHb tlzbw7RQ0gI7vM9IJygFbTHId7PV8Un9kqCQzxFLTG8ZfJRTFkRO2OVvsiJa3TiU5Snh B/z0zsR2dqpbkukbozKdKCLXMQMRojNBdYvs8sf5qbbjIa6aJAl6vMekaPUZMXUNPULg UHcUuZMReKjmZiZgaJa4sH/zRXzU5yM02RpIHECTWIz8MrExnJZH9gm7PJ5D2jjcFame H99Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bxhKx+6y; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s17-v6si26258302pge.99.2018.09.21.03.26.13; Fri, 21 Sep 2018 03:26:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bxhKx+6y; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390488AbeIUQOZ (ORCPT + 6 others); Fri, 21 Sep 2018 12:14:25 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:54720 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeIUQOY (ORCPT ); Fri, 21 Sep 2018 12:14:24 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LANnA1032939; Fri, 21 Sep 2018 05:23:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525429; bh=oDF6ndAYJvQk5lqs0pyCrinasCIrID1DOTXjY2ayVww=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bxhKx+6y89OzMZGYuHtzWPoV5lsR1NRkqPJTDy6pzxhxSt8B60pbKD93LOfvQaq4m 3nWggHxBSbjAoR7kd7TMXv75vOkeZu1xGk+cbpae7kfJU0jSne+Dxb9FU2KEty4GXJ 7qbDt5XdprYqDR238FiAsGpGwuMkPYXtKNAl03qw= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LANn7P018958; Fri, 21 Sep 2018 05:23:49 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:23:48 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:23:48 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtN032280; Fri, 21 Sep 2018 05:23:44 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 19/40] PCI: keystone: Cleanup set_dbi_mode and get_dbi_mode Date: Fri, 21 Sep 2018 15:51:34 +0530 Message-ID: <20180921102155.22839-20-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org No functional change. Use BIT() macro for DBI_CS2 and cleanup set_dbimode and get_dbi_mode Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d5304c4a1eb5..728b1e0db314 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -40,7 +40,7 @@ #define LTSSM_EN_VAL BIT(0) #define LTSSM_STATE_MASK 0x1f #define LTSSM_STATE_L0 0x11 -#define DBI_CS2_EN_VAL 0x20 +#define DBI_CS2 BIT(5) #define OB_XLAT_EN_VAL BIT(1) /* Application registers */ @@ -214,11 +214,12 @@ static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) u32 val; val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - ks_pcie_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val); + val |= DBI_CS2; + ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); do { val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - } while (!(val & DBI_CS2_EN_VAL)); + } while (!(val & DBI_CS2)); } /** @@ -232,11 +233,12 @@ static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) u32 val; val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - ks_pcie_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val); + val &= ~DBI_CS2; + ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); do { val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - } while (val & DBI_CS2_EN_VAL); + } while (val & DBI_CS2); } static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, From patchwork Fri Sep 21 10:21:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147213 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629645ljw; Fri, 21 Sep 2018 03:25:14 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaCP8pK/QXNyDoX5CFbQDpx+61bhs8cDS0Agc66xKgvTHSyxD2HlAUz6O4znvHnZP64xaq2 X-Received: by 2002:a17:902:3a3:: with SMTP id d32-v6mr43649953pld.294.1537525514550; Fri, 21 Sep 2018 03:25:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525514; cv=none; d=google.com; s=arc-20160816; b=tq+uzKpbQaMHwG6UXPxvE0uLh0hvo5ItTDQAX4f9JvYiBpzRp86/1Wz2VTgODiWx6d ycYoLHGtr/EGaYS7QBUIf6ZrMh3Z6ttVORu7TILQDaUqW0XvtH9YaOSUWqB5dl6RGQcy oGUP8nnDLcSsi9+Xf4Kx8uhysQZ9bxywsrFiQE7kGAhsXL/zcn19s1kodWtCoruCrFou B70k4m8y89XJtG5lPctfIGrvi+zXMUFH6MLT0XvjPq75kolFwvaAkpI5BAxWSana6hVK HRCYcTvDEmM5HwGqBwEl85VQvKqhAu3BANVn4j9OHL9KjOgUJTnNYt4AOx6HEEZadZWO Jthg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=MdVZEmvM9U35LgLquwnypWHuyVsV6bB8cMSesoTOxEQ=; b=RBuFvy8H0C0Oi43rYN17YVapGYtYmr3ZwnNvlkJAJ354j55lOU/lKjZnJt5HiP8Nzs H4IeD76yDjSICfBsJhzfoayu9TL5tMkMnkzy9Zab5QnO4JfDRWSnONs+oI37LDsqdaIJ 2tZHSluUMvdHRimIVD8JAEZcGxvMkFSYCrxXFqy1AfTHmOA/FqmRIhUQ2CFEBj1T29r3 z53qrf12xepmja2kVR0FT5iDrePgCIVkfDbMwoa3QE/htxJqCTiWPogU6bz19jQgzdsV zlEGe2eA8YvpdXADEOtCtMIoCMPf8C32XBTeJcDGTp2qIgg4XK5asrQlF7DOk8n9fiGx sPKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gwXEhNSA; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m23-v6si7702139pgn.603.2018.09.21.03.25.14; Fri, 21 Sep 2018 03:25:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gwXEhNSA; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390243AbeIUQNZ (ORCPT + 6 others); Fri, 21 Sep 2018 12:13:25 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51516 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeIUQNY (ORCPT ); Fri, 21 Sep 2018 12:13:24 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAOmZY033499; Fri, 21 Sep 2018 05:24:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525488; bh=MdVZEmvM9U35LgLquwnypWHuyVsV6bB8cMSesoTOxEQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gwXEhNSAC61pBkIuwuy7AcVxCQ9aw41u02U0M8FpOa2+GdyzZwgcrrbH3PhlEmGS3 7409X1DNHzKdedZ4L2r2VdVn7IInbRYmwPbQaZUFxB33kyb4s5fklqbiLYfsel9bIo wNDmQdrBa0OZ0a36+nlbWiMdzfFatCIIYORYPyn4= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAOmwM020534; Fri, 21 Sep 2018 05:24:48 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:24:48 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:24:48 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEta032280; Fri, 21 Sep 2018 05:24:43 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 32/40] phy: core: Invoke pm_runtime_get_*/pm_runtime_put_* before invoking reset callback Date: Fri, 21 Sep 2018 15:51:47 +0530 Message-ID: <20180921102155.22839-33-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PHY drivers may try to access PHY registers in the ->reset() callback. Invoke phy_pm_runtime_get_sync() before invoking the ->reset() callback so that the PHY drivers don't have to enable clocks by themselves before accessing PHY registers. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-core.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.1 diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index 35fd38c5a4a1..b2f863f0866e 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -384,10 +384,16 @@ int phy_reset(struct phy *phy) if (!phy || !phy->ops->reset) return 0; + ret = phy_pm_runtime_get_sync(phy); + if (ret < 0 && ret != -ENOTSUPP) + return ret; + mutex_lock(&phy->mutex); ret = phy->ops->reset(phy); mutex_unlock(&phy->mutex); + phy_pm_runtime_put(phy); + return ret; } EXPORT_SYMBOL_GPL(phy_reset); From patchwork Fri Sep 21 10:21:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147214 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629689ljw; Fri, 21 Sep 2018 03:25:17 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbQBJQFtgev/Bw/ecmM3pSyqU4GUpXPUorm94+ssJoOQdugP2pbaHkFqWwh7FED0NTcuYv6 X-Received: by 2002:a17:902:9a8a:: with SMTP id w10-v6mr42838914plp.14.1537525517626; Fri, 21 Sep 2018 03:25:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525517; cv=none; d=google.com; s=arc-20160816; b=WY7PjKnjts7ZUmzbLQBtOA0iuxfYiynO6rinYHiNro7gdCBz+cBKuroQ1W/ioGHnXE PdxZv83rR0vwPk03S3GSuRMXBQtlnJm50o89sAF+/3j28E1IqjLK3QlHJ47EK7T6TaBY mPGU9iJfxvF+xmVdVCcYPe+hkIPkJ80/4KJ7wz8iU4QNfgJ256YNLbOFcwxx6N/hdjfz GMrGDSonqSdp5JN+nd6vbiDRy0FZl9BWIUnw8Js99u+EHZ+GwhrdMvAF+lCywkuhWT6w asE6yNCLR7mmWY9O7gVVKE41A95rLl3G2QcjZkKMvNptSx7dp3lK4dEojsxb8IDPlilD 7I8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GUh9FXpXcAI6DF2YdGQGzCD19/FTKxOn8DpjbDpT3V4=; b=dJUIlvC92xNQ/PY/uAetVuenLiTkp5EEAuXYXXeoojfI3/dXrqCU/l8lLPTT10Qvou 6WV2PrWeFph81XMQHqWP6Ku8YT5LUGVYP2v+EtZsxJuZ2lC/nazfWTDZfZzR50DenWh2 7Xn0l1qAEmAxAHndVhMa0hFviHFPg6YsiAlJaFVzWeNJ7VE9yl+YzGpq8zxjVg1n+qj0 phzSQQZ5nNWPJjSFmNKFsyPe3dT9gEGj4IYadSSZRHyuyCg18S8AF2OJewQ6JLy3fXB+ 7v+xyRNnmFzzLvakjeMwmZBqkFMcbLyIC/SIAFfl+P74yf94zaCdr72OQSVx2DQTbHCz LpKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nLI5oluz; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id cc7-v6si29192674plb.97.2018.09.21.03.25.17; Fri, 21 Sep 2018 03:25:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nLI5oluz; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390258AbeIUQN2 (ORCPT + 6 others); Fri, 21 Sep 2018 12:13:28 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51528 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeIUQN2 (ORCPT ); Fri, 21 Sep 2018 12:13:28 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAOqPJ033517; Fri, 21 Sep 2018 05:24:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525492; bh=GUh9FXpXcAI6DF2YdGQGzCD19/FTKxOn8DpjbDpT3V4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nLI5oluz/G+JpsVtfD17EYwfJoTZTmQ+f+B4Lbar/ietuTbdXiSHBi/7zn/qGvffA 24ASQAeLY7VwVc+Q+0HLMYgveroCwr6wwKwRbC74+4xQ5WX6ZsxI2M394uvy3ikpcM RU3noESynzBWyQs0Hj0ehFZtC9fsx0Uj+XQZ1Yrw= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAOqGf031468; Fri, 21 Sep 2018 05:24:52 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:24:52 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:24:52 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtb032280; Fri, 21 Sep 2018 05:24:48 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 33/40] dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC Date: Fri, 21 Sep 2018 15:51:48 +0530 Message-ID: <20180921102155.22839-34-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org AM654x has two SERDES instances. Each instance has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The left and right input reference clock of SERDES0 and SERDES1 respectively are connected to the SoC clock. In the case of two lane SERDES personality card, the left input of SERDES1 is connected to the right output of SERDES0 in a chained fashion. See section "Reference Clock Distribution" of AM65x Sitara Processors TRM (SPRUID7 – April 2018) for more details. Add dt-binding documentation in order to represent all these different configurations in device tree. Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/ti-phy.txt | 77 +++++++++++++++++++ include/dt-bindings/phy/phy-am654-serdes.h | 13 ++++ 2 files changed, 90 insertions(+) create mode 100644 include/dt-bindings/phy/phy-am654-serdes.h -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt index 57dfda8a7a1d..fc2fff6b2c37 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt @@ -132,3 +132,80 @@ sata_phy: phy@4a096000 { syscon-pllreset = <&scm_conf 0x3fc>; #phy-cells = <0>; }; + + +TI AM654 SERDES + +Required properties: + - compatible: Should be "ti,phy-am654-serdes" + - reg : Address and length of the register set for the device. + - reg-names: Should be "serdes" which corresponds to the register space + populated in "reg". + - #phy-cells: determine the number of cells that should be given in the + phandle while referencing this phy. Should be "2". The 1st cell + corresponds to the phy type (should be one of the types specified in + include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes + lane function. + If SERDES0 is referenced 2nd cell should be: + 0 - USB3 + 1 - PCIe0 Lane0 + 2 - ICSS2 SGMII Lane0 + If SERDES1 is referenced 2nd cell should be: + 0 - PCIe1 Lane0 + 1 - PCIe0 Lane1 + 2 - ICSS2 SGMII Lane1 + - clocks: List of clock-specifiers representing the input to the SERDES. + Should have 3 items representing the left input clock, external + reference clock and right input clock in that order. + - clock-output-names: List of clock names for each of the clock outputs of + SERDES. Should have 3 items for CMU reference clock, + left output clock and right output clock in that order. + - assigned-clocks: As defined in + Documentation/devicetree/bindings/clock/clock-bindings.txt + - assigned-clock-parents: As defined in + Documentation/devicetree/bindings/clock/clock-bindings.txt + - #clock-cells: Should be <1> to choose between the 3 output clocks. + Defined in Documentation/devicetree/bindings/clock/clock-bindings.txt + + The following macros are defined in dt-bindings/phy/phy-am654-serdes.h + for selecting the correct reference clock. This can be used while + specifying the clocks created by SERDES. + => AM654_SERDES_CMU_REFCLK + => AM654_SERDES_LO_REFCLK + => AM654_SERDES_RO_REFCLK + + - mux-controls: phandle to the multiplexer + +Example: + +Example for SERDES0 is given below. It has 3 clock inputs; +left input reference clock as indicated by <&k3_clks 153 4>, external +reference clock as indicated by <&k3_clks 153 1> and right input +reference clock as indicated by <&serdes1 AM654_SERDES_LO_REFCLK>. (The +right input of SERDES0 is connected to the left output of SERDES1). + +SERDES0 registers 3 clock outputs as indicated in clock-output-names. The +first refers to the CMU reference clock, second refers to the left output +reference clock and the third refers to the right output reference clock. + +The assigned-clocks and assigned-clock-parents is used here to set the +parent of left input reference clock to MAINHSDIV_CLKOUT4 and parent of +CMU reference clock to left input reference clock. + +serdes0: serdes@900000 { + compatible = "ti,phy-am654-serdes"; + reg = <0x0 0x900000 0x0 0x2000>; + reg-names = "serdes"; + #phy-cells = <2>; + power-domains = <&k3_pds 153>; + clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, + <&serdes1 AM654_SERDES_LO_REFCLK>; + clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", + "serdes0_ro_refclk"; + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; + ti,serdes-clk = <&serdes0_clk>; + mux-controls = <&serdes_mux 0>; + #clock-cells = <1>; + status = "disabled"; +}; diff --git a/include/dt-bindings/phy/phy-am654-serdes.h b/include/dt-bindings/phy/phy-am654-serdes.h new file mode 100644 index 000000000000..e8d901729ed9 --- /dev/null +++ b/include/dt-bindings/phy/phy-am654-serdes.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for AM654 SERDES. + */ + +#ifndef _DT_BINDINGS_AM654_SERDES +#define _DT_BINDINGS_AM654_SERDES + +#define AM654_SERDES_CMU_REFCLK 0 +#define AM654_SERDES_LO_REFCLK 1 +#define AM654_SERDES_RO_REFCLK 2 + +#endif /* _DT_BINDINGS_AM654_SERDES */