From patchwork Fri May 19 08:15:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100163 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp201345qge; Fri, 19 May 2017 01:16:55 -0700 (PDT) X-Received: by 10.98.18.84 with SMTP id a81mr9215373pfj.188.1495181815643; Fri, 19 May 2017 01:16:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495181815; cv=none; d=google.com; s=arc-20160816; b=m2sKDHquvce9g9+u8JekDkRtWzDS2lxVKR7hV0QU53SynihsJH1mgL0JFw4ZGGQ0JV 7XnmHKfAh3/oolhfyFbad3KrUUV7rQ8LCG8Mof5nn/p629P2G6Y/PJCEktt/2MYF78ue x3nDFYUqKVlP/a0laDgaJD8eG7MutCgyXSKX4P0JV8kmv67cnqRDGb9t5MFwD+rVPOCY Tl7dXDDLzNYb53BbJD2ZXRAzI10e0d3su80GrjwDmDPNU1GISOcOOUuk4QyzRmith46l g/DeuP/mzD3I71L+iUg9DY5S6NGA3sJaqU2jhxbjfHDxINBTyCJlMezAgNKcR4NDfXfR sSpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=W8Pt2Fc+03TujXirgzZvON9JsUDqbZ1zUX6pb6HM5r0=; b=RfaHW4f8CkE328Cbl41Ee/PG+s+5D+d4zopPtbO2hgMJ2k0nyAULQSpDZ1bW786x9r LdCjutc45pO0ClDng5kn1qYay6R5mMhlAPCZeOF0JYUCS9zaZ60WX1eq+VEO6TqzX4C2 cTBbw77AJSjkItButO29WlpHoa4KMtnHK2utJ0kwR8x/x93+1nF8FCuIvply61QarjLt UNZDOL7t/BX1EP3ngydD/2sHANLvsHukhfnUdziHJ3unfHTSpijmj8H9Jh6qnpv2VlPx rQE2NGTR/EAa9z7lxbys6jx+Nhf3GAdNA/cdhH1NGR9mRP8e+n6EELLJsRAZ5PCLYpAp Sdqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b11si7607951pfl.131.2017.05.19.01.16.55; Fri, 19 May 2017 01:16:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752697AbdESIQh (ORCPT + 25 others); Fri, 19 May 2017 04:16:37 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:50183 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750761AbdESIQ3 (ORCPT ); Fri, 19 May 2017 04:16:29 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8FtYV024225; Fri, 19 May 2017 03:15:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181755; bh=5VKcseTBHaOSYn0mlFLPxEVWYxoq8LhuWX6endVOqxA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=btKAdhE+DEmr6R/k44JnZlxB/RDJ3VBVld30SuBYnCXwGlEe4h8GdGiHbKIR5I4Lp s/JXn8f54UU2pL5jSuAuW9EPMIxA8FatQXus2Z9+ZGhVKn/05KDhBmfddMLBhGEvDj PLZNRASiss0chqPkIVzGbKx7K/M6FIKWfOXudISw= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FtAJ025611; Fri, 19 May 2017 03:15:55 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:15:54 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQ9009185; Fri, 19 May 2017 03:15:51 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 02/41] mmc: host: omap_hsmmc: Separate setting voltage capabilities from bus power Date: Fri, 19 May 2017 13:45:02 +0530 Message-ID: <20170519081541.26753-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a separate function to set the voltage capabilities of the host controller. Voltage capabilities should be set only once during controller initialization but bus power can be changed every time there is a voltage switch and whenever a different card is inserted. This allows omap_hsmmc_conf_bus_power to be invoked every time there is a voltage switch. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- drivers/mmc/host/omap_hsmmc.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) -- 2.11.0 diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 2000aaa359c8..42954efe12f7 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -1809,25 +1809,34 @@ static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) return ret; } +static void omap_hsmmc_set_capabilities(struct omap_hsmmc_host *host) +{ + u32 val; + + val = OMAP_HSMMC_READ(host->base, CAPA); + + /* Only MMC1 supports 3.0V */ + if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) + val |= (VS30 | VS18); + else + val |= VS18; + + OMAP_HSMMC_WRITE(host->base, CAPA, val); +} + static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) { - u32 hctl, capa, value; + u32 hctl, value; /* Only MMC1 supports 3.0V */ - if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { + if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) hctl = SDVS30; - capa = VS30 | VS18; - } else { + else hctl = SDVS18; - capa = VS18; - } value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); - value = OMAP_HSMMC_READ(host->base, CAPA); - OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); - /* Set SD bus power bit */ set_sd_bus_power(host); } @@ -2134,6 +2143,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) mmc->pm_caps |= mmc_pdata(host)->pm_caps; + omap_hsmmc_set_capabilities(host); omap_hsmmc_conf_bus_power(host); host->rx_chan = dma_request_chan(&pdev->dev, "rx"); From patchwork Fri May 19 08:15:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100164 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp201348qge; Fri, 19 May 2017 01:16:56 -0700 (PDT) X-Received: by 10.98.18.157 with SMTP id 29mr8862348pfs.75.1495181816081; Fri, 19 May 2017 01:16:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495181816; cv=none; d=google.com; s=arc-20160816; b=VgD88M+ZsPUmkvdXHHYXbTvnaxVsNO9yINX8nKjhIITldoltcquCpnzANU0Rr2ZlCh NuEzJU0g2sWd7U6lNcJ6JumKAS7x8y3V3p1PN3fTRMhg+XKb1ZUGlUHTLkzFL1gFkGNl UFOkz8G/4he6lpPrOL/S8EsEqYllFtnw2aIBGxnWgMt0UZyDRosafhjlatXUEGAzqy0r UmB4Fo1Zd/K23P+fJB1+KRUVL7R1Fhc2xD3Q76AQLsZTNZ3LcjF9U8ptJ68JI4A7DTc1 Fnd7hAsLrQ1OpqO5gVZ3IsxhMs4r2I0jVCUh5ErH+NWIu1B91odTMial1pE/sHp709Tj AqVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=3LyaeN2ccQvT+ITPcdYvuBPD+Uu2DUZQh5L6uEzHj60=; b=j0hdML4XcHw2j9AIi7atEB+yVcPGiFiEfj6hS9Cvevqm/VK6I1o5GNal2hlwbFK9DH jVtCeQaoSEcnUkuqaXC5ln7bOMMzroareAFl2yJBD77RI9YhpaQeJTjZGO8fsOSq8eJJ qMSDfn//4issshepImRl4tJBdrbd+69qmoSo31qaDhbGGj2XO7ttcDzkW28TXe2j35+f u5wdCHi4hpAmDOFNF+ZHS12cVnzECxHbi2E0pRi7r6kuZkGtFuyFtlzrQPapTj1oUuDm N4BwoHnC15utJNdg/0mEHvDvFI2HTusF8zazax/fbrOpzBrfDnZCEuty5GOjGmts4utE TEQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b11si7607951pfl.131.2017.05.19.01.16.55; Fri, 19 May 2017 01:16:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752907AbdESIQq (ORCPT + 25 others); Fri, 19 May 2017 04:16:46 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:50202 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750761AbdESIQl (ORCPT ); Fri, 19 May 2017 04:16:41 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8G591024261; Fri, 19 May 2017 03:16:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181765; bh=pdZbiPDOay2/85oH5I3fDiX6jo2LfMjW8agAM3CbhWY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gkR0k7sgt2nmJR6O415nEefIML0YkTaEP4HTLw+IqVzAsHGbRso0EDtO2U9zO0Jq7 ZuP31aJMvuFORHMTTO3TB8aepD4Nb29vIIBQjHkTNDALKWwQ1+175DPN16rR9VAVu0 fLR6lU+cB2O5jW3Pwxpycr5dq50ZwQgPDGEiUI5A= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8G3kQ025947; Fri, 19 May 2017 03:16:04 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:16:03 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQB009185; Fri, 19 May 2017 03:16:00 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 04/41] mmc: host: omap_hsmmc: Add voltage switch support for UHS SD card Date: Fri, 19 May 2017 13:45:04 +0530 Message-ID: <20170519081541.26753-5-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Balaji T K UHS SD card i/o data line operates at 1.8V when in UHS speed mode. Add support for signal voltage switch to support UHS cards. Also, enable CIRQ before checking for CLEV/DLEV. MMC module can sense when the clock lines and data lines are driven high by the card, if MMC is active and CIRQ can be used to keep the MMC module active. This is required for voltage switching to succeed and the card to enumerate in UHS mode. Signed-off-by: Balaji T K Signed-off-by: Sourav Poddar [kishon@ti.com : cleanup the voltage switch sequence] Signed-off-by: Kishon Vijay Abraham I [nsekhar@ti.com: make card busy functions preempt safe] Signed-off-by: Sekhar Nori --- drivers/mmc/host/omap_hsmmc.c | 165 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) -- 2.11.0 diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 893d1624a5a3..4dbf75ad2376 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -44,6 +44,7 @@ #include #include #include +#include /* OMAP HSMMC Host Controller Registers */ #define OMAP_HSMMC_SYSSTATUS 0x0014 @@ -111,6 +112,9 @@ /* PSTATE */ #define DLEV_DAT(x) (1 << (20 + (x))) +/* AC12 */ +#define AC12_V1V8_SIGEN (1 << 19) + /* Interrupt masks for IE and ISE register */ #define CC_EN (1 << 0) #define TC_EN (1 << 1) @@ -150,6 +154,13 @@ #define VDD_1V8 1800000 /* 180000 uV */ #define VDD_3V0 3000000 /* 300000 uV */ #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) +#define VDD_30_31 (ffs(MMC_VDD_30_31) - 1) + +#define CON_CLKEXTFREE (1 << 16) +#define CON_PADEN (1 << 15) +#define PSTATE_CLEV (1 << 24) +#define PSTATE_DLEV (0xF << 20) +#define PSTATE_DLEV_DAT0 (0x1 << 20) /* * One controller can have multiple slots, like on some omap boards using @@ -177,6 +188,7 @@ struct omap_hsmmc_host { struct mmc_host *mmc; struct mmc_request *mrq; struct mmc_command *cmd; + u32 last_cmd; struct mmc_data *data; struct clk *fclk; struct clk *dbclk; @@ -209,6 +221,7 @@ struct omap_hsmmc_host { unsigned int flags; #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ +#define CLKEXTFREE_ENABLED (1 << 2) /* CLKEXTFREE enabled */ struct omap_hsmmc_next next_data; struct omap_hsmmc_platform_data *pdata; @@ -604,6 +617,9 @@ static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, if (cmd->opcode == MMC_ERASE) irq_mask &= ~DTO_EN; + if (host->flags & CLKEXTFREE_ENABLED) + irq_mask |= CIRQ_EN; + spin_lock_irqsave(&host->irq_lock, flags); OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); @@ -947,6 +963,7 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, cmdreg |= DMAE; host->req_in_progress = 1; + host->last_cmd = cmd->opcode; OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); @@ -1848,6 +1865,152 @@ static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, return blk_size; } +static int omap_hsmmc_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct omap_hsmmc_host *host; + u32 val = 0; + int ret = 0; + + host = mmc_priv(mmc); + + if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { + val = OMAP_HSMMC_READ(host->base, CAPA); + if (!(val & VS30)) + return -EOPNOTSUPP; + + omap_hsmmc_conf_bus_power(host, ios->signal_voltage); + + val = OMAP_HSMMC_READ(host->base, AC12); + val &= ~AC12_V1V8_SIGEN; + OMAP_HSMMC_WRITE(host->base, AC12, val); + + ret = omap_hsmmc_set_power(host, 1, VDD_30_31); + if (ret) { + dev_err(mmc_dev(host->mmc), "failed to switch to 3v\n"); + return ret; + } + + dev_dbg(mmc_dev(host->mmc), " i/o voltage switch to 3V\n"); + } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { + val = OMAP_HSMMC_READ(host->base, CAPA); + if (!(val & VS18)) + return -EOPNOTSUPP; + + omap_hsmmc_conf_bus_power(host, ios->signal_voltage); + + val = OMAP_HSMMC_READ(host->base, AC12); + val |= AC12_V1V8_SIGEN; + OMAP_HSMMC_WRITE(host->base, AC12, val); + + ret = omap_hsmmc_set_power(host, 1, VDD_165_195); + if (ret < 0) { + dev_err(mmc_dev(host->mmc), "failed to switch 1.8v\n"); + return ret; + } + } else { + return -EOPNOTSUPP; + } + + return 0; +} + +static int omap_hsmmc_card_busy_low(struct omap_hsmmc_host *host) +{ + int i; + u32 val; + + val = OMAP_HSMMC_READ(host->base, CON); + val &= ~CON_CLKEXTFREE; + val |= CON_PADEN; + OMAP_HSMMC_WRITE(host->base, CON, val); + + /* By observation, card busy status reflects in 100 - 200us */ + for (i = 0; i < 5; i++) { + val = OMAP_HSMMC_READ(host->base, PSTATE); + if (!(val & (PSTATE_CLEV | PSTATE_DLEV))) + return true; + + usleep_range(100, 200); + } + + dev_err(mmc_dev(host->mmc), "card busy\n"); + + return false; +} + +static int omap_hsmmc_card_busy_high(struct omap_hsmmc_host *host) +{ + int i; + u32 val; + int ret = true; + + val = OMAP_HSMMC_READ(host->base, CON); + val |= CLKEXTFREE; + OMAP_HSMMC_WRITE(host->base, CON, val); + + host->flags |= CLKEXTFREE_ENABLED; + disable_irq(host->irq); + omap_hsmmc_enable_irq(host, NULL); + + /* By observation, card busy status reflects in 100 - 200us */ + for (i = 0; i < 5; i++) { + val = OMAP_HSMMC_READ(host->base, PSTATE); + if ((val & PSTATE_CLEV) && (val & PSTATE_DLEV)) { + val = OMAP_HSMMC_READ(host->base, CON); + val &= ~(CON_CLKEXTFREE | CON_PADEN); + OMAP_HSMMC_WRITE(host->base, CON, val); + ret = false; + goto disable_irq; + } + + usleep_range(100, 200); + } + + dev_err(mmc_dev(host->mmc), "card busy\n"); + +disable_irq: + omap_hsmmc_disable_irq(host); + enable_irq(host->irq); + host->flags &= ~CLKEXTFREE_ENABLED; + + return ret; +} + +static int omap_hsmmc_card_busy(struct mmc_host *mmc) +{ + struct omap_hsmmc_host *host; + u32 val; + u32 reg; + int ret; + + host = mmc_priv(mmc); + + if (host->last_cmd != SD_SWITCH_VOLTAGE) { + /* + * PADEN should be set for DLEV to reflect the correct + * state of data lines atleast for MMC1 on AM57x. + */ + reg = OMAP_HSMMC_READ(host->base, CON); + reg |= CON_PADEN; + OMAP_HSMMC_WRITE(host->base, CON, reg); + val = OMAP_HSMMC_READ(host->base, PSTATE); + reg &= ~CON_PADEN; + OMAP_HSMMC_WRITE(host->base, CON, reg); + if (val & PSTATE_DLEV_DAT0) + return false; + return true; + } + + val = OMAP_HSMMC_READ(host->base, AC12); + if (val & AC12_V1V8_SIGEN) + ret = omap_hsmmc_card_busy_high(host); + else + ret = omap_hsmmc_card_busy_low(host); + + return ret; +} + static struct mmc_host_ops omap_hsmmc_ops = { .post_req = omap_hsmmc_post_req, .pre_req = omap_hsmmc_pre_req, @@ -1857,6 +2020,8 @@ static struct mmc_host_ops omap_hsmmc_ops = { .get_ro = mmc_gpio_get_ro, .init_card = omap_hsmmc_init_card, .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, + .start_signal_voltage_switch = omap_hsmmc_start_signal_voltage_switch, + .card_busy = omap_hsmmc_card_busy, }; #ifdef CONFIG_DEBUG_FS From patchwork Fri May 19 08:15:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100165 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp201563qge; 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[209.132.180.67]) by mx.google.com with ESMTP id 61si7667454plc.226.2017.05.19.01.17.43; Fri, 19 May 2017 01:17:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753962AbdESIR3 (ORCPT + 25 others); Fri, 19 May 2017 04:17:29 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:10336 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752555AbdESIRX (ORCPT ); Fri, 19 May 2017 04:17:23 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8GakB018070; Fri, 19 May 2017 03:16:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181796; bh=YzP7B+gKUX+aDHplB4DPk9GbGq/mkjJecEz3w8e0aIA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HrAtYw82wIZkLDG+uXtny3VK8xD67iikbXINJYErJLok9D/YMS0zn/f3v/Z6JIchi n01E6DTLTOvAQJ/ZMEm+1W9/lzHec0XJdXHsPZFWHbEWNrh3/UnOyGYMRPGkNyjk0v 9kr5bIMbaYVy6/g/RY8l7qJmUWV2D02IOM8kI1dg= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8Gaaa026876; Fri, 19 May 2017 03:16:36 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:16:35 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQI009185; Fri, 19 May 2017 03:16:31 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 11/41] mmc: host: omap_hsmmc: Add new compatible string to support dra7 Date: Fri, 19 May 2017 13:45:11 +0530 Message-ID: <20170519081541.26753-12-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new compatible string "ti,dra7-hsmmc" to support dra7 and dra72 controllers. Also create a new controller flag "OMAP_HSMMC_REQUIRE_IODELAY" to specify all controllers that use "ti,dra7-hsmmc" require iodealy configuration to be set. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt | 1 + drivers/mmc/host/omap_hsmmc.c | 10 ++++++++++ include/linux/platform_data/hsmmc-omap.h | 1 + 3 files changed, 12 insertions(+) -- 2.11.0 Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt index 74166a0d460d..258e25af10f7 100644 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt @@ -12,6 +12,7 @@ Required properties: Should be "ti,omap3-hsmmc", for OMAP3 controllers Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0 Should be "ti,omap4-hsmmc", for OMAP4 controllers + Should be "ti,dra7-hsmmc", for dra7 and dra72 controllers Should be "ti,am33xx-hsmmc", for AM335x controllers - ti,hwmods: Must be "mmc", n is controller instance starting 1 diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 7088a88074a8..8114b8b73491 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -2314,6 +2314,12 @@ static const struct omap_mmc_of_data am33xx_mmc_of_data = { .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, }; +static const struct omap_mmc_of_data dra7_mmc_of_data = { + .reg_offset = 0x100, + .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING | + OMAP_HSMMC_REQUIRE_IODELAY, +}; + static const struct of_device_id omap_mmc_of_match[] = { { .compatible = "ti,omap2-hsmmc", @@ -2333,6 +2339,10 @@ static const struct of_device_id omap_mmc_of_match[] = { .compatible = "ti,am33xx-hsmmc", .data = &am33xx_mmc_of_data, }, + { + .compatible = "ti,dra7-hsmmc", + .data = &dra7_mmc_of_data, + }, {}, }; MODULE_DEVICE_TABLE(of, omap_mmc_of_match); diff --git a/include/linux/platform_data/hsmmc-omap.h b/include/linux/platform_data/hsmmc-omap.h index 8e981be2e2c2..21832a357654 100644 --- a/include/linux/platform_data/hsmmc-omap.h +++ b/include/linux/platform_data/hsmmc-omap.h @@ -27,6 +27,7 @@ #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) #define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1) #define OMAP_HSMMC_SWAKEUP_MISSING BIT(2) +#define OMAP_HSMMC_REQUIRE_IODELAY BIT(3) struct omap_hsmmc_dev_attr { u8 flags; From patchwork Fri May 19 08:15:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100179 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp204797qge; Fri, 19 May 2017 01:29:36 -0700 (PDT) X-Received: by 10.99.9.130 with SMTP id 124mr9159381pgj.22.1495182576758; Fri, 19 May 2017 01:29:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495182576; cv=none; d=google.com; s=arc-20160816; b=PQys+Ig170sKS50yOj9dwqtKdmW/JlfqVF/e0wrOc55n1WLJJFReMgFzy41Ge/FX7P hg/hGR/OAwOuRD4WVVpN2WYNPh9oKJNh8rKMSQz5vBMhrRaqLIHFv28zE6XhcW9gpnP3 QRneiKOGnN34bmt3Tor0p510PPB1I+IPttbbbU/dCBalug6JWG39vVmeEaLH6Q0ct2Na mdZQ/5hN+RPzAUf5lVWPqu99nCA7WC9sSdSGhT9yWsntBmPXohgetwen7DugKLTX8tOd bC6ES/3SXfSndTPQ5uIBYhkA2SDQ59GhtIlKiLwGmY+zG16DX8wFt4mCOhgycuyWb9vu Q6QA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=FTsKJzLClYdhfd9vBTA5e8aPpYSZihkKajLCsS9O/Go=; b=fQJwS3Q1L9Qsn7cWH4W/Sh+8RG8r0Yt87sUOgKSy22ReGjQll15aGa/XoVOWkxaK70 pIJ9QppVCyEQQ6BUGl4msINeovGANRAHxL9ae7rIpIpwXmLF2IJGG+jqQnQvXj9iPvlQ Y44upWXNtahiAgkjqqbJhkb5TjMkdBEJvRS4tpTNG/R+DDc7rqJvjQLSyq/wb+5GabpV brhv3jtCKquUdfnDzhROVg+yR7ymd6b/yu8aCuakYfIV2nMRBQeCjGvHaiuaDPU/2RwT F2aSUd3PR0kse9z2bcnmS8+kODOE7JJqssb5KO88axpsqEt21oio7T+upqwCGHZB/Up5 gZbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q27si7733531pfk.48.2017.05.19.01.29.36; Fri, 19 May 2017 01:29:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755818AbdESI3I (ORCPT + 25 others); Fri, 19 May 2017 04:29:08 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:10335 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753542AbdESIRX (ORCPT ); Fri, 19 May 2017 04:17:23 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8GenF018095; Fri, 19 May 2017 03:16:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181800; bh=zOIwWFil3i81BToGD7cDvCD0//xsjKaAS1dSVG6WWSU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QU5Ih8ytBnTxMIGXcZuGq+Qq/8DD+fO4WYh6DQO8voWUmoIQHBufsUkqpR9CT1tz3 a6vh4SkNGABbG7AQIB9dqP44+6WHijz8pG8gOHMc70rpKffUmuiNkXya5kfJ9/8DVX HoaP0iojA681C07OBZAmFSLvsPudUdZhb6wgaU+8= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8Ge31026964; Fri, 19 May 2017 03:16:40 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:16:40 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQJ009185; Fri, 19 May 2017 03:16:36 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 12/41] mmc: host: omap_hsmmc: Fix error path sequence Date: Fri, 19 May 2017 13:45:12 +0530 Message-ID: <20170519081541.26753-13-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix the error path sequence so that clk_disable, runtime_disable etc are done in the reverse order of how they were enabled. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- drivers/mmc/host/omap_hsmmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.11.0 diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 8114b8b73491..b28f0e9631ce 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -2602,16 +2602,16 @@ static int omap_hsmmc_probe(struct platform_device *pdev) err_slot_name: mmc_remove_host(mmc); err_irq: - device_init_wakeup(&pdev->dev, false); if (!IS_ERR_OR_NULL(host->tx_chan)) dma_release_channel(host->tx_chan); if (!IS_ERR_OR_NULL(host->rx_chan)) dma_release_channel(host->rx_chan); + if (host->dbclk) + clk_disable_unprepare(host->dbclk); pm_runtime_dont_use_autosuspend(host->dev); pm_runtime_put_sync(host->dev); pm_runtime_disable(host->dev); - if (host->dbclk) - clk_disable_unprepare(host->dbclk); + device_init_wakeup(&pdev->dev, false); err1: err_gpio: mmc_free_host(mmc); From patchwork Fri May 19 08:15:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100176 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp203969qge; Fri, 19 May 2017 01:26:32 -0700 (PDT) X-Received: by 10.98.236.28 with SMTP id k28mr9393276pfh.3.1495182392294; Fri, 19 May 2017 01:26:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495182392; cv=none; d=google.com; s=arc-20160816; b=gqNGxIALHxOtHErLmemvzvEQhnmuUv78v+0u8sjik/SroL8V5xkCnO+8bPhwP7U5+1 EnJEf/5d7GsR02ch9/9IMg/GHe07slZW4NBBBspsxnRVkllb3YUUshMp7fvnRwDogiFN Me/+WFrJIUj+uox3o/5/DKSzKeo3hdFoFBruiRCe5QbKVzJ6BV8LZhVldTsshnUwyx2c chijRkSIji/DidEhhZSZl1zVS7N49r9MPC5iUEv0D5JZJrCkiYNK6SgBwkyQymm4IdC9 PvUxUiYuYIQWRbQT6/EmXKY/GCOw6l1mQ+w+qYzxAW089JFaExRiOcZrVtyLN8Q3aK0F BeOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=GuZbRiKafmANjoXbUzTLxiD/nXZEcAxO+evlgibNXvY=; b=swKoemkEIIULAQ7HTT56vgQhi7s2G+rx2yDzt5wbSvyj0TWTYT45YzGC4rG4rfJcJT n55rg6JkloxcUTnpjJDjC3LQc23Z1+fimMTCeNTW7k7vT3rp6lgm+pfBggAN350kq9p/ waEo1sSpMNshGNA6TmCz7/C1iLHjxRmlkHkEfvmhYpFKO8BUw3L3gm4V1TZpu/l7jT3n x7pKXBWD04OygcSljy9xKQCywYUk9R0LQzVvtdXmUcN3dEFmIW+1KxyhzkNz7Bi9+CBY sQIq3X99MsV365cx2LTJgTt+khmcBjzxLC6mYXicL8qIuYjtDoYQV5RU/Rti8Hg/j8NH xHFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t18si7826251pgn.128.2017.05.19.01.26.31; Fri, 19 May 2017 01:26:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755362AbdESI0K (ORCPT + 25 others); Fri, 19 May 2017 04:26:10 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:23209 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753203AbdESIS6 (ORCPT ); Fri, 19 May 2017 04:18:58 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8Go1e010014; Fri, 19 May 2017 03:16:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181810; bh=QGO93fWLJa2RWPMXmIQUnJmgV8wSbrRx/wJjeQTDY4Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yJkS6VT+FtX2dH/BB+hDmIGjFe+omVb7dvqpUJntzpgON7P+HEav2ubHBRz6V/0Sj o4RwLsWsHqvSw36aqLIxisaKBQ+Q5AbQfzd4WW0+yoTEWnXN4K+SA3icmpEM6JIDeI bImK5AZwF/jDa/JenmExxhaj+CMSq/UZBv4VvdLo= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8GjrP027070; Fri, 19 May 2017 03:16:45 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:16:44 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQK009185; Fri, 19 May 2017 03:16:40 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 13/41] mmc: host: omap_hsmmc: Add support to set IODELAY values Date: Fri, 19 May 2017 13:45:13 +0530 Message-ID: <20170519081541.26753-14-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. Add support to set the IODELAY values depending on the various MMC modes using the pinctrl APIs. Signed-off-by: Kishon Vijay Abraham I [nsekhar@ti.com: introduce OMAP_HSMMC_SETUP_PINCTRL()] Signed-off-by: Sekhar Nori --- .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 5 + drivers/mmc/host/omap_hsmmc.c | 124 ++++++++++++++++++++- include/linux/platform_data/hsmmc-omap.h | 3 + 3 files changed, 129 insertions(+), 3 deletions(-) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt index 258e25af10f7..dcf0b777c031 100644 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt @@ -20,6 +20,11 @@ Optional properties: ti,dual-volt: boolean, supports dual voltage cards -supply: phandle to the regulator device tree node "supply-name" examples are "vmmc", "vmmc_aux" etc +pinctrl-names: Should be a list of pinctrl state names and can be "sdr104", +"hs200_1_8v", "ddr50", "sdr50", "sdr25", "sdr12", "hs", "ddr_1_8v" or +"default". +pinctrl-: Phandle referencing pin configuration of the sd/emmc controller. +See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt ti,non-removable: non-removable slot (like eMMC) ti,needs-special-reset: Requires a special softreset sequence ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index b28f0e9631ce..7271c7e3144c 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -258,6 +258,18 @@ struct omap_hsmmc_host { struct timer_list timer; unsigned long long data_timeout; + struct pinctrl *pinctrl; + struct pinctrl_state *pinctrl_state; + struct pinctrl_state *default_pinctrl_state; + struct pinctrl_state *sdr104_pinctrl_state; + struct pinctrl_state *hs200_1_8v_pinctrl_state; + struct pinctrl_state *ddr50_pinctrl_state; + struct pinctrl_state *sdr50_pinctrl_state; + struct pinctrl_state *sdr25_pinctrl_state; + struct pinctrl_state *sdr12_pinctrl_state; + struct pinctrl_state *hs_pinctrl_state; + struct pinctrl_state *ddr_1_8v_pinctrl_state; + /* return MMC cover switch state, can be NULL if not supported. * * possible return values: @@ -1729,6 +1741,8 @@ static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) static void omap_hsmmc_set_timing(struct omap_hsmmc_host *host) { u32 val; + int ret; + struct pinctrl_state *pinctrl_state; struct mmc_ios *ios = &host->mmc->ios; omap_hsmmc_stop_clock(host); @@ -1738,35 +1752,54 @@ static void omap_hsmmc_set_timing(struct omap_hsmmc_host *host) switch (ios->timing) { case MMC_TIMING_UHS_SDR104: val |= AC12_UHSMC_SDR104; + pinctrl_state = host->sdr104_pinctrl_state; break; case MMC_TIMING_MMC_HS200: val |= AC12_UHSMC_SDR104; + pinctrl_state = host->hs200_1_8v_pinctrl_state; break; case MMC_TIMING_UHS_DDR50: val |= AC12_UHSMC_DDR50; + pinctrl_state = host->ddr50_pinctrl_state; break; case MMC_TIMING_UHS_SDR50: val |= AC12_UHSMC_SDR50; + pinctrl_state = host->sdr50_pinctrl_state; break; case MMC_TIMING_UHS_SDR25: val |= AC12_UHSMC_SDR25; + pinctrl_state = host->sdr25_pinctrl_state; break; case MMC_TIMING_UHS_SDR12: val |= AC12_UHSMC_SDR12; + pinctrl_state = host->sdr12_pinctrl_state; break; case MMC_TIMING_SD_HS: case MMC_TIMING_MMC_HS: val |= AC12_UHSMC_RES; + pinctrl_state = host->hs_pinctrl_state; break; case MMC_TIMING_MMC_DDR52: val |= AC12_UHSMC_RES; + pinctrl_state = host->ddr_1_8v_pinctrl_state; break; default: val |= AC12_UHSMC_RES; + pinctrl_state = host->default_pinctrl_state; break; } OMAP_HSMMC_WRITE(host->base, AC12, val); + if (host->pdata->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) { + ret = pinctrl_select_state(host->pinctrl, pinctrl_state); + if (ret) { + dev_err(mmc_dev(host->mmc), + "failed to select pinctrl state\n"); + return; + } + host->pinctrl_state = pinctrl_state; + } + omap_hsmmc_start_clock(host); } @@ -2357,8 +2390,14 @@ static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) return ERR_PTR(-ENOMEM); /* out of memory */ legacy = dev_get_platdata(dev); - if (legacy && legacy->name) - pdata->name = legacy->name; + if (legacy) { + if (legacy->name) + pdata->name = legacy->name; + if (legacy->version) + pdata->version = legacy->version; + if (legacy->max_freq > 0) + pdata->max_freq = legacy->max_freq; + } if (of_find_property(np, "ti,dual-volt", NULL)) pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; @@ -2388,6 +2427,73 @@ static inline struct omap_hsmmc_platform_data } #endif +#define OMAP_HSMMC_SETUP_PINCTRL(capvar, capmask, mode) \ + do { \ + struct pinctrl_state *s = ERR_PTR(-ENODEV); \ + char str[20]; \ + char *version = host->pdata->version; \ + \ + if (!(mmc->capvar & (capmask))) \ + break; \ + \ + if (host->pdata->version) { \ + sprintf(str, "%s-%s", #mode, version); \ + s = pinctrl_lookup_state(host->pinctrl, str); \ + } \ + \ + if (IS_ERR(s)) { \ + sprintf(str, "%s", #mode); \ + s = pinctrl_lookup_state(host->pinctrl, str); \ + } \ + \ + if (IS_ERR(s)) { \ + dev_err(host->dev, "no pinctrl state for %s " \ + "mode\n", #mode); \ + mmc->capvar &= ~(capmask); \ + } else { \ + host->mode##_pinctrl_state = s; \ + } \ + \ + } while (0) + +static int omap_hsmmc_get_iodelay_pinctrl_state(struct omap_hsmmc_host *host) +{ + struct mmc_host *mmc = host->mmc; + + if (!(host->pdata->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) + return 0; + + host->pinctrl = devm_pinctrl_get(host->dev); + if (IS_ERR(host->pinctrl)) { + dev_err(host->dev, "Cannot get pinctrl\n"); + return PTR_ERR(host->pinctrl); + } + + host->default_pinctrl_state = pinctrl_lookup_state(host->pinctrl, + "default"); + if (IS_ERR(host->default_pinctrl_state)) { + dev_err(host->dev, + "no pinctrl state for default mode\n"); + return PTR_ERR(host->default_pinctrl_state); + } + + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_UHS_SDR104, sdr104); + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_UHS_DDR50, ddr50); + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_UHS_SDR50, sdr50); + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_UHS_SDR25, sdr25); + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_UHS_SDR12, sdr12); + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_1_8V_DDR, ddr_1_8v); + OMAP_HSMMC_SETUP_PINCTRL(caps, + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + hs); + OMAP_HSMMC_SETUP_PINCTRL(caps2, MMC_CAP2_HS200_1_8V_SDR, + hs200_1_8v); + + host->pinctrl_state = host->default_pinctrl_state; + + return 0; +} + static int omap_hsmmc_probe(struct platform_device *pdev) { struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; @@ -2535,6 +2641,10 @@ static int omap_hsmmc_probe(struct platform_device *pdev) omap_hsmmc_set_capabilities(host); + ret = omap_hsmmc_get_iodelay_pinctrl_state(host); + if (ret) + goto err_pinctrl; + host->rx_chan = dma_request_chan(&pdev->dev, "rx"); if (IS_ERR(host->rx_chan)) { dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); @@ -2606,6 +2716,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) dma_release_channel(host->tx_chan); if (!IS_ERR_OR_NULL(host->rx_chan)) dma_release_channel(host->rx_chan); +err_pinctrl: if (host->dbclk) clk_disable_unprepare(host->dbclk); pm_runtime_dont_use_autosuspend(host->dev); @@ -2741,6 +2852,7 @@ static int omap_hsmmc_runtime_resume(struct device *dev) { struct omap_hsmmc_host *host; unsigned long flags; + int ret; host = platform_get_drvdata(to_platform_device(dev)); omap_hsmmc_context_restore(host); @@ -2757,7 +2869,13 @@ static int omap_hsmmc_runtime_resume(struct device *dev) OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); } else { - pinctrl_pm_select_default_state(host->dev); + if (host->pinctrl) { + ret = pinctrl_select_state(host->pinctrl, + host->pinctrl_state); + if (ret) + dev_err(mmc_dev(host->mmc), + "failed to activate pinctrl state\n"); + } } spin_unlock_irqrestore(&host->irq_lock, flags); return 0; diff --git a/include/linux/platform_data/hsmmc-omap.h b/include/linux/platform_data/hsmmc-omap.h index 21832a357654..8e771851e07a 100644 --- a/include/linux/platform_data/hsmmc-omap.h +++ b/include/linux/platform_data/hsmmc-omap.h @@ -71,6 +71,9 @@ struct omap_hsmmc_platform_data { #define HSMMC_HAS_HSPE_SUPPORT (1 << 2) unsigned features; + /* string specifying a particular variant of hardware */ + char *version; + int gpio_cd; /* gpio (card detect) */ int gpio_cod; /* gpio (cover detect) */ int gpio_wp; /* gpio (write protect) */ From patchwork Fri May 19 08:15:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100175 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp203786qge; Fri, 19 May 2017 01:25:53 -0700 (PDT) X-Received: by 10.98.33.74 with SMTP id h71mr9014160pfh.209.1495182353327; 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[209.132.180.67]) by mx.google.com with ESMTP id f67si5796305pff.170.2017.05.19.01.25.53; Fri, 19 May 2017 01:25:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755246AbdESITQ (ORCPT + 25 others); Fri, 19 May 2017 04:19:16 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:23239 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750892AbdESITJ (ORCPT ); Fri, 19 May 2017 04:19:09 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8Gx7x010031; Fri, 19 May 2017 03:16:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181819; bh=4mB4EOXU11P1m7FfjgMLgEwXTx1EE/0kNyFSzZP3xM4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Yg/lT6Ow9Zre11gjT75A3lNk4KcfdDVi62SsxRYI/+oCaKH5sOYz10SqUKIUTWqab e268Zv7bM+m+/S5yUAJRQaPq5WNtG9rRC2bj573FGyV122HBQtrohL0383GgaautTS mfd/TiFt1NFC7XolGgbpQ90rwauOvszajrI29lww= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8GsmH027226; Fri, 19 May 2017 03:16:54 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:16:53 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQM009185; Fri, 19 May 2017 03:16:49 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 15/41] mmc: host: omap_hsmmc: Enable ADMA2 Date: Fri, 19 May 2017 13:45:15 +0530 Message-ID: <20170519081541.26753-16-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org omap hsmmc host controller has ADMA2 feature. Enable it here for better read and write throughput. Signed-off-by: Kishon Vijay Abraham I [misael.lopez@ti.com: handle ADMA errors] Signed-off-by: Misael Lopez Cruz [nsekhar@ti.com: restore adma settings after context loss] Signed-off-by: Sekhar Nori --- drivers/mmc/host/omap_hsmmc.c | 307 +++++++++++++++++++++++++++---- include/linux/platform_data/hsmmc-omap.h | 1 + 2 files changed, 271 insertions(+), 37 deletions(-) -- 2.11.0 diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 90bf097484ae..c6e3efb0f8fb 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -48,6 +48,9 @@ #include /* OMAP HSMMC Host Controller Registers */ +#define OMAP_HSMMC_HL_REV 0x0000 +#define OMAP_HSMMC_HL_HWINFO 0x0004 +#define OMAP_HSMMC_HL_SYSCONFIG 0x0010 #define OMAP_HSMMC_SYSSTATUS 0x0014 #define OMAP_HSMMC_CON 0x002C #define OMAP_HSMMC_DLL 0x0034 @@ -69,7 +72,10 @@ #define OMAP_HSMMC_AC12 0x013C #define OMAP_HSMMC_CAPA 0x0140 #define OMAP_HSMMC_CAPA2 0x0144 +#define OMAP_HSMMC_ADMAES 0x0154 +#define OMAP_HSMMC_ADMASAL 0x0158 +#define MADMA_EN (1 << 0) #define VS18 (1 << 26) #define VS30 (1 << 25) #define HSS (1 << 21) @@ -79,6 +85,7 @@ #define SDVS_MASK 0x00000E00 #define SDVSCLR 0xFFFFF1FF #define SDVSDET 0x00000400 +#define DMA_SELECT (2 << 3) #define AUTOIDLE 0x1 #define SDBP (1 << 8) #define DTO 0xe @@ -100,6 +107,7 @@ #define FOUR_BIT (1 << 1) #define HSPE (1 << 2) #define IWE (1 << 24) +#define DMA_MASTER (1 << 20) #define DDR (1 << 19) #define CLKEXTFREE (1 << 16) #define CTPL (1 << 11) @@ -153,10 +161,11 @@ #define DCRC_EN (1 << 21) #define DEB_EN (1 << 22) #define ACE_EN (1 << 24) +#define ADMAE_EN (1 << 25) #define CERR_EN (1 << 28) #define BADA_EN (1 << 29) -#define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ +#define INT_EN_MASK (BADA_EN | CERR_EN | ADMAE_EN | ACE_EN | DEB_EN | DCRC_EN |\ DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ BRR_EN | BWR_EN | TC_EN | CC_EN) @@ -206,6 +215,33 @@ #define OMAP_HSMMC_WRITE(base, reg, val) \ __raw_writel((val), (base) + OMAP_HSMMC_##reg) +struct omap_hsmmc_adma_desc { + u8 attr; + u8 reserved; + u16 len; + u32 addr; +} __packed; + +#define ADMA_DESC_SIZE 8 + +#define ADMA_MAX_LEN 65532 + +/* Decriptor table defines */ +#define ADMA_DESC_ATTR_VALID BIT(0) +#define ADMA_DESC_ATTR_END BIT(1) +#define ADMA_DESC_ATTR_INT BIT(2) +#define ADMA_DESC_ATTR_ACT1 BIT(4) +#define ADMA_DESC_ATTR_ACT2 BIT(5) + +#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 +#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2) + +/* ADMA error status */ +#define AES_MASK 0x3 +#define ST_STOP 0x0 +#define ST_FDS 0x1 +#define ST_TFR 0x3 + struct omap_hsmmc_next { unsigned int dma_len; s32 cookie; @@ -239,6 +275,7 @@ struct omap_hsmmc_host { int irq; int wake_irq; int dma_ch; + int use_adma; struct dma_chan *tx_chan; struct dma_chan *rx_chan; int response_busy; @@ -270,6 +307,9 @@ struct omap_hsmmc_host { struct pinctrl_state *hs_pinctrl_state; struct pinctrl_state *ddr_1_8v_pinctrl_state; + struct omap_hsmmc_adma_desc *adma_desc_table; + dma_addr_t adma_desc_table_addr; + /* return MMC cover switch state, can be NULL if not supported. * * possible return values: @@ -851,6 +891,18 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) OMAP_HSMMC_WRITE(host->base, IE, 0); OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); + if (host->use_adma) { + u32 val; + + val = OMAP_HSMMC_READ(host->base, CON); + val |= DMA_MASTER; + OMAP_HSMMC_WRITE(host->base, CON, val); + + val = OMAP_HSMMC_READ(host->base, HCTL); + val |= DMA_SELECT; + OMAP_HSMMC_WRITE(host->base, HCTL, val); + } + /* Do not initialize card-specific things if the power is off */ if (host->power_mode == MMC_POWER_OFF) goto out; @@ -1065,6 +1117,10 @@ omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) return; } + if (host->use_adma && host->data && !data->host_cookie) + dma_unmap_sg(host->dev, data->sg, data->sg_len, + mmc_get_dma_dir(data)); + host->data = NULL; if (!data->error) @@ -1126,13 +1182,17 @@ static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) host->dma_ch = -1; spin_unlock_irqrestore(&host->irq_lock, flags); - if (dma_ch != -1) { - struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); - + if (host->use_adma) { + dma_unmap_sg(host->dev, host->data->sg, host->data->sg_len, + mmc_get_dma_dir(host->data)); + host->data->host_cookie = 0; + } else if (dma_ch != -1) { + struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, + host->data); dmaengine_terminate_all(chan); dma_unmap_sg(chan->device->dev, - host->data->sg, host->data->sg_len, - mmc_get_dma_dir(host->data)); + host->data->sg, host->data->sg_len, + mmc_get_dma_dir(host->data)); host->data->host_cookie = 0; } @@ -1227,6 +1287,35 @@ static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, host->mrq->cmd->error = err; } +static void omap_hsmmc_adma_err(struct omap_hsmmc_host *host) +{ + u32 admaes, admasal; + + admaes = OMAP_HSMMC_READ(host->base, ADMAES); + admasal = OMAP_HSMMC_READ(host->base, ADMASAL); + + switch (admaes & AES_MASK) { + case ST_STOP: + dev_err(mmc_dev(host->mmc), + "ADMA err: ST_STOP, desc at 0x%08x follows the erroneous one\n", + admasal); + break; + case ST_FDS: + dev_err(mmc_dev(host->mmc), + "ADMA err: ST_FDS, erroneous desc at 0x%08x\n", + admasal); + break; + case ST_TFR: + dev_err(mmc_dev(host->mmc), + "ADMA err: ST_TFR, desc at 0x%08x follows the erroneous one\n", + admasal); + break; + default: + dev_warn(mmc_dev(host->mmc), "Unexpected ADMA error state\n"); + break; + } +} + static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) { struct mmc_data *data; @@ -1245,6 +1334,13 @@ static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) end_trans = !end_cmd; host->response_busy = 0; } + + if (status & ADMAE_EN) { + omap_hsmmc_adma_err(host); + end_trans = 1; + data->error = -EIO; + } + if (status & (CTO_EN | DTO_EN)) hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | @@ -1426,6 +1522,7 @@ static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, struct dma_chan *chan) { int dma_len; + struct device *dev; if (!next && data->host_cookie && data->host_cookie != host->next_data.cookie) { @@ -1435,11 +1532,15 @@ static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, data->host_cookie = 0; } + if (chan) + dev = chan->device->dev; + else + dev = mmc_dev(host->mmc); + /* Check if next job is already prepared */ if (next || data->host_cookie != host->next_data.cookie) { - dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, + dma_len = dma_map_sg(dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); - } else { dma_len = host->next_data.dma_len; host->next_data.dma_len = 0; @@ -1612,8 +1713,58 @@ static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) | (req->data->blocks << 16)); set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); - chan = omap_hsmmc_get_dma_chan(host, req->data); - dma_async_issue_pending(chan); + + if (host->use_adma) { + OMAP_HSMMC_WRITE(host->base, ADMASAL, + (u32)host->adma_desc_table_addr); + } else { + chan = omap_hsmmc_get_dma_chan(host, req->data); + dma_async_issue_pending(chan); + } +} + +static int omap_hsmmc_write_adma_desc(struct omap_hsmmc_host *host, void *desc, + dma_addr_t addr, u16 len, u8 attr) +{ + struct omap_hsmmc_adma_desc *dma_desc = desc; + + dma_desc->len = len; + dma_desc->addr = (u32)addr; + dma_desc->reserved = 0; + dma_desc->attr = attr; + + return 0; +} + +static int omap_hsmmc_setup_adma_transfer(struct omap_hsmmc_host *host, + struct mmc_request *req) +{ + struct mmc_data *data = req->data; + struct scatterlist *sg; + int i; + int len; + int ret; + dma_addr_t addr; + struct omap_hsmmc_adma_desc *dma_desc; + + ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, NULL); + if (ret) + return ret; + + dma_desc = host->adma_desc_table; + for_each_sg(data->sg, sg, host->dma_len, i) { + addr = sg_dma_address(sg); + len = sg_dma_len(sg); + WARN_ON(len > ADMA_MAX_LEN); + omap_hsmmc_write_adma_desc(host, dma_desc, addr, len, + ADMA_DESC_ATTR_VALID | + ADMA_DESC_TRANSFER_DATA); + dma_desc++; + } + omap_hsmmc_write_adma_desc(host, dma_desc, 0, 0, ADMA_DESC_ATTR_END | + ADMA_DESC_ATTR_VALID); + + return 0; } /* @@ -1644,10 +1795,18 @@ omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) return 0; } - ret = omap_hsmmc_setup_dma_transfer(host, req); - if (ret != 0) { - dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); - return ret; + if (host->use_adma) { + ret = omap_hsmmc_setup_adma_transfer(host, req); + if (ret != 0) { + dev_err(mmc_dev(host->mmc), "MMC adma setup failed\n"); + return ret; + } + } else { + ret = omap_hsmmc_setup_dma_transfer(host, req); + if (ret != 0) { + dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); + return ret; + } } return 0; } @@ -1657,11 +1816,18 @@ static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, { struct omap_hsmmc_host *host = mmc_priv(mmc); struct mmc_data *data = mrq->data; + struct device *dev; + struct dma_chan *c; if (data->host_cookie) { - struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); + if (host->use_adma) { + dev = mmc_dev(mmc); + } else { + c = omap_hsmmc_get_dma_chan(host, mrq->data); + dev = c->device->dev; + } - dma_unmap_sg(c->device->dev, data->sg, data->sg_len, + dma_unmap_sg(dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); data->host_cookie = 0; } @@ -1677,7 +1843,8 @@ static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) return ; } - c = omap_hsmmc_get_dma_chan(host, mrq->data); + if (!host->use_adma) + c = omap_hsmmc_get_dma_chan(host, mrq->data); if (omap_hsmmc_pre_dma_transfer(host, mrq->data, &host->next_data, c)) @@ -2337,6 +2504,7 @@ static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { static const struct omap_mmc_of_data omap4_mmc_of_data = { .reg_offset = 0x100, + .controller_flags = OMAP_HSMMC_HAS_HWPARAM, }; static const struct omap_mmc_of_data am33xx_mmc_of_data = { .reg_offset = 0x100, @@ -2346,7 +2514,8 @@ static const struct omap_mmc_of_data am33xx_mmc_of_data = { static const struct omap_mmc_of_data dra7_mmc_of_data = { .reg_offset = 0x100, .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING | - OMAP_HSMMC_REQUIRE_IODELAY, + OMAP_HSMMC_REQUIRE_IODELAY | + OMAP_HSMMC_HAS_HWPARAM, }; static const struct of_device_id omap_mmc_of_match[] = { @@ -2490,6 +2659,64 @@ static int omap_hsmmc_get_iodelay_pinctrl_state(struct omap_hsmmc_host *host) return 0; } +static int omap_hsmmc_adma_init(struct omap_hsmmc_host *host) +{ + struct mmc_host *mmc = host->mmc; + u32 val; + + host->adma_desc_table = dma_alloc_coherent(host->dev, ADMA_DESC_SIZE * + (mmc->max_segs + 1), + &host->adma_desc_table_addr, + GFP_KERNEL); + if (!host->adma_desc_table) { + dev_err(host->dev, "failed to allocate adma desc table\n"); + return -ENOMEM; + } + + val = OMAP_HSMMC_READ(host->base, HCTL); + val |= DMA_SELECT; + OMAP_HSMMC_WRITE(host->base, HCTL, val); + + val = OMAP_HSMMC_READ(host->base, CON); + val |= DMA_MASTER; + OMAP_HSMMC_WRITE(host->base, CON, val); + + return 0; +} + +static void omap_hsmmc_adma_exit(struct omap_hsmmc_host *host) +{ + struct mmc_host *mmc = host->mmc; + + dma_free_coherent(host->dev, ADMA_DESC_SIZE * (mmc->max_segs + 1), + host->adma_desc_table, host->adma_desc_table_addr); +} + +static int omap_hsmmc_dma_init(struct omap_hsmmc_host *host) +{ + host->rx_chan = dma_request_chan(host->dev, "rx"); + if (IS_ERR(host->rx_chan)) { + dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); + return PTR_ERR(host->rx_chan); + } + + host->tx_chan = dma_request_chan(host->dev, "tx"); + if (IS_ERR(host->tx_chan)) { + dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); + return PTR_ERR(host->tx_chan); + } + + return 0; +} + +static void omap_hsmmc_dma_exit(struct omap_hsmmc_host *host) +{ + if (!IS_ERR_OR_NULL(host->tx_chan)) + dma_release_channel(host->tx_chan); + if (!IS_ERR_OR_NULL(host->rx_chan)) + dma_release_channel(host->rx_chan); +} + static int omap_hsmmc_probe(struct platform_device *pdev) { struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; @@ -2497,6 +2724,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) struct omap_hsmmc_host *host = NULL; struct resource *res; int ret, irq; + u32 val; const struct of_device_id *match; const struct omap_mmc_of_data *data; void __iomem *base; @@ -2552,6 +2780,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) host->next_data.cookie = 1; host->pbias_enabled = 0; host->vqmmc_enabled = 0; + host->use_adma = false; ret = omap_hsmmc_gpio_init(mmc, host, pdata); if (ret) @@ -2613,6 +2842,12 @@ static int omap_hsmmc_probe(struct platform_device *pdev) host->dbclk = NULL; } + if (host->pdata->controller_flags & OMAP_HSMMC_HAS_HWPARAM) { + val = OMAP_HSMMC_READ(base, HL_HWINFO); + if (val & MADMA_EN) + host->use_adma = true; + } + /* Since we do only SG emulation, we can have as many segs * as we want. */ mmc->max_segs = 1024; @@ -2620,7 +2855,10 @@ static int omap_hsmmc_probe(struct platform_device *pdev) mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; - mmc->max_seg_size = mmc->max_req_size; + if (host->use_adma) + mmc->max_seg_size = ADMA_MAX_LEN; + else + mmc->max_seg_size = mmc->max_req_size; mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; @@ -2640,19 +2878,12 @@ static int omap_hsmmc_probe(struct platform_device *pdev) if (ret) goto err_pinctrl; - host->rx_chan = dma_request_chan(&pdev->dev, "rx"); - if (IS_ERR(host->rx_chan)) { - dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); - ret = PTR_ERR(host->rx_chan); - goto err_irq; - } - - host->tx_chan = dma_request_chan(&pdev->dev, "tx"); - if (IS_ERR(host->tx_chan)) { - dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); - ret = PTR_ERR(host->tx_chan); + if (host->use_adma) + ret = omap_hsmmc_adma_init(host); + else + ret = omap_hsmmc_dma_init(host); + if (ret) goto err_irq; - } /* Request IRQ for MMC operations */ ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, @@ -2707,10 +2938,10 @@ static int omap_hsmmc_probe(struct platform_device *pdev) err_slot_name: mmc_remove_host(mmc); err_irq: - if (!IS_ERR_OR_NULL(host->tx_chan)) - dma_release_channel(host->tx_chan); - if (!IS_ERR_OR_NULL(host->rx_chan)) - dma_release_channel(host->rx_chan); + if (host->use_adma) + omap_hsmmc_adma_exit(host); + else + omap_hsmmc_dma_exit(host); err_pinctrl: if (host->dbclk) clk_disable_unprepare(host->dbclk); @@ -2732,8 +2963,10 @@ static int omap_hsmmc_remove(struct platform_device *pdev) pm_runtime_get_sync(host->dev); mmc_remove_host(host->mmc); - dma_release_channel(host->tx_chan); - dma_release_channel(host->rx_chan); + if (host->use_adma) + omap_hsmmc_adma_exit(host); + else + omap_hsmmc_dma_exit(host); del_timer_sync(&host->timer); diff --git a/include/linux/platform_data/hsmmc-omap.h b/include/linux/platform_data/hsmmc-omap.h index 8e771851e07a..c3f2a34db97a 100644 --- a/include/linux/platform_data/hsmmc-omap.h +++ b/include/linux/platform_data/hsmmc-omap.h @@ -28,6 +28,7 @@ #define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1) #define OMAP_HSMMC_SWAKEUP_MISSING BIT(2) #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3) +#define OMAP_HSMMC_HAS_HWPARAM BIT(4) struct omap_hsmmc_dev_attr { u8 flags; From patchwork Fri May 19 08:15:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100177 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp204359qge; 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[209.132.180.67]) by mx.google.com with ESMTP id o19si7871912pfj.126.2017.05.19.01.28.03; Fri, 19 May 2017 01:28:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755690AbdESI1p (ORCPT + 25 others); Fri, 19 May 2017 04:27:45 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:10396 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753452AbdESIS0 (ORCPT ); Fri, 19 May 2017 04:18:26 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8Gwha018163; Fri, 19 May 2017 03:16:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181818; bh=hOcchWHNdS9cbiQIXglSXOjzBwmisiLI9OOnhYlBtv0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OV4ue7cayoFEgoGBrlHHFqKatRc1Ihy40WCYk21qdMZicBGhktV6vTFVZJhxpWPbq 153WVVWaS2VkVMw/b8xZWCWx8LYrnBnwEtXHevz1oaYbQe91otgEmGrktLsEihsjfN 3aeXU4DC2HpxcEvbGW0hm6yVycQ+NmYTz7GCaYjw= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8Gwt2027315; Fri, 19 May 2017 03:16:58 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:16:58 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQN009185; Fri, 19 May 2017 03:16:54 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 16/41] mmc: omap_hsmmc: Support non-1.8V IO controllers Date: Fri, 19 May 2017 13:45:16 +0530 Message-ID: <20170519081541.26753-17-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sekhar Nori OMAP HSMMC driver assumes that if the controller does not support dual-volt, then it supports only 1.8V IO. This assumption can be incorrect. For example, on K2G MMC0 supports 3.3V IO only. AM57x Beagle-x15 and IDK boards support only 3.3V IO on eMMC interface. Support device-tree property "no-1-8-v" to for controllers which are not dual-voltage and do not support 1.8V IO. Note that lack of support for this property has not led to any known regression in affected platforms so far. But it will be nice to be in sync with hardware configuration. Signed-off-by: Sekhar Nori Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/omap_hsmmc.c | 15 ++++++++++++--- include/linux/platform_data/hsmmc-omap.h | 5 +++++ 2 files changed, 17 insertions(+), 3 deletions(-) -- 2.11.0 diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index c6e3efb0f8fb..7c555e3ecce8 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -865,6 +865,9 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) else hctl = SDVS30; capa = VS30 | VS18; + } else if (host->pdata->controller_flags & OMAP_HSMMC_NO_1_8_V) { + hctl = SDVS30; + capa = VS30; } else { hctl = SDVS18; capa = VS18; @@ -2121,11 +2124,14 @@ static void omap_hsmmc_set_capabilities(struct omap_hsmmc_host *host) val = OMAP_HSMMC_READ(host->base, CAPA); - /* Only MMC1 supports 3.0V */ - if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) + if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { val |= (VS30 | VS18); - else + } else if (host->pdata->controller_flags & OMAP_HSMMC_NO_1_8_V) { + val |= VS30; + val &= ~VS18; + } else { val |= VS18; + } OMAP_HSMMC_WRITE(host->base, CAPA, val); } @@ -2567,6 +2573,9 @@ static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) if (of_find_property(np, "ti,dual-volt", NULL)) pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; + if (of_find_property(np, "no-1-8-v", NULL)) + pdata->controller_flags |= OMAP_HSMMC_NO_1_8_V; + pdata->gpio_cd = -EINVAL; pdata->gpio_cod = -EINVAL; pdata->gpio_wp = -EINVAL; diff --git a/include/linux/platform_data/hsmmc-omap.h b/include/linux/platform_data/hsmmc-omap.h index c3f2a34db97a..d7be21dc9ffd 100644 --- a/include/linux/platform_data/hsmmc-omap.h +++ b/include/linux/platform_data/hsmmc-omap.h @@ -23,12 +23,17 @@ * for example Advisory 2.1.1.128 "MMC: Multiple Block Read * Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_ * Revision F (October 2010) (SPRZ278F). + * + * OMAP_HSMMC_NO_1_8_V: The controller does not support 1.8V IO voltage + * irrespective of what the capability states. + * */ #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) #define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1) #define OMAP_HSMMC_SWAKEUP_MISSING BIT(2) #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3) #define OMAP_HSMMC_HAS_HWPARAM BIT(4) +#define OMAP_HSMMC_NO_1_8_V BIT(5) struct omap_hsmmc_dev_attr { u8 flags; From patchwork Fri May 19 08:15:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100174 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp203681qge; Fri, 19 May 2017 01:25:33 -0700 (PDT) X-Received: by 10.98.103.87 with SMTP id b84mr9323774pfc.235.1495182333234; Fri, 19 May 2017 01:25:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495182333; cv=none; d=google.com; s=arc-20160816; b=OfUOpkCpiN6ezSXuIEUVcQXGnSvrnGkUEsD7HjeJlMlLERtzFgPE/pm1j3OfVa9YoY ezkQoc8T59uVNpjwWlnLF1FHmjZslU4U1MlCaIbDPjEqXHEt8RtTC8fSnGwJWbz48qiA JGKrj/iLsLgxhZMTDgVfSLj2ahtJcXry8Zw9EU6sS07S0TIJvnr51kynlXKf8dGpReD1 1kpQ31lUMqAIPaW3Pa09HVs0/p6FCAnTGEsPYqpoC7sBl/XMRnrvRxM/IM85Z/PWA1R5 FSSX4P/LJYp5QTUxFjFtf3879zNCbxNgvaCaipUtGKl/gEn0bSlxvFg/aec7DMmVTH2b zvWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=WNllE6jU4gZ7FlOah5Y3x4VDT1LVFBXl4QLN+rk1Xb8=; b=db1LrUXDpZC3wkvcWU0aTR9BUxy6UoxJ0n8UxdIzACGIJjxvCErPLAz2cXvOPXt2EP svullXfGDnuPvXh9//o5W06cAiCBKVvhwoM0IWGLP++2ox/yyK7KZ2uQAkcnYj0bz2/t t5xSWnmchw2lYJnX56gVPvQy+ZpOyA9YoxHRfShAznSVOkpzMSi3PZUhD+QZrPDOyMkC 0UP5qLSRMtXkuzAjtUzvtm3trwje3trsvyGcKIFSfp8M+xh30txSeflli+669FPIJ6a4 uGang8cv6YHvPb0iKTHF27ptu5ZksmfaT4xjIsbFMQ4l3gCALs6T60ccuCJxW1fE7/AI 3Qfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n17si1604874pfg.215.2017.05.19.01.25.32; Fri, 19 May 2017 01:25:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755807AbdESIZO (ORCPT + 25 others); Fri, 19 May 2017 04:25:14 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:23243 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755276AbdESITW (ORCPT ); Fri, 19 May 2017 04:19:22 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8H8iV010059; Fri, 19 May 2017 03:17:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181828; bh=8EQYivV3WHlTCKKs4zomkhOzUEH/MQSjZv2nV8zUuz8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JKg4gZIBrlvfHF1TUITbA2jua8lKyS+pHimBeSDVc5LhM60gUB9kiKBAqOg6L5i2H HXpY/vI6eedNYmC0FTk076UkVpL+ylZbRHNlHryS71BfyQyF9skzS/Sws5h5FHhp/Y WCwYirM04wACe8l+aVRIG3cDI25QbvdgxYbQGtRE= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8H3g2027626; Fri, 19 May 2017 03:17:03 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:17:02 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQO009185; Fri, 19 May 2017 03:16:58 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 17/41] ARM: dts: dra72-evm: Add vmmc_aux supply to mmc1 Date: Fri, 19 May 2017 13:45:17 +0530 Message-ID: <20170519081541.26753-18-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add vmmc_aux-supply property to mmc1 dt node and populate it with ldo1_reg to reflect ldo1_out is connected to mmc1 IO lines. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra72-evm.dts | 4 ++++ 1 file changed, 4 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index cd9c4ff12654..1c570236a1a0 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -43,3 +43,7 @@ phy_id = <&davinci_mdio>, <3>; phy-mode = "rgmii"; }; + +&mmc1 { + vmmc_aux-supply = <&ldo1_reg>; +}; From patchwork Fri May 19 08:15:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100166 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp201687qge; Fri, 19 May 2017 01:18:14 -0700 (PDT) X-Received: by 10.98.103.207 with SMTP id t76mr8819489pfj.147.1495181893912; Fri, 19 May 2017 01:18:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495181893; cv=none; d=google.com; s=arc-20160816; b=g5N4uIzbrUTXaj06cR756GE1Hbkn0JTm1OPnD8asjNxDXDDeiUQolyadjxahHMrQiL 5E/kIuM62MDcbx0Igk7vK2MVxa7paYblkXPT/fa4RA/+s9OtBiIW+ZWO+jyqBqurcG2w /ADgb++/sbzaYtJbI1stpUxBtjrbZ0JrnqwNCvy2CqIJQqorM/yCkJmm4Cm3ztK2CoVF mxsWmsRYcc4RdhF9PuEG+HvERTZgxWYzoqJluUdNlH6JHAmPPu0EjSrmzyh5fHrx5BnA D5jDKetlJYZyJY7BGLk0P3XWizxS2PsmxAcxBfeLn0YkEg199jF/0uWWCWjkq07RMB/G 2xVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=74cGLAqY+QNfRETWfm7nReI1mahf6JULR6R9cTMvTiQ=; b=trtNoKU0+TvI8HJawSEytFm3r62XO41FYHjBhgKCIwgO8IB1OPsGFraFOp6OwLscet Y9I18VpSa6MZBWq+EWypp0LsB3iGAIW68oSKEHdsTsm8c53RCHpUo7yYVBmRwTE/Xffj E22Di2wbLuvJkH0RxumsmFo6fdCdNDylxSbgtE3L7NSpdEgMOLfoSq9hHdp3H4BA/PHI XXLQmkLJ6DJguH8RrmjBvCFund2Yx+toKLM2XBCtk6JWOt8tIavoWsgbkg+wTeqFTKGL lk/RaVAD7ViNusK3cnDVmMvENgGaP9Fv55l/W2bzENqfuA9ehy0qlm4y9fJSjnCYURUq WpOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g1si7752481pln.18.2017.05.19.01.18.13; Fri, 19 May 2017 01:18:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754645AbdESISG (ORCPT + 25 others); Fri, 19 May 2017 04:18:06 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:46375 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751772AbdESIRr (ORCPT ); Fri, 19 May 2017 04:17:47 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8HCAL005994; Fri, 19 May 2017 03:17:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181832; bh=DJOS6uxQChVpVrisNXhcDnnnsxA8BCyj0Ukr9mwAKDY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=k3gbjnMKVidKra7QEnVVI97iNZeDhZ4RLUevNRm9mvzOZuvTm3jBWm3VY0+3Fjq/W lphx3Dt0UxyTkPZx9KTsdzJGe3UZ+pJyZ43t80gvqtZDgUws+RA2kwoQmhCIRkVTmN lAkCgNj8PNARSf0L6zJVuiYCAVomsMLf149kIHsk= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8HCp2014670; Fri, 19 May 2017 03:17:12 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:17:11 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQQ009185; Fri, 19 May 2017 03:17:07 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 19/41] ARM: dts: am57xx-beagle-x15-revb1: Fix supply name used for MMC1 IO lines Date: Fri, 19 May 2017 13:45:19 +0530 Message-ID: <20170519081541.26753-20-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The dt binding documentation of omap-hsmmc recommends using "vmmc_aux" for IO supply lines. However commit 0af28cc92690d8c ("ARM: dts: am57xx-beagle-x15: Add support for rev B1") added it as "vmmc-aux". Fix it here. Fixes: commit 0af28cc92690d8c ("ARM: dts: am57xx-beagle-x15: Add support for rev B1") Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.11.0 diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts index 39a92aff0a0d..6ae94ab52b7b 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts @@ -20,7 +20,7 @@ &mmc1 { vmmc-supply = <&vdd_3v3>; - vmmc-aux-supply = <&ldo1_reg>; + vmmc_aux-supply = <&ldo1_reg>; }; /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ From patchwork Fri May 19 08:15:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100178 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp204487qge; Fri, 19 May 2017 01:28:30 -0700 (PDT) X-Received: by 10.99.125.67 with SMTP id m3mr8965078pgn.153.1495182510251; Fri, 19 May 2017 01:28:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495182510; cv=none; d=google.com; s=arc-20160816; b=MbgnswpYZV88zHixYLPdX7jcd/9HAz+Fo9RmzpwmVyVuD4JkDOoWIRXkkdypNHzu/D pQzerTjCB1CgBA8ox9HDS4U4HiTVwFQUNE9SFRKLp7botp7lfyqk6Fu7jNqsbAuOW4WR FGortcRGcg4fxUcD48QK+H0guqokjMm93pmNNCDZU1TrO0IYStleZR55OMlB1uaGrxwj IEslLlCxhcYQfiVJC5JhVM7wWPK/CKJZcXQ3StuLcrCVh9PIgZPbOBkNce5aigtBDQ8L 6304zL4L+E/YErfDE5PaKwO8nSo/A020eSuWIUKg5kBq5kqSKTePnbSO59PLwmKY8cqu 2BHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=CtcOp0F9omtRl/Q0iHBwejtMi5x93+hupjUJB1KOOdA=; b=xKf1J5pe9Vw3X9Ex950TFHstzGzxIaNq3yiZ6YEpF1lmEDGINvrhrlN0upmBGBZ2Yc C3Ub7Bz0iSls0dPbjWsRiAP67TaPdI1/E6YotmoWgXo7KHGC/+W8IJtbB6HDEMBn08Bd Y3i1VvhvHxHhyDA4RmJrSiVrBN0+t5v+lUL22+kMYPZhwIix+VlGxtZXH9HpWY14qm0T yqTFIAroTYKJ47W6p1arDoeF7ivbJgVL3QMChfp5aV01BPhz42F9gCel4uQR0Fd/vr0Q qD6XdQdZ9x5JwqgHWEkoBA5444NNgAkV3mRRTkTmYXcsn16KA+fh9H8YfpxZByLdBm2v J6Ng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a186si7621246pge.285.2017.05.19.01.28.29; Fri, 19 May 2017 01:28:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755608AbdESI2W (ORCPT + 25 others); Fri, 19 May 2017 04:28:22 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:10384 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751772AbdESISL (ORCPT ); Fri, 19 May 2017 04:18:11 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8HdxF018259; Fri, 19 May 2017 03:17:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181859; bh=1j8TDwUEHSPp/y0FvT8FpXznA+XPyn6smnOg/f8kWRQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vuTsfZMeTBCu2sg40jcvrSNQohXNnc7MxLFhVhwq1BuP061VoXxlRWR7wGtFoP1bO EzDRpSGywZob+wHleCmzC+qqGxl3laMhccTjlt9YlbWf7Dr3BywYsfQMEsLs4DbSth GqjVErR2fIhLzMh4aVCBEZnG/uJFtVotazRCXgFM= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8Hdfp028718; Fri, 19 May 2017 03:17:39 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:17:38 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQW009185; Fri, 19 May 2017 03:17:34 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 25/41] ARM: dts: dra7-evm: Add pinmux configuration for MMC Date: Fri, 19 May 2017 13:45:25 +0530 Message-ID: <20170519081541.26753-26-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Include dra74x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra74 SoC and use it in the pinctrl properties of MMC devicetree nodes present in dra7-evm. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7-evm.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index fbcb3199defd..64955e8f06d2 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "dra74x.dtsi" +#include "dra74x-mmc-iodelay.dtsi" #include #include #include @@ -451,6 +452,16 @@ * is always hardwired. */ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; + pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; + pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; }; &mmc2 { @@ -459,6 +470,13 @@ pinctrl-0 = <&mmc2_pins_default>; vmmc-supply = <&evm_1v8_sw>; bus-width = <8>; + pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>; + pinctrl-3 = <&mmc2_pins_ddr_rev20>; + pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>; + pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; }; &cpu0 { From patchwork Fri May 19 08:15:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100168 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp201927qge; Fri, 19 May 2017 01:19:04 -0700 (PDT) X-Received: by 10.84.184.12 with SMTP id l12mr10161863plc.9.1495181944258; Fri, 19 May 2017 01:19:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495181944; cv=none; d=google.com; s=arc-20160816; b=ilIsrQvBal4/7BPodj9qLtXIy6WNr/N24+W618a3+gdx/rhGROG6Z6JhqptYVLCs68 IY0lnklhV5G2IoUdY51Kk1s6/m9wEK0cVXF+6cxooSVTrPeLTtfUvNzMpzyZYUN5VAb8 i2z8cdx3sUgObhtAcJ2jsZcKKoiy8jEVZOyfLyAiPqXDVCklbnwrIgGWNLXTGm1cANSl ZdVxqMoLYUBOXJt/FQzKknbdIcTAnMXvT2RQRq9sS0jV139GBgHXvrQb8z24EcgewBOR c3NedMkoL7WzDpTgNxVUaO42t/KxaJ9I49Mz9/XsFVFEY8KhgVQFe3oSu1EzbgQrOpXX HCDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=lONeGpeBHM+dKm92apLVnM5onRGMcjqlWdO6FJo7GrQ=; b=N1RGQRMINSO57tgUgI1tYIZKi0oZkxnGXSYXwaOnWkxx08yB3nYeeJEf2kX3FOnZFi MGkf3qU6uIlwMO7MtUjKV5RufHqZXy1BQOv7H8Dby1ymgpfxd/T/3EAUHyKz+KxQu8bw XVHidSINjHloyC/DBtQUG0N8bxYMaiKtEKaGd3RVAw4QcGFbrXKgiZ/myzUXCi5uXKpv PBIR/wP840ZuCwty3BW02u6rAelUIHBnoNSjAtsfU0Lv7ZzTi8UYVYPYjoV9A+PSfHaJ VuGpqkbpC5m02ofMIR6fxFtyPMSvjpa9XmkXzGiqGEqzQ2hinhSaabYFaZhPSjKubPCP s4Zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t18si7810952pgn.128.2017.05.19.01.19.03; Fri, 19 May 2017 01:19:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755183AbdESISw (ORCPT + 25 others); Fri, 19 May 2017 04:18:52 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:10408 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752560AbdESISn (ORCPT ); Fri, 19 May 2017 04:18:43 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8HqXu018305; Fri, 19 May 2017 03:17:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181872; bh=rXXLF97hS0A8vSXSJtQlSooowsBmb4vU+Ig0JmWhttE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jIynunJkT3oaAKO0HPh9mWd/s1m/OkzT/p6yaO+GMHm0DHayrHVBA3hi5nBCYCnqY cZjhK4a2rRl5mxu7OGsi7bx5cx7FEZchaZPmIpaZpXGS+jKght2bl2ZrkSscdq1seL UtKgXVXeRV/kiMM3eES2Ms4eNPspEOsjs5RjeNmo= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8HqPE015769; Fri, 19 May 2017 03:17:52 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:17:51 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQZ009185; Fri, 19 May 2017 03:17:48 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 28/41] ARM: dts: am571x-idk: Add pinmux configuration for MMC Date: Fri, 19 May 2017 13:45:28 +0530 Message-ID: <20170519081541.26753-29-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Include dra72x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra72 SoC and use it in the pinctrl properties of MMC devicetree nodes present in am571x-idk.dts. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/am571x-idk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index e685c8e811b0..875291d1bdd7 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -11,6 +11,7 @@ #include #include #include "am57xx-idk-common.dtsi" +#include "dra72x-mmc-iodelay.dtsi" / { model = "TI AM5718 IDK"; @@ -72,3 +73,21 @@ id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; }; + +&mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; +}; From patchwork Fri May 19 08:15:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100167 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp201839qge; Fri, 19 May 2017 01:18:44 -0700 (PDT) X-Received: by 10.84.241.206 with SMTP id t14mr10070619plm.48.1495181924891; Fri, 19 May 2017 01:18:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495181924; cv=none; d=google.com; s=arc-20160816; b=UFFMpWpgCadgD+kjsQLr44kajNjFFgDBBBws1g8dYXJA8iOcgmxbwVf5VbGZpoCNzv kAqENJZM/NT8yBWwKINnR6g+7ogAcSl6UbzBwmjQtJ4jnC6cSzeoWF1KcHYPLL+kahzv Ncso8NAbxZEzOWNIGcujcDYAlyi937ydONUX6QbMza9uYLmN7IpKm1ETI8xLwQlcVwoI o6XuBYDtT0ITRhZIBOwh9n+0RzRJaMCzzrfnLfjhAZ0wPlHJ56swDGJbQPxSPWWror1y 2OiM3gvUPE1gJsJ7eaoZOwDIzMwe5oGbAIjBZK2n6OTMsrvbKgHNzOyOVvpVEVRZ7+Iy +Obw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=mzvkeIT3AhG9zhPg/HKTg0CecptIR571J2uqtOEQpcQ=; b=qB3xvrdWj2WWDFMuR7eYwQwE9I0D5ttVrovcEnX2mqsRD+hO0dsFo8UiHlhnhl9j17 0I2t+SWlxEO4dcrHZSAYYuKYhZvaSwrrPc5/6Dl7wQbV6iNlFS8E9mOYdpWjjhsioag3 Dyerqxn6hgZK2WWi3H7bmWs3naCR3jvf5ZKJFxRL86T1VRayP5vKd63iAom6gqSvk4oD sq1Pmh2AYJJhHe+D2ge3fl7TW5UL8n3GpAKRDO7KSnd6dRQaFkhe1R38tHnjlf0PimSu x1GAC5DfrI71xm/tI2qZBG6DMM9MwLpD2dhHr3WbiGBblAYXo/3ON/P5qvtzw7JnrMKM oAOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b78si7616830pfe.220.2017.05.19.01.18.44; Fri, 19 May 2017 01:18:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755037AbdESISk (ORCPT + 25 others); Fri, 19 May 2017 04:18:40 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:50318 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752860AbdESISe (ORCPT ); Fri, 19 May 2017 04:18:34 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8HvAf024575; Fri, 19 May 2017 03:17:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181877; bh=RWo9O49SJSs1+9hJktXcCEWPkgm6objj/QL/mB7g3sk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Yz46/2BbZZkc8wOCRvDR3dVqtexeAmKopaQNUgMj1KhZhRSlBBSI695wOMPVeIkML Rc1aTkNNWjxuikkYn2x+VuVgBOnN/27TlPD4UDKuq9K0rwRTUz2rNjf2fzvSaE9VoI nZGgWqT/HP3SM0bzaZnU3MW1S1NHxze9FS0WlXAM= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8HvOe028979; Fri, 19 May 2017 03:17:57 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:17:56 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQa009185; Fri, 19 May 2017 03:17:52 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 29/41] ARM: dts: am572x-idk: Add pinmux configuration for MMC Date: Fri, 19 May 2017 13:45:29 +0530 Message-ID: <20170519081541.26753-30-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Include dra74x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra74x SoC and use it in the pinctrl properties of MMC devicetree nodes present in am572x-idk.dts. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/am572x-idk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index 1c112eb25db4..79fac687428c 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -12,6 +12,7 @@ #include #include #include "am57xx-idk-common.dtsi" +#include "dra74x-mmc-iodelay.dtsi" / { model = "TI AM5728 IDK"; @@ -67,6 +68,24 @@ }; }; +&mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20>; +}; + &omap_dwc3_2 { extcon = <&extcon_usb2>; }; From patchwork Fri May 19 08:15:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100170 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp202166qge; Fri, 19 May 2017 01:19:57 -0700 (PDT) X-Received: by 10.98.200.23 with SMTP id z23mr9279061pff.18.1495181997791; Fri, 19 May 2017 01:19:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495181997; cv=none; d=google.com; s=arc-20160816; b=BFcnVEGBpxGeIToF38PTjKZF9hVxl+LFYLE54JN38QiZRXCnSraysV1JDIMMRrgL3J 5uT7sVD9lOpQe/HC4l5OhVOGa3TI50ARpbLf9/jyMerRSX/ghYc6YAXG6sdxm4pdWQSA XN80TvMBCcSqTqdWl1IiztJU5Y6ix/4Ha3M5af9d9PGL+WeyGNEOB769YdyIc4RCb9NT D/8f98G4atlqUlXa73PV2kSWWMhl6zvoANMO0BCQJVD6qSTs4kUGTrHn45vOQu3WAkmM DFrUPqZfAHa4Yp5pt6TcMIWSmormaj0EUhwe42lKxJ2Yv9XtY1dAdi+M4Wfr8gpVKZxK Kw2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=wCFKHo1j0JLsGFHHPCC6f9IEbaoFcO0YsuZyHDwtl6s=; b=pMm6Yi5nFQQDZDKbd2upEmXlu7d9H9i1himuYujgvHOkzPvBz39jvSVWDKZ43EBcHq ko7GDnfggecvBhm092fgrr7w1xvO6C1k7b2M7FVbuBkJsaPBPZQ2bBsL+m2DPbUsp+bU 9eWKTFX63jzxs8qxPvu2UsQKGpr7Ux7xEqq+Sz7tZ1DDcO1vdOq3umBoQSJJbas/Sh+V C2YHLkObzGTITbR0QKVsNV2sY9ZktdIDLqgH6kMgMJJ0rfbZVjWeqtkQcJFpFVW7vfu/ nfdD468BUSJonPoKi41Z4PoeteGbupBPnkDR5H97SlFuKZmsyt+exiaQv6goh2QEfAWN OGWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j80si7677271pfk.390.2017.05.19.01.19.57; Fri, 19 May 2017 01:19:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755413AbdESITh (ORCPT + 25 others); Fri, 19 May 2017 04:19:37 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:10427 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753420AbdESITa (ORCPT ); Fri, 19 May 2017 04:19:30 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8IFOb018359; Fri, 19 May 2017 03:18:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181895; bh=JkIPIdadfStjwV/JSetfeOJQ8qyJtpxjR7LantI2dl8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=q7v0KXxTHZ1+dIUbgfnISn6p2MZhWqLZ46lSIM0av7ZvGuwOVnv9e9w2dAtflAMM0 MrbTUmYHG6SYKcBX/t4AsTuWneFkBuwK9O1m/cCHf32azqgT1AOE1lsAaLnEOIT71/ F8zAfdFRQcaDgKkzVZ3FFySbkh+ueB6U7UL/UynE= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8IFwl029827; Fri, 19 May 2017 03:18:15 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:18:14 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQe009185; Fri, 19 May 2017 03:18:11 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 33/41] ARM: dts: dra7: Add "max-frequency" property to MMC dt nodes Date: Fri, 19 May 2017 13:45:33 +0530 Message-ID: <20170519081541.26753-34-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add "max-frequency" property to MMC dt nodes and set the maximum frequency to 192MHz for MMC1/MMC2, 64MHz for MMC3 and 192MHz for MMC4. pdata quirks must be utilized to detect presence of rev 1.1/1.0 of silicon and adjust maximum frequencies as per restrictions documented in i843. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra7.dtsi | 5 +++++ 1 file changed, 5 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 5a262e1a0313..38fb1828e26a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1045,6 +1045,7 @@ dma-names = "tx", "rx"; status = "disabled"; pbias-supply = <&pbias_mmc_reg>; + max-frequency = <192000000>; }; mmc2: mmc@480b4000 { @@ -1056,6 +1057,7 @@ dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; dma-names = "tx", "rx"; status = "disabled"; + max-frequency = <192000000>; }; mmc3: mmc@480ad000 { @@ -1067,6 +1069,8 @@ dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; dma-names = "tx", "rx"; status = "disabled"; + /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ + max-frequency = <64000000>; }; mmc4: mmc@480d1000 { @@ -1078,6 +1082,7 @@ dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; dma-names = "tx", "rx"; status = "disabled"; + max-frequency = <192000000>; }; mmu0_dsp1: mmu@40d01000 { From patchwork Fri May 19 08:15:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100171 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp202377qge; Fri, 19 May 2017 01:20:43 -0700 (PDT) X-Received: by 10.98.79.28 with SMTP id d28mr9130383pfb.56.1495182043133; Fri, 19 May 2017 01:20:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495182043; cv=none; d=google.com; s=arc-20160816; b=m8bB9Y/dd4eaRevccXV1OsBuMt2LnLYqSUfoIeOpgAmdkvDx+fyJH26SaYPlKcxAA/ jnZfqFPtKqdYraJGmeexLmZtC8iK4SHFpqTVN/Udhh02AhT87RIX3f+mXRxpRHtFnaEF zkUeL8ZDCUmu5cQuugJekhqZvfyQ6xqNZ960+ykvkID8V/p9Z93RcCrcyTcWoiJFKnY7 zctkqOyC4ZpEwvZYzKEBjXkX0kob7eyYlRgQjC9UrziMmmIuTY8Q9yjldEyVTY/VUNea LhFHdJ5GZ6CjfUhjH9YTl/CeOpOGS+F5ZmTpzob5GNvzmWqxXP/RqNpb4ft7WR4Fl2eK JYmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=vS4CeWF800A/1sBl3uY3lZwhxDHNYb5gw3oNOZi/e9Y=; b=bLFG2HGHruCJ7jiU1y7kylzBVx4jerRpNlnmPN48Wb7dNlOYY5EvEFxOGqeGyBZVSJ Zo8T4Hh/zLtbXjon4oh8gRT5p7BGveZ7pZOYdRR2A+jDSX5Bx+f2liNv21BhHaXkBXRv tQ56rcQK/ApwYYpCP7wpc+qDq3WTUIjpSWzMWpmAlt18pPsnMg56YCvpxjZ31NtyIEFm tfhhYHyX4FUlDpecPwwUA7UszE9No1/E2LNAv2hYHLYc722X40tW7HxKIOjI4LnW0ZsR yxVZvRVcDEF2XiWamc7sJ/OhHKiwKjxleTez6EJULW/OvRkxpY3fOTANmS8EyQuJjYdW s1lQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g63si7703909pfc.46.2017.05.19.01.20.42; Fri, 19 May 2017 01:20:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755594AbdESIUj (ORCPT + 25 others); Fri, 19 May 2017 04:20:39 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:23306 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753208AbdESIU3 (ORCPT ); Fri, 19 May 2017 04:20:29 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8IOi6010328; Fri, 19 May 2017 03:18:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181904; bh=H/N8NixbYK9Oco5rMn9ro3Zzu5mnFNBPe7em0TC6UEc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rXwDYc/tLnCmtRejE4+v0BqUs4p6TpvwvpjOa2mwU9Wqc6nduquwVUQmM/OhvPMNc OTX6rN0eREZmayVlqheZLWfhdfamUlqMi7A2zt9iEzxA0opKT3TLleAKUx6u5hElba z4Ao8zu6h7+DmairekIvhSt1wWkssUhZ58OhrjYc= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8IJ3L016819; Fri, 19 May 2017 03:18:19 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:18:19 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQf009185; Fri, 19 May 2017 03:18:15 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 34/41] ARM: dts: dra7: Use new dra7-specific compatible string Date: Fri, 19 May 2017 13:45:34 +0530 Message-ID: <20170519081541.26753-35-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use the new compatible string "ti,dra7-hsmmc" that was specifically added for dra7 and dra72. This is required since for dra7 and dra72 processors iodelay values has to be set unlike other processors. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra7.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.11.0 diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 38fb1828e26a..40b9eb96cdeb 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1035,7 +1035,7 @@ }; mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; interrupts = ; ti,hwmods = "mmc1"; @@ -1049,7 +1049,7 @@ }; mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; interrupts = ; ti,hwmods = "mmc2"; @@ -1061,7 +1061,7 @@ }; mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480ad000 0x400>; interrupts = ; ti,hwmods = "mmc3"; @@ -1074,7 +1074,7 @@ }; mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480d1000 0x400>; interrupts = ; ti,hwmods = "mmc4"; From patchwork Fri May 19 08:15:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100169 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp202069qge; Fri, 19 May 2017 01:19:36 -0700 (PDT) X-Received: by 10.84.174.197 with SMTP id r63mr9950907plb.67.1495181976870; Fri, 19 May 2017 01:19:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495181976; cv=none; d=google.com; s=arc-20160816; b=W5+Yh7UioAOzcUOQwkYLU1wVuKCVfkkSljoBn6OxT7oVOEFz845ojS9zSlRPJz7Wjv 5PsltSFl2fPYTYplN1Vp/jZ8v5240NroiKE+mtAn9xZmwRT25jYaS/78bo9ABcwYCb0E DDiQnCCpNdUVhb3uSSkgpEVtntIOhg/bflwh2OzGB/JeRlR1IUj5vrZvRIH38Fo9blcx Qrwha+sN6Psv8xUGGSaKpZ4qVvCl133d77N4+pXtY3/SBRhoG23qZZu3YQYxIUp2b1mJ Bf/sPL+DgrqOZzUwlGKeVPmpsXI9y6d2uIFPx7mxELKBK3lQXrxWyr2F+f8CdqRTf5F7 JYKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=LhKDGhkTyVDiVJZjYdOhS21p59fNJdIEEhxZ/rM3fvc=; b=RoL+Dr7fk76Kq5PEybhL35zDqG4YVXuPHZCXmqYniUD1jAa9r4J5D3yf1QmCGjJ3kI dUy4F84c/ZPpPrk6nSjx1PihpxriXZOHKsMZl7YumVndckxMylxYpUZG2oG4HbapuwH8 IchYGsA+BSpUvMTJTnO65aLb/ix2m4AjPrbslxf8BuVCP2jp4m/+Z3XyOkCDQoGIwECp LKSHlyA9h7+a64R4ZIpKD0rUzcMAsNZScfzPSbTdmjB5WP1GFTD32VY1Wu/DdwtlRy5J 88EXqpPH5y1Ay41iTg1iq3p4qdDV+eZogLo3mdHrK6hiiatRmJ5H7uAoQqaxZeEIWp4v +kQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si7674039pgp.311.2017.05.19.01.19.36; Fri, 19 May 2017 01:19:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755370AbdESITa (ORCPT + 25 others); Fri, 19 May 2017 04:19:30 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:50362 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753420AbdESITT (ORCPT ); Fri, 19 May 2017 04:19:19 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8IbwQ024681; Fri, 19 May 2017 03:18:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181917; bh=MF0V9peq6EMW9tO4//NREZber61OWzvjQ2PpTS6VWyg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vEDwgwz65BlE4TvUjjB624AVZU635dBguaQdowvzDrckLtRvxfUtKQMgGoITUapvv aPNKGb67fIkZzgfLoe978Rre0OfvTzNIK9G7x2Z78HEZygNz8F4tX6+rMrVfDvXcy5 VasNLAzkRO11JYFrwUUBAYzggv5KeFVXVmTrG9/I= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8Ib71030214; Fri, 19 May 2017 03:18:37 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:18:37 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQj009185; Fri, 19 May 2017 03:18:33 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 38/41] ARM: OMAP2+: Add pdata-quirks for MMC/SD on DRA74x EVM Date: Fri, 19 May 2017 13:45:38 +0530 Message-ID: <20170519081541.26753-39-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sekhar Nori DRA74x EVM Rev H EVM comes with revision 2.0 silicon. However, earlier versions of EVM can come with either revision 1.1 or revision 1.0 of silicon. The device-tree file is written to support rev 2.0 of silicon. pdata quirks are used to then override the settings needed for PG 1.1 silicon. PG 1.1 silicon has limitations w.r.t frequencies at which MMC1/2/3 can operate as well as different IOdelay numbers. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/mach-omap2/pdata-quirks.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) -- 2.11.0 diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 9700a8ef0f16..6b433fce65a5 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -434,6 +434,26 @@ static void __init omap5_uevm_legacy_init(void) } #endif +#ifdef CONFIG_SOC_DRA7XX +static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1; +static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2; +static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3; + +static void __init dra7x_evm_mmc_quirk(void) +{ + if (omap_rev() == DRA752_REV_ES1_1 || omap_rev() == DRA752_REV_ES1_0) { + dra7_hsmmc_data_mmc1.version = "rev11"; + dra7_hsmmc_data_mmc1.max_freq = 96000000; + + dra7_hsmmc_data_mmc2.version = "rev11"; + dra7_hsmmc_data_mmc2.max_freq = 48000000; + + dra7_hsmmc_data_mmc3.version = "rev11"; + dra7_hsmmc_data_mmc3.max_freq = 48000000; + } +} +#endif + static struct pcs_pdata pcs_pdata; void omap_pcs_legacy_init(int irq, void (*rearm)(void)) @@ -561,6 +581,14 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu", &omap4_iommu_pdata), #endif +#ifdef CONFIG_SOC_DRA7XX + OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x4809c000, "4809c000.mmc", + &dra7_hsmmc_data_mmc1), + OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480b4000, "480b4000.mmc", + &dra7_hsmmc_data_mmc2), + OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", + &dra7_hsmmc_data_mmc3), +#endif /* Common auxdata */ OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata), { /* sentinel */ }, @@ -590,6 +618,9 @@ static struct pdata_init pdata_quirks[] __initdata = { #ifdef CONFIG_SOC_OMAP5 { "ti,omap5-uevm", omap5_uevm_legacy_init, }, #endif +#ifdef CONFIG_SOC_DRA7XX + { "ti,dra7-evm", dra7x_evm_mmc_quirk, }, +#endif { /* sentinel */ }, }; From patchwork Fri May 19 08:15:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100173 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp203438qge; Fri, 19 May 2017 01:24:40 -0700 (PDT) X-Received: by 10.84.233.132 with SMTP id l4mr10008212plk.148.1495182280113; Fri, 19 May 2017 01:24:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495182280; cv=none; d=google.com; s=arc-20160816; b=ntLw/ko5pliaR1xPxeAHtoKM9iOda98E8+qq7M8QyRVpnfr+3m5seFUR2nexxlWxUu yN/xc+t3dfLveMfXF2YKuKwIjzj1MFfbnW9lkgxzT9sFl7HtUhbe9a1z/ZLSv8Mf5SzY Nol27zThK2LERXPRJL0UNfKF6+MCsILScW+iRkOKKAPFLGQLA/7EhHoDNRTUfBN/KKdG Vcr/T6odLa/Hl6UzVbAxpKSm8GCQXzZc7Jh6QYQf05MCM/NLSYtwzsrwXaTXzQ3UxoYO g0oc5Px/7uChwPLONC5f6zkLHCLoMYhTAzcIcCAy7jOwYL7+EFJX3WKl2W/h/eHjCCGa tt7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=a6gVFt+MV6tjyEQrqcW+oSlsiZ+ZG5mdO5EA8DgBOXA=; b=zclkHuThQAoFhgjrCZTr1BJw9qqbcdj7kSPEo/fSYaJJoleCR8ztLziVzfj4WVEASp RysGxSJRasTcaNSbVOsT9+AKnxkzy4ELgaxO+cgL6APAuK10dP7UX724BcbZ8B7wFbw0 Mt05HiZrqbikr62eaOhA+rXq01C+FPHmBFp++fJHisW5c7LtWfZSB4mMLn1zMFU8pSnJ W3CF+bCOgkkNZ47YBO/odiSvkDqYh9NDXA6i2rINRaGMoECgUFMbODdND3lm+4tvP95W BaVAhmOuP5ExOhHC6CT/2x1iXHc0mPMUFc40OhuCBirb+S6OLD4CEZ+npRKUkumq0hsA E4Vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x26si7731985pgc.126.2017.05.19.01.24.39; Fri, 19 May 2017 01:24:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755621AbdESIYh (ORCPT + 25 others); Fri, 19 May 2017 04:24:37 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:46478 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753221AbdESITZ (ORCPT ); Fri, 19 May 2017 04:19:25 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8Ig3Y006283; Fri, 19 May 2017 03:18:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181922; bh=tPCiKEkwmBjasHozSD8D8PRVNxzUA9rURmOiWEfQjro=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IguaDULFip7C/NQ65aPPOdecd2Y0cdJ10HsI9uhSYNFCv67mfDzfNtXHekK8e42zQ lxMZJ34JBu1lcKQxwcRm51A45hdjvXMxRHdlU0g7yytvBOB36g5wXEf4dE/iZ0qnJ2 /YEfE564D8h/+i3EfjDQDyBvky1GVIFQEDZr9+2k= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8Igmn030285; Fri, 19 May 2017 03:18:42 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:18:41 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQk009185; Fri, 19 May 2017 03:18:37 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 39/41] ARM: omap2plus_defconfig: Enable PINCTRL_TI_IODELAY Date: Fri, 19 May 2017 13:45:39 +0530 Message-ID: <20170519081541.26753-40-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable PINCTRL_TI_IODELAY since it is required for MMC module in DRA7 family of processors to configure "IODelay" values depending on the enumerated MMC modes. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/configs/omap2plus_defconfig | 1 + 1 file changed, 1 insertion(+) -- 2.11.0 diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index a120ae816260..4d92f308349f 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -246,6 +246,7 @@ CONFIG_HSI=m CONFIG_OMAP_SSI=m CONFIG_SSI_PROTOCOL=m CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_TI_IODELAY=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X=m From patchwork Fri May 19 08:15:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 100172 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp202471qge; Fri, 19 May 2017 01:21:06 -0700 (PDT) X-Received: by 10.98.198.72 with SMTP id m69mr9270677pfg.169.1495182066142; Fri, 19 May 2017 01:21:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495182066; cv=none; d=google.com; s=arc-20160816; b=k1frTbm1ILkxYDfcaGFp3YaJTC+V/x+OwUqrsCU01ra3b9WLAZhruuiVlX7U1H0jiV iGoCUMU453sZ/iiMY2OsoajTyqK3UPvYVM01y/5seMTGq+i5AIamqE6ZdNLJ5kYMyHEs GEFq0zY8Bwkg61ZuXNJQYJWzYlZ8FfjGSIsfrwK4grOXMQOhDiy2Yr3XINy6boVTOYNR B1I5Yw/U9PNlCKdE30KHEj+E+ocUcJT/5a3Ej3EIeamwjmxS9e8zxf2am4YT5w9G1Rzg mRwJ1a9PaCLTNHR/+MT9ObOiz+RFC0fjgRWJCo3VSGjcGxJ2IsC6ZLYN0TCru71ReEDu Zlug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=0YEnFOvhJgsLbzOl6Tvk70Hsimrxrl4efr1+n76YCOM=; b=rYLS/5Oav4T6NHFfv+2zo/R8Hj7El4A9kBLOnWXDToozMLDG98TdP8oD2TGtlQH17q W8aR3ROsm900b4Cx9Ll3AzM947bC498OAzSrLRhUcBWhr6/AKXZrAyodh9BLozSNjaRj N+xQWEfJx3ghr4DCI23XbBw2RyZv0YlTPX+BKVRa31Pffnk+XTJYwsiBjHdF7enNNtiZ SmwmR2pXmSPOyKD6Z6a/BxkuJku+T0scOfQbZ0GOpuN/8xnVw/2ssBozrKT7cE20LM2y BgjOLgZIY+HkzscbhENI6fLiGPhFqKvUJGCLv9yjBX5l4kGePyzGwBLWBUl2vIELMNeM A8mA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d10si7803658pfe.85.2017.05.19.01.21.05; Fri, 19 May 2017 01:21:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755708AbdESIVA (ORCPT + 25 others); Fri, 19 May 2017 04:21:00 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:23327 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932125AbdESIU4 (ORCPT ); Fri, 19 May 2017 04:20:56 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8IuIp010417; Fri, 19 May 2017 03:18:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181936; bh=WqBwL1O7RoZRlItAR4DwmYFmBvxXrwHiu7DJcJyAcYw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pjIH4SAVNEZWxXTd4KueyoJeCJgW3c9svPJLdyDAl3Ga8sgKc+ovSUJXhNV7Fun3D 2VgBYSkE9q2K7LyNzTQZ0pkdhGWpapt5BYFb4xVO4Jp4HzMl63fmM8KESe0/bpNt0w wOsWDFtbL2a9RANv/XdGkhxu1qqr5NSPG5QRTMxA= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8Ip9W017311; Fri, 19 May 2017 03:18:51 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:18:50 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQm009185; Fri, 19 May 2017 03:18:46 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 41/41] Documentation: ARM: Document new dependencies for MMC on DRA7 Date: Fri, 19 May 2017 13:45:41 +0530 Message-ID: <20170519081541.26753-42-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MMC on DRA7 SoCs require different IO Delay values to be configured depending on the MMC mode. In order to confgiure these IO Delay values CONFIG_PINCTRL_TI_IODELAY must be enabled. Document this dependency here so that it can be added by anyone using custom .config. Signed-off-by: Kishon Vijay Abraham I --- Documentation/arm/OMAP/README | 4 ++++ 1 file changed, 4 insertions(+) -- 2.11.0 diff --git a/Documentation/arm/OMAP/README b/Documentation/arm/OMAP/README index 75645c45d14a..df018c59e36a 100644 --- a/Documentation/arm/OMAP/README +++ b/Documentation/arm/OMAP/README @@ -5,3 +5,7 @@ KERNEL NEW DEPENDENCIES v4.3+ Update is needed for custom .config files to make sure CONFIG_REGULATOR_PBIAS is enabled for MMC1 to work properly. + +v4.13+ Update is needed for custom .config files to make sure + CONFIG_PINCTRL_TI_IODELAY is enabled for all MMC instances + to work properly in DRA7 based boards.