From patchwork Fri Aug 6 15:21:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 492842 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp423392jap; Fri, 6 Aug 2021 08:21:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwsubefhZvvdHhvtX++3iL7CcPST2Y6e3DsK5DYnFrnU9y6mfLZYzU/Gph+Q8vz1fLOQtZQ X-Received: by 2002:a17:906:1789:: with SMTP id t9mr10215612eje.61.1628263316436; Fri, 06 Aug 2021 08:21:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628263316; cv=none; d=google.com; s=arc-20160816; b=un3rJszD0n428M8QYMHiF/Mr7VwLrDKC/3ABIlsLY1mrDaIqWAO7ri+JjKAVpJ6HP5 EK43Psk/TLWsEYlmClQhTuobxVb0pfF1Ui9BAvVKvqWuum7cGVE3AAIof7h/6cf7D2b1 6iJQ2K2QToPslrOVbIyXuHHYcaMpl8eNKvxbRGbCst3Tmiop/cU4U5rhUQmuINjso2Os BJn0J2g8TxYVpd4fX9o+y7NMlkRl3MMIDRnfvQ57pnFc2dXRHGpFLONCe8QxRDUP4dko zkuk4RSTwEnvYfP4imO38VlwODnFhR0C8yCgIVr9DMcXFVDSmWVpIvyMTTXdX/oor18e vGlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=khXkhKyU/DguseIJ+nWbqK0XZk3XU5Ivr52Y6srFBWM=; b=dd6H79c6h2VrqLodkGrjDeZiF6nQOMti0Re0b41ty/IdBOyRtfeeIt6vGU4Q5WZCBu 3etQmkBTxYSHs1pC19UDcMtyMSjEp/lz4VVgit51j5KT+jF8CMV/m7cyEnwsI8DyXGYz 88MLP/K8DAswl2iFOajEGheERrMFlq2frfukO4ZneZHeqUK0mJK5H2exAWvK3HUVGhA8 akC0S/ppK/Zr05teziAHjvZsz8VisHUP6DhhNYCfmw44rsueplS5AeJBWbPa0v+Bbw1t iblX/+2Zf/5D8PjvlIUHhUi6BKc9UM/HDG4Rsxjo8qxlnDcgEy6Hjgx7jzoPI1K8BdRq CJWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EtIc77Dm; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u15si9530543edt.211.2021.08.06.08.21.56; Fri, 06 Aug 2021 08:21:56 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EtIc77Dm; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244412AbhHFPWL (ORCPT + 7 others); Fri, 6 Aug 2021 11:22:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244335AbhHFPWJ (ORCPT ); Fri, 6 Aug 2021 11:22:09 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBE32C061798 for ; Fri, 6 Aug 2021 08:21:52 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id c24so15321160lfi.11 for ; Fri, 06 Aug 2021 08:21:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=khXkhKyU/DguseIJ+nWbqK0XZk3XU5Ivr52Y6srFBWM=; b=EtIc77DmJbqKnQJIWYRtOQGBtdEOlPiWSm/7xnVVcy7JknD3CdKvslWp3AGkQRBEQx HCSzbTLvC6z2yAA7koctC0UZAMMEWbuF7UlS3LfEYzbOkTryV7Hg7xPWfsbzaiFscbt4 3tdWlq3mFwR/PPerK6eXVadQ5qJ4tsLx8X4yNgaswq90SLM1Cw79uHRwAWqcjhEsWF9J rEf3r9oL3mU4Xg9ZpP7t6ngxrHCzimWAg51h1sHTV+zDoiKZQ0qX+7z4WdhSHVLds9JD +MWN2+JnhCo5q8QaO1ghvhrbg8NThHo4FJdr0puZcXmhzHOx3Ye+KxRFps04xwdYQpoS 03Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=khXkhKyU/DguseIJ+nWbqK0XZk3XU5Ivr52Y6srFBWM=; b=H0c5VfQXUoNQfppSLfn8wpA77VToiVtnPNjRmPSJuI4EcYNjPF+ZMq3d5K2mK+COgC WMGrApmcVw538LRGYBc1RizzwroBeFQVd3i37eKNw9rVJ/lK5jHTv5iTQxgAEjp3BLYo 3qabipzG3KDHeX1sc2CMUzl2O+1Htj0iw/0ua3c79zwfZy8wQVp1QFrhylnJeV/iaihc lYQL87zGivoqZJAOXsIaEr3M0TcGlqAZIhqT0XSMmiS1Y2k9ODdC1OzxWWEaCM8JBIZD yj4Vvpgzpitui24Au5cU1eEXo6BQGMWp03pa94WEy3r6CubMzu2V1Q2f+1g9C0e3fvBe gjTA== X-Gm-Message-State: AOAM533nBTnFQlVuuIJltEYf4FNeevwkbcL6GhbwiXs/lS1NxfPuZvbX sV7twvs3gCGVIY0blAE36JDQhw== X-Received: by 2002:ac2:511a:: with SMTP id q26mr7794829lfb.521.1628263311324; Fri, 06 Aug 2021 08:21:51 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id p8sm738022ljn.108.2021.08.06.08.21.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Aug 2021 08:21:50 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , =?utf-8?q?Pawe=C5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v2 2/8] pinctrl: samsung: Add Exynos850 SoC specific data Date: Fri, 6 Aug 2021 18:21:40 +0300 Message-Id: <20210806152146.16107-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210806152146.16107-1-semen.protsenko@linaro.org> References: <20210806152146.16107-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Samsung Exynos850 SoC specific data to enable pinctrl support for all platforms based on Exynos850. Signed-off-by: Sam Protsenko --- Changes in v2: - Removed .suspend/.resume callbacks, as retention registers are not implemented yet for Exynos850 - Removed .eint_gpio_init for AUD domain, as there are no external interrupts available for that domain .../pinctrl/samsung/pinctrl-exynos-arm64.c | 116 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 29 +++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 148 insertions(+) -- 2.30.2 diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index b6e56422a700..3157bdf0233c 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, }; +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 + */ +static struct samsung_pin_bank_type exynos850_bank_type_off = { + .fld_width = { 4, 1, 4, 4, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +/* + * Bank type for alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4 + */ +static struct samsung_pin_bank_type exynos850_bank_type_alive = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; @@ -422,3 +440,101 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { .ctrl = exynos7_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), }; + +/* pin banks of exynos850 pin-controller 0 (ALIVE) */ +static struct samsung_pin_bank_data exynos850_pin_banks0[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), + EXYNOS9_PIN_BANK_EINTN(3, 0x0A0, "gpq0"), +}; + +/* pin banks of exynos850 pin-controller 1 (CMGP) */ +static struct samsung_pin_bank_data exynos850_pin_banks1[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS9_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS9_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS9_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), + EXYNOS9_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS9_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), + EXYNOS9_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), + EXYNOS9_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), +}; + +/* pin banks of exynos850 pin-controller 2 (AUD) */ +static struct samsung_pin_bank_data exynos850_pin_banks2[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS9_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 3 (HSI) */ +static struct samsung_pin_bank_data exynos850_pin_banks3[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), +}; + +/* pin banks of exynos850 pin-controller 4 (CORE) */ +static struct samsung_pin_bank_data exynos850_pin_banks4[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 5 (PERI) */ +static struct samsung_pin_bank_data exynos850_pin_banks5[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), + EXYNOS9_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), + EXYNOS9_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), + EXYNOS9_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0C), + EXYNOS9_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), + EXYNOS9_PIN_BANK_EINTG(8, 0x0A0, "gpg2", 0x14), + EXYNOS9_PIN_BANK_EINTG(1, 0x0C0, "gpg3", 0x18), + EXYNOS9_PIN_BANK_EINTG(3, 0x0E0, "gpc0", 0x1C), + EXYNOS9_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), +}; + +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos850_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos850_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 2 AUD data */ + .pin_banks = exynos850_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), + }, { + /* pin-controller instance 3 HSI data */ + .pin_banks = exynos850_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 4 CORE data */ + .pin_banks = exynos850_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 5 PERI data */ + .pin_banks = exynos850_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { + .ctrl = exynos850_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index da1ec13697e7..595086f2d5dd 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -108,6 +108,35 @@ .pctl_res_idx = pctl_idx, \ } \ +#define EXYNOS9_PIN_BANK_EINTN(pins, reg, id) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS9_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS9_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 2975b4369f32..2a0fc63516f1 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1264,6 +1264,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos5433_of_data }, { .compatible = "samsung,exynos7-pinctrl", .data = &exynos7_of_data }, + { .compatible = "samsung,exynos850-pinctrl", + .data = &exynos850_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index de44f8ec330b..4c2149e9c544 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -339,6 +339,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; +extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; From patchwork Fri Aug 6 15:21:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 492927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3B17C19F34 for ; Fri, 6 Aug 2021 15:22:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C60FB611F0 for ; Fri, 6 Aug 2021 15:22:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244470AbhHFPWS (ORCPT ); Fri, 6 Aug 2021 11:22:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244406AbhHFPWK (ORCPT ); Fri, 6 Aug 2021 11:22:10 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 538B3C0617A3 for ; Fri, 6 Aug 2021 08:21:54 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id n17so15942786lft.13 for ; Fri, 06 Aug 2021 08:21:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1EL13QEz0jQB5TyPm5EQVY1mhJsKtZswS+e8nPlFSmk=; b=xIdVeClSm5h+yaEEHwHmI3GqBB+wqqezAfScV34d1XkTvLZRrFAKkQkVA7iYInNuyd 2uzs5o9wpyr4iuAX/aGNCTrc2UoJGgmY/wW0X+BhZltOB/Gw7k7tepcwk5u1zePvAl8r C6drAoqZMKRCRJdt4w614Rj1nI3mhYmV4XdwcINazOpL/cfkqrCs0vlXs/I9e0pxGryC f6+Ly3fv7wL8RwWoHVPFu2bw8vtAjzuUCirYn2OeupRGzFQW7JbMVIxF43GFjkWx8eUP Y4KNHl1+F01Yjqbj9O1ctIgrWG1RYpXEQUIaQG0NWLviKTXxXD/YMypIEj8024r9Go2U AzcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1EL13QEz0jQB5TyPm5EQVY1mhJsKtZswS+e8nPlFSmk=; b=fFzx0tmJ7KIMaWdiqP+uI9Tgqdv66LJb6UFNVV8WCGDS4RySfNSSPbdl40EyA9HqE/ tsCgjVw15tgICfteJN0aHQ8Lf9MSGs5/ZbT2Byz2p7adMPtGs7Ctx68C5XAeWdyz7utJ kQI5gfv9KwDU3YJP25FB4tjoUoxrVg1eVtHTDBwago52LJQe25lehWoyEjP41G/CXu9O l+uigVtkxy8E1U3F8Dj0jHYaFzC8sgmqXsSGtlFxR3rLM8hJUxtYvyx7ecxiMGmpLOSs D9P7cJZNmm0oUu6FV5eQBSiFDGC6pTOT/P87wJDQXg+jZfW6p19hDu7prtnsF/bbr0L6 mQBQ== X-Gm-Message-State: AOAM532ntrkISSUw8anF1K9sHlqlz+UygCUnFMY/BYgVv9Va6YyXYgYG DzKX6Oze3H8+o+L/JS6ICDSGFg== X-Google-Smtp-Source: ABdhPJzrtuIMNwEbAEfRv2gXt1rLQY8sTcJq6ivzuavxVikoja9ulbZlZN0f+WV/0monIlJmcioKvg== X-Received: by 2002:a19:6541:: with SMTP id c1mr7959645lfj.423.1628263312699; Fri, 06 Aug 2021 08:21:52 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id i8sm861500lfu.55.2021.08.06.08.21.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Aug 2021 08:21:52 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , =?utf-8?q?Pawe=C5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v2 3/8] dt-bindings: serial: samsung: Add Exynos850 doc Date: Fri, 6 Aug 2021 18:21:41 +0300 Message-Id: <20210806152146.16107-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210806152146.16107-1-semen.protsenko@linaro.org> References: <20210806152146.16107-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatible string for Exynos850 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sam Protsenko --- Changes in v2: - None Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index f064e5b76cf1..2940afb874b3 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -26,6 +26,7 @@ properties: - samsung,s3c6400-uart - samsung,s5pv210-uart - samsung,exynos4210-uart + - samsung,exynos850-uart reg: maxItems: 1 From patchwork Fri Aug 6 15:21:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 492843 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp423497jap; Fri, 6 Aug 2021 08:22:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw11fbMD+n8ENgiCvilO31PaRniMhTXAYl/7JQKIWNg3HqSsjB3UrFC9VlSTsqbyQQr3jP8 X-Received: by 2002:a05:6402:60b:: with SMTP id n11mr14151111edv.235.1628263322614; Fri, 06 Aug 2021 08:22:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628263322; cv=none; d=google.com; s=arc-20160816; b=Os2U0Q7hCjfwT82VSOPolEEJlEw5Um8QFE5iFyqmLUTeYsZ7bR6akvAySRM2oGOHRV +Ol/8OTl36i+kd1KQB9Y5dZaNBDPBV+d/44aGtSbXzduB2spohP7T2/4HEXG6rllsgbf rMmyBhfPTsqWtBopxbiOd5z8VTUgWlUO7fpKpgkdhOr71Y3vsFkk2eDQZ05QVgR06P2Y ZegTMx6KKW+d2aEB73ZqHArEoqfGQ05rxGLIXOPK6v0/kW40M21RRXnowGXIruxE7Pna RGi3LcDnAqYoYMg9b+gtJgQHp2025PzjaY7uow5WpJufdw5B+XDPDagqFJo19VvxiRhg G9/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7149QsY3bxKHTBqGFladXmfU1OHnqAYwWvtju/kpgDw=; b=AmQSqIcxQcsXHRPwrrdebHnwfh8kr+htnmzlXIcUTT6j8pxL95fk5H0PoxSh75U6Y7 vCWxl3bV2pnf+ysThcKprRx1CW9xNlO79SLbF0QuQO6fCVqrZTlpjBgc665/sIZ+qlmk os0E4qqZC4I7EcWBdM63bFFAsLNrms6iqbb2I+LeZ3orMdb8gQO80Ac1P7Vz9WXtgFwV T4rI70FKY9f3w3w2zfS01I68u1J8OzYpJWEl8ICmXIRRfFJ7mTRkTihF6Mi2LoKsKirn zFgSL8Y5e3EjeZg3sUqyo37X1TT5qBLY1jvh/RtEdQqLBh+/pPJgaiXumX8JViAnObOh csAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mU3tb0VO; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u15si9530543edt.211.2021.08.06.08.22.02; Fri, 06 Aug 2021 08:22:02 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mU3tb0VO; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244546AbhHFPWR (ORCPT + 7 others); Fri, 6 Aug 2021 11:22:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244438AbhHFPWM (ORCPT ); Fri, 6 Aug 2021 11:22:12 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0236BC061798 for ; Fri, 6 Aug 2021 08:21:56 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id o10so12458658ljp.0 for ; Fri, 06 Aug 2021 08:21:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7149QsY3bxKHTBqGFladXmfU1OHnqAYwWvtju/kpgDw=; b=mU3tb0VOjIyfm2Q/1wxVB5IQeJY6SOfiPtxtSTAQSM7URQzOPL3Aj6JlwK9ogcH3sU SMRfbF3EFe3/V4/9h71BBGirdS9wb8TFJYrsXsbbkuV8Uiol9nOthlQtIBB3C+u0xHri 2Z917j9Wby2pjv5vyCqcjnIkOzxPZDgdZpHMDnwUTRYVWg8ENCrBT2mnatKNXyLzDTIs MTWCN8MC66Q6+dNxDk4R74/+PBJttkSfuGBh52UEQgGHiIgd+2GsCAO/TZjeJ9sXrw5w 0FBuR3pF8HVMuy85s7WKXXTLaKqIrxc9JsVbxi4yBObBekrmgOHh6gv0vNu76QiLGXOp A/VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7149QsY3bxKHTBqGFladXmfU1OHnqAYwWvtju/kpgDw=; b=YO8rjMGo1wxrROBUXsf2fnKK39KbAYqZRARiOFTAxJIbsSJh8Wof/TW5/qHBCJKXST MMb01BJ60FXJIH5zaIIn+rQFvR5XAzwH6EyPxCkHsJOm4e67aNLJAuKC7HzudrVhtLWH b5AOCMUtdflglKaNebzWnvF66RVoxtlyw++1gW8CBjH4HLfRZN+eZKIGkrxQFjm0cHZP sZg1uovdh+VAd35y6aD45MGWeUcw5OXvqvNv3lwBtasbJ064x8ob6x57d8UGwuTFrw+S 8aymYz4YisC8OcUJIMJLZwzRYajJntyl7Ag3dFwaa+1jd1wOnkXe68JPaqQShD6Jywhg taSA== X-Gm-Message-State: AOAM532hpB5k/kmIauW/6R5gxa3Zt1UbBvSjAoQZKpnsKjrnJjrg7nhm OmfAficPrCLuo3+0av079aNcJw== X-Received: by 2002:a2e:a887:: with SMTP id m7mr7083249ljq.236.1628263314373; Fri, 06 Aug 2021 08:21:54 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id u18sm87339ljj.2.2021.08.06.08.21.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Aug 2021 08:21:53 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , =?utf-8?q?Pawe=C5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v2 4/8] tty: serial: samsung: Init USI to keep clocks running Date: Fri, 6 Aug 2021 18:21:42 +0300 Message-Id: <20210806152146.16107-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210806152146.16107-1-semen.protsenko@linaro.org> References: <20210806152146.16107-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org UART block is a part of USI (Universal Serial Interface) IP-core in Samsung SoCs since Exynos9810 (e.g. in Exynos850). USI allows one to enable one of three types of serial interface: UART, SPI or I2C. That's possible because USI shares almost all internal circuits within each protocol. USI also provides some additional registers so it's possible to configure it. One USI register called USI_OPTION has reset value of 0x0. Because of this the clock gating behavior is controlled by hardware (HWACG = Hardware Auto Clock Gating), which simply means the serial won't work after reset as is. In order to make it work, USI_OPTION[2:1] bits must be set to 0b01, so that HWACG is controlled manually (by software). Bits meaning: - CLKREQ_ON = 1: clock is continuously provided to IP - CLKSTOP_ON = 0: drive IP_CLKREQ to High (needs to be set along with CLKREQ_ON = 1) USI is not present on older chips, like s3c2410, s3c2412, s3c2440, s3c6400, s5pv210, exynos5433, exynos4210. So the new boolean field '.has_usi' was added to struct s3c24xx_uart_info. USI registers will be only actually accessed when '.has_usi' field is set to "1". This feature is needed for further serial enablement on Exynos850, but some other new Exynos chips (like Exynos9810) may benefit from this feature as well. Signed-off-by: Sam Protsenko --- Changes in v2: - Non-intrusive modification of USI registers - Improved comments - Rearranged USI register definitions to conform with existing style drivers/tty/serial/samsung_tty.c | 32 +++++++++++++++++++++++++++++++- include/linux/serial_s3c.h | 9 +++++++++ 2 files changed, 40 insertions(+), 1 deletion(-) -- 2.30.2 Reviewed-by: Krzysztof Kozlowski diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 9fbc61151c2e..b8034c1168e0 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -65,6 +65,7 @@ enum s3c24xx_port_type { struct s3c24xx_uart_info { char *name; enum s3c24xx_port_type type; + unsigned int has_usi; unsigned int port_type; unsigned int fifosize; unsigned long rx_fifomask; @@ -1352,6 +1353,28 @@ static int apple_s5l_serial_startup(struct uart_port *port) return ret; } +static void exynos_usi_init(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + struct s3c24xx_uart_info *info = ourport->info; + unsigned int val; + + if (!info->has_usi) + return; + + /* Clear the software reset of USI block (it's set at startup) */ + val = rd_regl(port, USI_CON); + val &= ~USI_CON_RESET_MASK; + wr_regl(port, USI_CON, val); + udelay(1); + + /* Continuously provide the clock to USI IP w/o gating (for Rx mode) */ + val = rd_regl(port, USI_OPTION); + val &= ~USI_OPTION_HWACG_MASK; + val |= USI_OPTION_HWACG_CLKREQ_ON; + wr_regl(port, USI_OPTION, val); +} + /* power power management control */ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, @@ -1379,6 +1402,7 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, if (!IS_ERR(ourport->baudclk)) clk_prepare_enable(ourport->baudclk); + exynos_usi_init(port); break; default: dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); @@ -2102,6 +2126,8 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, if (ret) pr_warn("uart: failed to enable baudclk\n"); + exynos_usi_init(port); + /* Keep all interrupts masked and cleared */ switch (ourport->info->type) { case TYPE_S3C6400: @@ -2750,10 +2776,11 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { #endif #if defined(CONFIG_ARCH_EXYNOS) -#define EXYNOS_COMMON_SERIAL_DRV_DATA \ +#define EXYNOS_COMMON_SERIAL_DRV_DATA_USI(_has_usi) \ .info = &(struct s3c24xx_uart_info) { \ .name = "Samsung Exynos UART", \ .type = TYPE_S3C6400, \ + .has_usi = _has_usi, \ .port_type = PORT_S3C6400, \ .has_divslot = 1, \ .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ @@ -2773,6 +2800,9 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { .has_fracval = 1, \ } \ +#define EXYNOS_COMMON_SERIAL_DRV_DATA \ + EXYNOS_COMMON_SERIAL_DRV_DATA_USI(0) + static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { EXYNOS_COMMON_SERIAL_DRV_DATA, .fifosize = { 256, 64, 16, 16 }, diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h index f6c3323fc4c5..cf0de4a86640 100644 --- a/include/linux/serial_s3c.h +++ b/include/linux/serial_s3c.h @@ -27,6 +27,15 @@ #define S3C2410_UERSTAT (0x14) #define S3C2410_UFSTAT (0x18) #define S3C2410_UMSTAT (0x1C) +#define USI_CON (0xC4) +#define USI_OPTION (0xC8) + +#define USI_CON_RESET (1<<0) +#define USI_CON_RESET_MASK (1<<0) + +#define USI_OPTION_HWACG_CLKREQ_ON (1<<1) +#define USI_OPTION_HWACG_CLKSTOP_ON (1<<2) +#define USI_OPTION_HWACG_MASK (3<<1) #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) From patchwork Fri Aug 6 15:21:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 492926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68944C432BE for ; Fri, 6 Aug 2021 15:22:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4EDD761206 for ; Fri, 6 Aug 2021 15:22:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244704AbhHFPWx (ORCPT ); Fri, 6 Aug 2021 11:22:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244548AbhHFPWR (ORCPT ); Fri, 6 Aug 2021 11:22:17 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F7FDC061385 for ; Fri, 6 Aug 2021 08:21:59 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id x8so18663528lfe.3 for ; Fri, 06 Aug 2021 08:21:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bjAidQVjPnsdyg/2uwjvZwZUIqwFqOyk06P5z8n6Pdk=; b=w3bhoI9TaLN9+BaimUNJdAjGiFas7439LuvvPO8mNbDlicCeKyi4nWUx/VModoGVzN 61TIDRksKmXIdADyvk9S+YFXan+9/kjvEYf3AT1cHXjR1QwcLNnZIfdrk2gvkAntlfV0 K6VwycLQ+HSAwMMNXhyCL8a/tsA/9BBPnetOkQUJ3KcTOOPcAaVz5dizGOtSvHyK8Djh qHmWrZ6bEOKg7WWM+e+yCt5InvbFG4U0tOMwUbx1BAAPc2SrzbF24cASRp1V0p0VxckO YMqy9bkGMPPR2828C4oShzaEi9rck++WFZT/2nXpJ2Ou+jXfmrn1XYbpwTEtaHD0ulfS vivA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bjAidQVjPnsdyg/2uwjvZwZUIqwFqOyk06P5z8n6Pdk=; b=LA9j/FZNH7Nsyly14BH7+S7DUr+6VF9DekH6LiIEKLZDlEqAs3DBCKezNp9uUQ+GrU l4/muToP8cfoTINSCquNWHwwy9pC+a82+byd2ZeHI/Wy96e2oN9kldCYYfSyBMMxU3+t fDldy9Brs/p0hX6LZlMJoLQ15mBZbLvbPMtyeGH1BBPCHZwIJVVM96seHcz/ppGC/13e l5CncIe+JFfFteGgGjKL4e1+A/C/GTlS8Wt63qyP3HmFUmEWJvxdSOwz44+y4OFl4XXH kAibfWveEVCdhlwY/DF9D91J3gpRScLWW5EpyepjpxniNc143atRTq5TBKCybMR1Vk1L kN3w== X-Gm-Message-State: AOAM533txGaUB3mjp/JY8RZQRsjUBKKjOPyvrdcyZjiJ6oXJw441csia ZNjPTI3/ex/MTHUckjWWeI2dxQ== X-Google-Smtp-Source: ABdhPJyNqJD0uINMyeXLyFGbH4gPkm7zTB1xHT/l74cQsoPIXDTz+BX+WJCAjByqRpZnZpbWyOCjsw== X-Received: by 2002:ac2:5087:: with SMTP id f7mr7702795lfm.43.1628263317657; Fri, 06 Aug 2021 08:21:57 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id j18sm861634lfg.65.2021.08.06.08.21.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Aug 2021 08:21:57 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , =?utf-8?q?Pawe=C5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v2 6/8] tty: serial: samsung: Add Exynos850 SoC data Date: Fri, 6 Aug 2021 18:21:44 +0300 Message-Id: <20210806152146.16107-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210806152146.16107-1-semen.protsenko@linaro.org> References: <20210806152146.16107-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add serial driver data for Exynos850 SoC. This driver data is basically reusing EXYNOS_COMMON_SERIAL_DRV_DATA, which is common for all Exynos chips, but also enables USI init, which was added in previous commit: "tty: serial: samsung: Init USI to keep clocks running". Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- Changes in v2: - Fixed default fifo sizes drivers/tty/serial/samsung_tty.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 130bdc978e93..a069e7bb858f 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2813,11 +2813,19 @@ static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { .fifosize = { 64, 256, 16, 256 }, }; +static struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { + EXYNOS_COMMON_SERIAL_DRV_DATA_USI(1), + .fifosize = { 256, 64, 64, 64 }, +}; + #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) +#define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos850_serial_drv_data) + #else #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) +#define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) #endif #ifdef CONFIG_ARCH_APPLE @@ -2873,6 +2881,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { }, { .name = "s5l-uart", .driver_data = S5L_SERIAL_DRV_DATA, + }, { + .name = "exynos850-uart", + .driver_data = EXYNOS850_SERIAL_DRV_DATA, }, { }, }; @@ -2896,6 +2907,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { .data = (void *)EXYNOS5433_SERIAL_DRV_DATA }, { .compatible = "apple,s5l-uart", .data = (void *)S5L_SERIAL_DRV_DATA }, + { .compatible = "samsung,exynos850-uart", + .data = (void *)EXYNOS850_SERIAL_DRV_DATA }, {}, }; MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); From patchwork Fri Aug 6 15:21:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 492848 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp424200jap; Fri, 6 Aug 2021 08:22:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx/UlWiQvxLtU6Mg+BjyXV2zZCYhiKYfvxqHtPOp8FCze5oyjzMIZam/MJhJ1sqA0Jt3Cid X-Received: by 2002:a05:6402:1458:: with SMTP id d24mr13848663edx.281.1628263375803; Fri, 06 Aug 2021 08:22:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628263375; cv=none; d=google.com; s=arc-20160816; b=G/g1VqqxdZkV8dWXwVSPSOIRDrqtgcqoCSs+yLIuXbA/xkHNziA47BUq4Mibjs3xZ5 1CaACn4bNoLP8AVzb1g3aZMUU/rthymDt9zLLtPCZokF0epE/8+yZLVZ+tA2CyJITfzo Upq7yqqYsdgTib5azBS+MeWbgml7sl/C+REWLC52cqoVfYvuLfqw0NcTkfHkuVbI/fzi wNZfzZZFdRuntdYsYBj45TWALgEfiB0KpvK7iO5XIeFYWqtsmUO9hpG15CU8GZ1fC271 IkRMYcHSO090kFfH4GybIrqb9WYXNuSClvGsWdCXLFoTPdOsA5DyjPsJLiE094516CmU /aAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DEw4AnrBpMSOvBaDKqc62OLDqJ/rOmIVhI1hfmr2Aao=; b=zhDD4CDXRXfOoGeghdmh7pvgFR54WhyV4g3yoBGIYikNVkTsL20M9xUedZ1S81HT4L 0x7F8ba744YZfKnX7nhD5jbnDrinKDqRdHfg+GDBmeMEpyvQTxIUDu70W2nxBrLx/O3R BMDNl03Mxwkyg9cwI7NFwcbsTUOFfRXBq6cnDRHCYBxAuxE7OZdpjI0X5Fc8DLqpioDQ G2qm5yS+UjhJeVIVy6Gi9dB3yUF2eexuIUsLbVU633Hb32fdmAZGC8C87GwbU80BK/I8 BPciUduNJP+jCClVKMZLJhf3scDr9licvOfP9r13LoT4E12toTMJYYO82MbsHzuUNBpQ Ze8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DdGJv9h5; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w20si9145184edr.65.2021.08.06.08.22.55; Fri, 06 Aug 2021 08:22:55 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DdGJv9h5; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244643AbhHFPXJ (ORCPT + 7 others); Fri, 6 Aug 2021 11:23:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244675AbhHFPWh (ORCPT ); Fri, 6 Aug 2021 11:22:37 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5F2CC061798 for ; Fri, 6 Aug 2021 08:22:02 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id m18so1128299ljo.1 for ; Fri, 06 Aug 2021 08:22:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DEw4AnrBpMSOvBaDKqc62OLDqJ/rOmIVhI1hfmr2Aao=; b=DdGJv9h5+/Fz1btG+8Tn2oYJmxv+VBcCw8RyVnJCy0DBn9S9ObdI7iWxteEcL+oENJ iz5tqWySXbrTpuU/ySw27Wcd34Yf9XFqgK00xJ8AUJ259zorPo4OZQMmfvGqQtWNWZn5 69WUGb7KUSBvoSYV0xkjW0ZNeznAVr8/YStaUtNHWtEKjnXvm1xjdDNJWkq6MepgGLvn ozvhnfy+Pe1PvtOa3JDJy4MzjVP1xv7ZdmuzOhTn5dUCiaT4OF1DFWuTheisl7P+VYOY Q7y1lVVGd66udlPXs0QPFXBB6YQ88MmIIjYdJ310ZpJNfQHu0nr79XuGv0O4WgzaT9CP ODKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DEw4AnrBpMSOvBaDKqc62OLDqJ/rOmIVhI1hfmr2Aao=; b=C9YXPIg0/GmHxymoaeXjuhSKeZMU0iI/umofNQabbB61CCQc/PPOduC52IMis5zkk2 ZZ/04Svpisah+7yMMMXKes2gvbc2suDQ3Nk55QJp4ofZhGPBEzpDtdS+wgfjFO3KiDNY Lu50UjsDBsTyjfSvYwSQw4B1ojtHECRqjkFG5vdx7FiiDX0ZU2YjXWgiHqlit7S+Imc8 aoy9HreF8CaiMLMvvV1TIgUVKXl0rBHg5h0yWH6ChuN44uhLvC66GBBvZGyrLjiXhugY +rWC/14zBUnSYg4WVf0ZFXxPZxY9K22t3ee5WJPEBO33PmPrjVyGsx0CdWN+UGeybdKy ZCUw== X-Gm-Message-State: AOAM532kLURn7RxYJ9qoHZwWEE7LZCg4veBy6pGUZOaCPX2MrkfXz527 3LOtkbT6zry6g+O/s48cWJTRrA== X-Received: by 2002:a2e:9b03:: with SMTP id u3mr2804254lji.401.1628263321057; Fri, 06 Aug 2021 08:22:01 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id t30sm713170ljo.124.2021.08.06.08.22.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Aug 2021 08:22:00 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , =?utf-8?q?Pawe=C5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v2 8/8] arm64: dts: exynos: Add Exynos850 SoC support Date: Fri, 6 Aug 2021 18:21:46 +0300 Message-Id: <20210806152146.16107-9-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210806152146.16107-1-semen.protsenko@linaro.org> References: <20210806152146.16107-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Samsung Exynos850 is ARMv8-based mobile-oriented SoC. This patch adds minimal SoC support by including next Device Tree nodes: 1. Octa cores (Cortex-A55), supporting PSCI v1.0 2. ARM architecture timer (armv8-timer) 3. Interrupt controller (GIC-400) 4. Clock controller node (using stub driver for now) 5. Pinctrl nodes for GPIO 6. Serial node Signed-off-by: Sam Protsenko --- Changes in v2: * Commit message: - Documented added dts features instead of CPU features * exynos850-usi.dtsi: - Removed, moved everything to exynos850.dtsi * exynos850.dtsi: - Root node: - Added comment about engineering name (Exynos3830) - Renamed pinctrl nodes, adding domain names - Used hard coded IRQ numbers instead of named constants everywhere - Added soc node, moved next nodes there: gic, clock, pinctrls and serial - Used address-cells=1 for soc node and removed unneeded 0x0 from reg properties - Moved exynos850-pinctrl.dtsi include line to the end of exynos850.dtsi - Coding style fixes - cpus: - Used address-cells=1 for cpus node - Renamed cpu@0001 to cpu@1, and so on - Left only "arm,cortex-a55" for cpus compatible - Renamed reg = <0x0001> to <0x1> for cpus - armv8 timer: - Add comment about missing HV timer IRQ to armv8 timer node - Removed not existing properties from armv8 timer node - Fixed cpu number in CPU_MASK() - Removed obsolete clock-frequency property - GIC: - Fixed GIC type to be GIC-400 - Fixed size of GIC's 2nd region to be 0x2000 - serial node: - Hard coded clock number for serial_0 for now; will replace with named const once proper clock driver is implemented - Removed gate_uart_clk0 clock from serial_0, as that clock is not supported in serial driver anyway (yet) - clock node: - Fixed clock controller node name (@0x12.. -> @12..) * exynos850-pinctrl.dtsi: - Referenced pinctrl nodes instead of defining those again in root node - Fixed interrupt-cells (3 -> 2) - Fixed USI related comments for pin config nodes - Removed decon_f_te_* and fm_lna_en nodes (won't be used) - Reordered pin config nodes by pin numbers - Improved all comments - Used existing named constants for pin-function and pin-pud - Fixed node names (used hyphens instead of underscore) - Fixed warnings found in W=1 build .../boot/dts/exynos/exynos850-pinctrl.dtsi | 748 ++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos850.dtsi | 256 ++++++ 2 files changed, 1004 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi -- 2.30.2 diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi new file mode 100644 index 000000000000..ba5d5f33e2f6 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source + * + * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include +#include + +&pinctrl_alive { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa4: gpa4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + gpq0: gpq0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ + i2c5_bus: i2c5-bus { + samsung,pins = "gpa3-5", "gpa3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* I2C6 (also called MOTOR_I2C in TRM) */ + i2c6_bus: i2c6-bus { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: UART */ + uart0_bus: uart0-bus { + samsung,pins = "gpq0-0", "gpq0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_cmgp { + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm5: gpm5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + /* USI_CMGP0: HSI2C function */ + hsi2c3_bus: hsi2c3-bus { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */ + uart1_bus_single: uart1-bus { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */ + uart1_bus_dual: uart1-bus-dual { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: SPI function */ + spi1_bus: spi1-bus { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi1_cs: spi1-cs { + samsung,pins = "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi1_cs_func: spi1-cs-func { + samsung,pins = "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI_CMGP1: HSI2C function */ + hsi2c4_bus: hsi2c4-bus { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */ + uart2_bus_single: uart2-bus { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */ + uart2_bus_dual: uart2-bus-dual { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: SPI function */ + spi2_bus: spi2-bus { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi2_cs: spi2-cs { + samsung,pins = "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi2_cs_func: spi2-cs-func { + samsung,pins = "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_aud { + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + aud_codec_mclk: aud-codec-mclk { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_mclk_idle: aud-codec-mclk-idle { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_bus: aud-i2s0-bus { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_idle: aud-i2s0-idle { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_bus: aud-i2s1-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_idle: aud-i2s1-idle { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_bus: aud-fm-bus { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_idle: aud-fm-idle { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_hsi { + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + sd2_clk_fast_slew_rate_1_5x: sd2-clk-fast-slew-rate-1-5x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <1>; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_2_5x: sd2-clk-fast-slew-rate-2-5x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <4>; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <5>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpf2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpf2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_pins_as_pdn: sd2-pins-as-pdn { + samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_core { + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <1>; + }; + + sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpf0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_nreset: sd0-nreset { + samsung,pins = "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpf1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; +}; + +&pinctrl_peri { + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp0: gpp0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp1: gpp1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* USI: HSI2C0 */ + hsi2c0_bus: hsi2c0-bus { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: HSI2C1 */ + hsi2c1_bus: hsi2c1-bus { + samsung,pins = "gpc1-2", "gpc1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: HSI2C2 */ + hsi2c2_bus: hsi2c2-bus { + samsung,pins = "gpc1-4", "gpc1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: SPI */ + spi0_bus: spi0-bus { + samsung,pins = "gpp2-0", "gpp2-2", "gpp2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi0_cs: spi0-cs { + samsung,pins = "gpp2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi0_cs_func: spi0-cs-func { + samsung,pins = "gpp2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpp0-0", "gpp0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpp0-2", "gpp0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpp0-4", "gpp0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpp1-0", "gpp1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + sensor_mclk0_in: sensor-mclk0-in { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk0_out: sensor-mclk0-out { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk0_fn: sensor-mclk0-fn { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_in: sensor-mclk1-in { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_out: sensor-mclk1-out { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_fn: sensor-mclk1-fn { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_in: sensor-mclk2-in { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_out: sensor-mclk2-out { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_fn: sensor-mclk2-fn { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + xclkout: xclkout { + samsung,pins = "gpq0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi new file mode 100644 index 000000000000..9d8c1402685e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos850 SoC device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung Exynos850 SoC device nodes are listed in this file. + * Exynos based board files can include this file and provide + * values for board specific bindings. + */ + +#include + +/ { + /* Also known under engineering name Exynos3830 */ + compatible = "samsung,exynos850"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_cmgp; + pinctrl2 = &pinctrl_aud; + pinctrl3 = &pinctrl_hsi; + pinctrl4 = &pinctrl_core; + pinctrl5 = &pinctrl_peri; + serial0 = &serial_0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x1>; + enable-method = "psci"; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x2>; + enable-method = "psci"; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x3>; + enable-method = "psci"; + }; + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + }; + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x101>; + enable-method = "psci"; + }; + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x102>; + enable-method = "psci"; + }; + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x103>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts = , + , + , + ; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + gic: interrupt-controller@12a01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0x12a01000 0x1000>, + <0x12a02000 0x2000>, + <0x12a04000 0x2000>, + <0x12a06000 0x2000>; + interrupt-controller; + interrupts = ; + }; + + clock: clock-controller@120e0000 { + compatible = "samsung,exynos850-clock"; + reg = <0x120e0000 0x8000>; + #clock-cells = <1>; + }; + + pinctrl_alive: pinctrl@11850000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11850000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_cmgp: pinctrl@11c30000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11c30000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_aud: pinctrl@14a60000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x14a60000 0x1000>; + }; + + pinctrl_hsi: pinctrl@13430000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x13430000 0x1000>; + interrupts = ; + }; + + pinctrl_core: pinctrl@12070000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x12070000 0x1000>; + interrupts = ; + }; + + pinctrl_peri: pinctrl@139b0000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x139b0000 0x1000>; + interrupts = ; + }; + + /* USI: UART */ + serial_0: uart@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x13820000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + clocks = <&clock 2>; + clock-names = "uart"; + status = "disabled"; + }; + }; +}; + +#include "exynos850-pinctrl.dtsi"