From patchwork Mon May 22 04:52:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 100245 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp83853qge; Sun, 21 May 2017 21:53:23 -0700 (PDT) X-Received: by 10.84.229.15 with SMTP id b15mr26715350plk.14.1495428803706; Sun, 21 May 2017 21:53:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495428803; cv=none; d=google.com; s=arc-20160816; b=u1TVQa4b/vRmceweSFp8d1liif/rFOvtLKBxQ16dadi/3kgbWWCMgl5z1NGAKwaWEQ jANfxVzdlR82e0pnBJ2tVlY/Hp+fQuRcYNm5xJNrpcT5PClTvLFEGXwZflIPi+CF3dRT 7G/EvkTD4FdrxgpjlS9lYCqk3pB7zgKSHto7hh14cxDgN7LOfipZZkhUc40KWMY4QVng VhqFVIpBNuwQhR6oiA2rVB0qokFJX55gHMo6NUvlFkyGumvDka1n8MlJXW9el0I7hBmB mJZj2UfP/4A3qEoGnpe2+doCN4NGW25XrKHSByMVVjWBPi6npZwS4U8vK83lK9Bp9duZ CP2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=1bKAjNSbz6Dyn1KUAXAWFGzg+2kmJCsl3yUZfa6t70w=; b=MPLllI1rQoqyzOkHKGU26eXGw0+3vddbWm8jiWI/dw541mLJUC9S8AwVlZjgdZhB8X k/1ZtFC/OdDEoOExbs+Tr9YiXLsgUdRwNWflKywxtPbqXGgv1EtF+btxpluG3epcV1S4 7JeB2mdquwsYqf4IxhT2Bg9x7wVqLr7uRgzPZ5Kiu06ymG24XQzJGG6kWaZ1aOIar00W wn2W08fUgWCaXmaOCZC2cut+JT/7QWZa1g8ZzqRNwizXeyoXuGWRcX61lves0Tywaisw Jx5f3ZbQV7FRpLYrVvsXFkZc8G4LhqKgKDJE8VzPbDn3FWRoH1HYxMaZhJOysBxl7/2N OjIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[106.186.117.108]) by smtp.gmail.com with ESMTPSA id s68sm28837594pgc.5.2017.05.21.21.53.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 21 May 2017 21:53:09 -0700 (PDT) From: Leo Yan To: Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Zhangfei Gao , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Guodong Xu , Haojian Zhuang Cc: Leo Yan Subject: [PATCH v3 1/2] clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVER Date: Mon, 22 May 2017 12:52:27 +0800 Message-Id: <1495428748-11153-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495428748-11153-1-git-send-email-leo.yan@linaro.org> References: <1495428748-11153-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The timer will register into system at very early phase at kernel boot; if timer needs to use clock, the clock should be get ready in function of_clk_init() so later the timer driver probe can retrieve clock successfully. This is finished in below flow on arm64: start_kernel() `-> time_init() `-> of_clk_init(NULL) => register timer's clock `-> clocksource_probe() => register timer On Hi3660 the sp804 timer uses clock "osc32k", this clock is registered as platform driver rather than CLK_OF_DECLARE_DRIVER method. As result, sp804 timer probe returns failure due if cannot bind clock properly. To fix the failure, this patch is to split crgctrl clocks into two subsets. One part is for fixed_rate_clks which includes pre-defined fixed rate clocks, and "osc32k" clock is in this category; So we change their registration to CLK_OF_DECLARE_DRIVER method, as result the clocks can be registered ahead with function of_clk_init() and timer driver can bind timer clock successfully; the rest of the crgctrl clocks are still registered by the probe of the platform driver. This patch also adds checking for all crgctrl clocks registration and print out log if any clock has failure. Signed-off-by: Leo Yan --- drivers/clk/hisilicon/clk-hi3660.c | 48 ++++++++++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 10 deletions(-) -- 1.9.1 diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index fd5ce7f..271008b 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -452,6 +452,8 @@ CLK_SET_RATE_PARENT, 0x90, 0, 0, }, }; +static struct hisi_clock_data *clk_crgctrl_data; + static void hi3660_clk_iomcu_init(struct device_node *np) { struct hisi_clock_data *clk_data; @@ -514,38 +516,64 @@ static void hi3660_clk_sctrl_init(struct device_node *np) clk_data); } -static void hi3660_clk_crgctrl_init(struct device_node *np) +static void hi3660_clk_crgctrl_early_init(struct device_node *np) { - struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) + ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) + ARRAY_SIZE(hi3660_crgctrl_gate_clks) + ARRAY_SIZE(hi3660_crgctrl_mux_clks) + ARRAY_SIZE(hi3660_crg_fixed_factor_clks) + ARRAY_SIZE(hi3660_crgctrl_divider_clks); + int i; - clk_data = hisi_clk_init(np, nr); - if (!clk_data) + clk_crgctrl_data = hisi_clk_init(np, nr); + if (!clk_crgctrl_data) return; + for (i = 0; i < nr; i++) + clk_crgctrl_data->clk_data.clks[i] = ERR_PTR(-EPROBE_DEFER); + hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks, ARRAY_SIZE(hi3660_fixed_rate_clks), - clk_data); + clk_crgctrl_data); +} +CLK_OF_DECLARE_DRIVER(hi3660_clk_crgctrl, "hisilicon,hi3660-crgctrl", + hi3660_clk_crgctrl_early_init); + +static void hi3660_clk_crgctrl_init(struct device_node *np) +{ + struct clk **clks; + int i; + + if (!clk_crgctrl_data) + hi3660_clk_crgctrl_early_init(np); + + /* clk_crgctrl_data initialization failed */ + if (!clk_crgctrl_data) + return; + hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks, ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks), - clk_data); + clk_crgctrl_data); hisi_clk_register_gate(hi3660_crgctrl_gate_clks, ARRAY_SIZE(hi3660_crgctrl_gate_clks), - clk_data); + clk_crgctrl_data); hisi_clk_register_mux(hi3660_crgctrl_mux_clks, ARRAY_SIZE(hi3660_crgctrl_mux_clks), - clk_data); + clk_crgctrl_data); hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks, ARRAY_SIZE(hi3660_crg_fixed_factor_clks), - clk_data); + clk_crgctrl_data); hisi_clk_register_divider(hi3660_crgctrl_divider_clks, ARRAY_SIZE(hi3660_crgctrl_divider_clks), - clk_data); + clk_crgctrl_data); + + clks = clk_crgctrl_data->clk_data.clks; + for (i = 0; i < clk_crgctrl_data->clk_data.clk_num; i++) { + if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER) + pr_err("Failed to register crgctrl clock[%d] err=%ld\n", + i, PTR_ERR(clks[i])); + } } static const struct of_device_id hi3660_clk_match_table[] = { From patchwork Mon May 22 04:52:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 100246 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp83884qge; Sun, 21 May 2017 21:53:31 -0700 (PDT) X-Received: by 10.84.174.3 with SMTP id q3mr26783079plb.179.1495428811346; Sun, 21 May 2017 21:53:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495428811; cv=none; d=google.com; s=arc-20160816; b=ojvhhGpyEqssyFyC5wZha6dlNCrUGSeE31WlhbXqNqsJ2zmmP9S9TM5KnDl0B63HK6 TbqV5v7eS0iLQBuLiGo/9mpwZEsVWhtE6YYTkBKW/ESfntmEkI5rYOL3WVNV+mn3nkWs HDODhjDdsNgWTFp8GcMhRRUClCNAKPVXr2s7jUS0SgMj7CS5SA1Orpd6+0HhGOZXKBUO VJTt4nBW6Q+p4OYLGKsZKA/JONbd7M05RYLuP5droayiuGhMCxJ0dAz2kT9gRT3BrAWL 4YNoS0Rc8iudhJiSqNy0i5C9KTAHEwej0cgCX7I6VdGS+yOMnYRtl0oGzs0R6JaYGFEu 86mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=wJAzihJNdQtMyT+iTeJQtD3nlj+AP+QoQkcKNRMR0+g=; b=n3IM5bAFwcmSe+RxVunwDthIPjnw3YaF81uKG7K5MX8LRBCVPGjvk9VOWpbR4CqGlf otu+0/h/M/DMejghb/kEOoXm1zI74miEweOReBtMNvF7JOXSofydm0sUoVmZQeLv3yju upL/TUAr2oEoV4UVWYJyTDK2j3UGZoXWNvWe7DWk1AqFf4rNpxRDOKhwBdCM6IVVzmyy u+lTafrOfsCTiiSwnvcOqRmhWCNl3ItdCQrEegYtbnVF7SJ2zLe1wgbpjdAn8IxQmPor SKKg2z1hGL96qc/0HJAgKx2LPfERyRaVheXA6pfqWw6jyTtHaQieJsJYY5+SRLpO+y8E w4Xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[106.186.117.108]) by smtp.gmail.com with ESMTPSA id s68sm28837594pgc.5.2017.05.21.21.53.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 21 May 2017 21:53:16 -0700 (PDT) From: Leo Yan To: Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Zhangfei Gao , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Guodong Xu , Haojian Zhuang Cc: Leo Yan Subject: [PATCH v3 2/2] arm64: dts: add sp804 timer node for Hi3660 Date: Mon, 22 May 2017 12:52:28 +0800 Message-Id: <1495428748-11153-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495428748-11153-1-git-send-email-leo.yan@linaro.org> References: <1495428748-11153-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Hi3660 SoC comes with the sp804 timer in addition to the architecture timers. These ones are shutdown when reaching a deep idle states and a backup timer is needed. The sp804 belongs to another power domain and can fulfill the purpose of replacing temporarily an architecture timer when the CPU is idle. Describe it in the device tree, so it can be enabled at boot time. Suggested-by: Daniel Lezcano Acked-by: Daniel Lezcano Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 138fcba..f75c792 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -173,6 +173,17 @@ #clock-cells = <1>; }; + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = , + ; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + ufs: ufs@ff3b0000 { compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs"; reg = <0x0 0xff3b0000 0x0 0x1000>, /* 0: HCI standard */