From patchwork Tue Aug 17 07:45:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48E19C43214 for ; Tue, 17 Aug 2021 07:46:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3336660F5E for ; Tue, 17 Aug 2021 07:46:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238669AbhHQHqr (ORCPT ); Tue, 17 Aug 2021 03:46:47 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:47498 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S238627AbhHQHqq (ORCPT ); Tue, 17 Aug 2021 03:46:46 -0400 X-UUID: fb60b2d7a8fa4cd9a547ff61193cda31-20210817 X-UUID: fb60b2d7a8fa4cd9a547ff61193cda31-20210817 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 301300522; Tue, 17 Aug 2021 15:46:08 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:07 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [v2, 01/12] dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC Date: Tue, 17 Aug 2021 15:45:46 +0800 Message-ID: <20210817074557.30953-2-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This patch adds the binding documentation for topckgen, apmixedsys, infracfg, and ethernet subsystem clocks. Signed-off-by: Sam Shih --- v2: remove compatiable string 'mt7986-sgmiisys' --- .../devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + .../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + .../devicetree/bindings/arm/mediatek/mediatek,infracfg.txt | 1 + .../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt | 2 ++ .../devicetree/bindings/arm/mediatek/mediatek,topckgen.txt | 1 + 5 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index ea827e8763de..3fa755866528 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -14,6 +14,7 @@ Required Properties: - "mediatek,mt7622-apmixedsys" - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" - "mediatek,mt7629-apmixedsys" + - "mediatek,mt7986-apmixedsys" - "mediatek,mt8135-apmixedsys" - "mediatek,mt8167-apmixedsys", "syscon" - "mediatek,mt8173-apmixedsys" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt index 6b7e8067e7aa..0502db73686b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt @@ -10,6 +10,7 @@ Required Properties: - "mediatek,mt7622-ethsys", "syscon" - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" - "mediatek,mt7629-ethsys", "syscon" + - "mediatek,mt7986-ethsys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index eb3523c7a7be..f66bd720571d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -15,6 +15,7 @@ Required Properties: - "mediatek,mt7622-infracfg", "syscon" - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - "mediatek,mt7629-infracfg", "syscon" + - "mediatek,mt7986-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8167-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt index 30cb645c0e54..29ca7a10b315 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt @@ -8,6 +8,8 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-sgmiisys", "syscon" - "mediatek,mt7629-sgmiisys", "syscon" + - "mediatek,mt7986-sgmiisys_0", "syscon" + - "mediatek,mt7986-sgmiisys_1", "syscon" - #clock-cells: Must be 1 The SGMIISYS controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index 5ce7578cf274..b82422bb717f 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -14,6 +14,7 @@ Required Properties: - "mediatek,mt7622-topckgen" - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" - "mediatek,mt7629-topckgen" + - "mediatek,mt7986-topckgen", "syscon" - "mediatek,mt8135-topckgen" - "mediatek,mt8167-topckgen", "syscon" - "mediatek,mt8173-topckgen" From patchwork Tue Aug 17 07:45:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498212 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63B12C00143 for ; Tue, 17 Aug 2021 07:46:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4FDC560FC3 for ; Tue, 17 Aug 2021 07:46:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238873AbhHQHrA (ORCPT ); Tue, 17 Aug 2021 03:47:00 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:49108 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S238401AbhHQHq5 (ORCPT ); Tue, 17 Aug 2021 03:46:57 -0400 X-UUID: 723d57c8675f4595a3cc522197344b3b-20210817 X-UUID: 723d57c8675f4595a3cc522197344b3b-20210817 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1486542070; Tue, 17 Aug 2021 15:46:19 +0800 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:18 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 17 Aug 2021 15:46:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:18 +0800 From: Sam Shih To: Rob Herring , Sean Wang , "Linus Walleij" , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , "Sam Shih" Subject: [v2, 04/12] pinctrl: mediatek: moore: check if pin_desc is valid before use Date: Tue, 17 Aug 2021 15:45:49 +0800 Message-ID: <20210817074557.30953-5-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Certain SoC are missing the middle part gpios in consecutive pins, it's better to check if mtk_pin_desc is a valid pin for the extensibility Signed-off-by: Sam Shih --- v2: applied the comment suggested by reviewers: - for the pins not ballout, we can fill .name in struct mtk_pin_desc as NULL and return -ENOTSUPP in gpio/pinconf ops. --- drivers/pinctrl/mediatek/pinctrl-moore.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 3a4a23c40a71..ad3b67163973 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -60,6 +60,8 @@ static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev, int pin = grp->pins[i]; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; + if (!desc->name) + return -ENOTSUPP; mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, pin_modes[i]); @@ -76,6 +78,8 @@ static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; + if (!desc->name) + return -ENOTSUPP; return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, hw->soc->gpio_m); @@ -89,6 +93,8 @@ static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; + if (!desc->name) + return -ENOTSUPP; /* hardware would take 0 as input direction */ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input); @@ -103,6 +109,8 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; + if (!desc->name) + return -ENOTSUPP; switch (param) { case PIN_CONFIG_BIAS_DISABLE: @@ -218,6 +226,8 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, int cfg, err = 0; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; + if (!desc->name) + return -ENOTSUPP; for (cfg = 0; cfg < num_configs; cfg++) { param = pinconf_to_config_param(configs[cfg]); @@ -435,6 +445,8 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) int value, err; desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; + if (!desc->name) + return -ENOTSUPP; err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); if (err) @@ -449,6 +461,10 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; + if (!desc->name) { + dev_err(hw->dev, "Failed to set gpio %d\n", gpio); + return; + } mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); } @@ -490,6 +506,8 @@ static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset, u32 debounce; desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; + if (!desc->name) + return -ENOTSUPP; if (!hw->eint || pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE || From patchwork Tue Aug 17 07:45:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE9D5C4320E for ; Tue, 17 Aug 2021 07:46:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 917F660FD7 for ; Tue, 17 Aug 2021 07:46:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238814AbhHQHrL (ORCPT ); Tue, 17 Aug 2021 03:47:11 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:49282 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234779AbhHQHrA (ORCPT ); Tue, 17 Aug 2021 03:47:00 -0400 X-UUID: 1576c2985ca245b4873d502c9a261f40-20210817 X-UUID: 1576c2985ca245b4873d502c9a261f40-20210817 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 161453402; Tue, 17 Aug 2021 15:46:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:21 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [v2,05/12] dt-bindings: pinctrl: update bindings for MT7986 SoC Date: Tue, 17 Aug 2021 15:45:50 +0800 Message-ID: <20210817074557.30953-6-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This updates bindings for MT7986 pinctrl driver. The difference of pinctrl between mt7986a and mt7986b is that pin-41 to pin-65 do not exist on mt7986b Signed-off-by: Sam Shih --- v2 : deleted the redundant description of mt7986a/mt7986b --- .../bindings/pinctrl/pinctrl-mt7622.txt | 170 ++++++++++++++++++ 1 file changed, 170 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt index 7a7aca1ed705..4711dfb2ea77 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt @@ -4,6 +4,8 @@ Required properties for the root node: - compatible: Should be one of the following "mediatek,mt7622-pinctrl" for MT7622 SoC "mediatek,mt7629-pinctrl" for MT7629 SoC + "mediatek,mt7986a-pinctrl" for MT7986a SoC + "mediatek,mt7986b-pinctrl" for MT7986b SoC - reg: offset and length of the pinctrl space - gpio-controller: Marks the device node as a GPIO controller. @@ -455,6 +457,174 @@ Valid values for groups are: "wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 +== Valid values for pins, function and groups on MT7986a and MT7986b == + +Valid values for pins are: +pins can be referenced via the pin names as the below table shown and the +related physical number is also put ahead of those names which helps cross +references to pins between groups to know whether pins assignment conflict +happens among devices try to acquire those available pins. + + Pin #: Valid values for pins + ----------------------------- + PIN 0: "SYS_WATCHDOG" + PIN 1: "WF2G_LED" + PIN 2: "WF5G_LED" + PIN 3: "I2C_SCL" + PIN 4: "I2C_SDA" + PIN 5: "GPIO_0" + PIN 6: "GPIO_1" + PIN 7: "GPIO_2" + PIN 8: "GPIO_3" + PIN 9: "GPIO_4" + PIN 10: "GPIO_5" + PIN 11: "GPIO_6" + PIN 12: "GPIO_7" + PIN 13: "GPIO_8" + PIN 14: "GPIO_9" + PIN 15: "GPIO_10" + PIN 16: "GPIO_11" + PIN 17: "GPIO_12" + PIN 18: "GPIO_13" + PIN 19: "GPIO_14" + PIN 20: "GPIO_15" + PIN 21: "PWM0" + PIN 22: "PWM1" + PIN 23: "SPI0_CLK" + PIN 24: "SPI0_MOSI" + PIN 25: "SPI0_MISO" + PIN 26: "SPI0_CS" + PIN 27: "SPI0_HOLD" + PIN 28: "SPI0_WP" + PIN 29: "SPI1_CLK" + PIN 30: "SPI1_MOSI" + PIN 31: "SPI1_MISO" + PIN 32: "SPI1_CS" + PIN 33: "SPI2_CLK" + PIN 34: "SPI2_MOSI" + PIN 35: "SPI2_MISO" + PIN 36: "SPI2_CS" + PIN 37: "SPI2_HOLD" + PIN 38: "SPI2_WP" + PIN 39: "UART0_RXD" + PIN 40: "UART0_TXD" + PIN 41: "PCIE_PERESET_N" + PIN 42: "UART1_RXD" + PIN 43: "UART1_TXD" + PIN 44: "UART1_CTS" + PIN 45: "UART1_RTS" + PIN 46: "UART2_RXD" + PIN 47: "UART2_TXD" + PIN 48: "UART2_CTS" + PIN 49: "UART2_RTS" + PIN 50: "EMMC_DATA_0" + PIN 51: "EMMC_DATA_1" + PIN 52: "EMMC_DATA_2" + PIN 53: "EMMC_DATA_3" + PIN 54: "EMMC_DATA_4" + PIN 55: "EMMC_DATA_5" + PIN 56: "EMMC_DATA_6" + PIN 57: "EMMC_DATA_7" + PIN 58: "EMMC_CMD" + PIN 59: "EMMC_CK" + PIN 60: "EMMC_DSL" + PIN 61: "EMMC_RSTB" + PIN 62: "PCM_DTX" + PIN 63: "PCM_DRX" + PIN 64: "PCM_CLK" + PIN 65: "PCM_FS" + PIN 66: "MT7531_INT" + PIN 67: "SMI_MDC" + PIN 68: "SMI_MDIO" + PIN 69: "WF0_DIG_RESETB" + PIN 70: "WF0_CBA_RESETB" + PIN 71: "WF0_XO_REQ" + PIN 72: "WF0_TOP_CLK" + PIN 73: "WF0_TOP_DATA" + PIN 74: "WF0_HB1" + PIN 75: "WF0_HB2" + PIN 76: "WF0_HB3" + PIN 77: "WF0_HB4" + PIN 78: "WF0_HB0" + PIN 79: "WF0_HB0_B" + PIN 80: "WF0_HB5" + PIN 81: "WF0_HB6" + PIN 82: "WF0_HB7" + PIN 83: "WF0_HB8" + PIN 84: "WF0_HB9" + PIN 85: "WF0_HB10" + PIN 86: "WF1_DIG_RESETB" + PIN 87: "WF1_CBA_RESETB" + PIN 88: "WF1_XO_REQ" + PIN 89: "WF1_TOP_CLK" + PIN 90: "WF1_TOP_DATA" + PIN 91: "WF1_HB1" + PIN 92: "WF1_HB2" + PIN 93: "WF1_HB3" + PIN 94: "WF1_HB4" + PIN 95: "WF1_HB0" + PIN 96: "WF1_HB0_B" + PIN 97: "WF1_HB5" + PIN 98: "WF1_HB6" + PIN 99: "WF1_HB7" + PIN 100: "WF1_HB8" + +There is no PIN 41 to PIN 65 above on mt7686b, you can only use those +pins on mt7986a. + +Valid values for function are: + "audio, "emmc", "eth", "i2c", "wifi", "led", "flash", "pcie", + "pwm", "spi", "uart", "watchdog" + +There is no "audio", "pcie" functions above on mt7986b, you can only +use those functions on mt7986a. + +Valid values for groups are: +additional data is put followingly with valid value allowing us to know which +applicable function and which relevant pins (in pin#) are able applied for that +group. + + Valid value function pins (in pin#) + ------------------------------------------------------------------------- + "watchdog" "watchdog" 0 + "wifi_led" "led" 1, 2 + "i2c" "i2c" 3, 4 + "uart1_0" "uart" 7, 8, 9, 10 + "pcie_clk" "pcie" 9 + "pcie_wake" "pcie" 10 + "spi1_0" "spi" 11, 12, 13, 14 + "pwm1_1" "pwm" 20, + "pwm0" "pwm" 21, + "pwm1_0" "pwm" 22, + "snfi" "flash" 23, 24, 25, 26, 27, 28 + "spi1_2" "spi" 29, 30, 31, 32 + "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, + 28, 29, 30, 31, 32 + "spi1_1" "spi" 23, 24, 25, 26 + "uart1_2" "uart" 29, 30, 31, 32 + "uart1_1" "uart" 23, 24, 25, 26 + "uart2_0" "uart" 29, 30, 31, 32 + "spi0" "spi" 33, 34, 35, 36 + "spi0_wp_hold" "spi" 37, 38 + "uart1_3_rx_tx" "uart" 35, 36 + "uart1_3_cts_rts" "uart" 37, 38 + "uart2_1" "uart" 33, 34, 35, 36 + "spi1_3" "spi" 33, 34, 35, 36 + "uart0" "uart" 39, 40 + "pcie_pereset" "pcie" 41 + "uart1" "uart" 42, 43, 44, 45 + "uart2" "uart" 46, 47, 48, 49 + "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, + 56, 57, 57, 59, 60, 61 + "pcm" "audio" 62, 63, 64, 65 + "i2s" "audio" 62, 63, 64, 65 + "switch_int" "eth" 66 + "mdc_mdio" "eth" 67 + +There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", and "i2s" groups +above on mt7986b, you can only use those groups on mt7986a. + + Example: pio: pinctrl@10211000 { From patchwork Tue Aug 17 07:45:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498210 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA840C4320A for ; Tue, 17 Aug 2021 07:46:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B302160FD8 for ; Tue, 17 Aug 2021 07:46:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238401AbhHQHrR (ORCPT ); Tue, 17 Aug 2021 03:47:17 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:49496 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S238932AbhHQHrI (ORCPT ); Tue, 17 Aug 2021 03:47:08 -0400 X-UUID: 6a52e664a3cd4481ae5920f794536755-20210817 X-UUID: 6a52e664a3cd4481ae5920f794536755-20210817 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1263032662; Tue, 17 Aug 2021 15:46:25 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:24 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [v2,06/12] pinctrl: mediatek: add support for MT7986 SoC Date: Tue, 17 Aug 2021 15:45:51 +0800 Message-ID: <20210817074557.30953-7-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This commit includes pinctrl driver for Mediatek MT7986 The difference of pinctrl between mt7986a and mt7986b is that pin-41 to pin-65 do not exist on mt7986b Signed-off-by: Sam Shih --- v2: applied the comment suggested by reviewers: - for the pins not ballout, we can fill .name in struct mtk_pin_desc as NULL and return -ENOTSUPP in gpio/pinconf ops. --- drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt7986.c | 1217 +++++++++++++++++++++ 3 files changed, 1225 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7986.c diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 7040a7a7bd5d..66db4ac5d169 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -119,6 +119,13 @@ config PINCTRL_MT7622 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE +config PINCTRL_MT7986 + bool "Mediatek MT7986 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_MOORE + config PINCTRL_MT8167 bool "Mediatek MT8167 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 1bb7f9c65bc2..1e3931d924e7 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o +obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c new file mode 100644 index 000000000000..808ae4e03eb2 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -0,0 +1,1217 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT7986 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam Shih + */ + +#include "pinctrl-moore.h" + +#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) +#define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number } + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +/** + * enum - Locking variants of the iocfg bases + * + * MT7986 have multiple bases to program pin configuration listed as the below: + * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000, + * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000, + * _i_based could be used to indicate what base the pin should be mapped into. + * + * Each iocfg register base control different group of pads on the SoC + * + * + * chip carrier + * + * A B C D E F G H + * +------------------------+ + * 8 | o o o o o o o o | + * 7 | o o o o o o o o | + * 6 | o o o o o o o o | + * 5 | o o o o o o o o | + * 4 | o o o o o o o o | + * 3 | o o o o o o o o | + * 2 | o o o o o o o o | + * 1 | o o o o o o o o | + * +------------------------+ + * + * inside Chip carrier + * + * A B C D E F G H + * +------------------------+ + * 8 | | + * 7 | TL TR | + * 6 | +---------+ | + * 5 | LT | | RT | + * 4 | | | | + * 3 | LB | | RB | + * 2 | +---------+ | + * 1 | | + * +------------------------+ + * + */ + +enum { + GPIO_BASE, + IOCFG_RT_BASE, + IOCFG_RB_BASE, + IOCFG_LT_BASE, + IOCFG_LB_BASE, + IOCFG_TR_BASE, + IOCFG_TL_BASE, +}; + +static const char *const mt7986_pinctrl_register_base_names[] = { + "gpio_base", "iocfg_rt_base", "iocfg_rb_base", "iocfg_lt_base", + "iocfg_lb_base", "iocfg_tr_base", "iocfg_tl_base", +}; + +static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = { + PIN_FIELD(0, 40, 0x300, 0x10, 0, 4), + PIN_FIELD(41, 65, 0x350, 0x10, 4, 4), + PIN_FIELD(66, 68, 0x380, 0x10, 8, 4), + PIN_FIELD(69, 100, 0x380, 0x10, 20, 4), +}; + +static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = { + PIN_FIELD(0, 40, 0x0, 0x10, 0, 1), + PIN_FIELD(41, 65, 0x10, 0x10, 9, 1), + PIN_FIELD(66, 68, 0x20, 0x10, 2, 1), + PIN_FIELD(69, 100, 0x20, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_di_range[] = { + PIN_FIELD(0, 40, 0x200, 0x10, 0, 1), + PIN_FIELD(41, 65, 0x210, 0x10, 9, 1), + PIN_FIELD(66, 68, 0x220, 0x10, 2, 1), + PIN_FIELD(69, 100, 0x220, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_do_range[] = { + PIN_FIELD(0, 40, 0x100, 0x10, 0, 1), + PIN_FIELD(41, 65, 0x110, 0x10, 9, 1), + PIN_FIELD(66, 68, 0x120, 0x10, 2, 1), + PIN_FIELD(69, 100, 0x120, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x20, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x30, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x30, 0x10, 16, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x30, 0x10, 19, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x30, 0x10, 20, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x40, 0x10, 18, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x40, 0x10, 19, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x40, 0x10, 22, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x40, 0x10, 23, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x40, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x40, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x40, 0x10, 26, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x40, 0x10, 27, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x40, 0x10, 24, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x40, 0x10, 25, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1), + PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x30, 0x10, 15, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x30, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x90, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0xf0, 0x10, 1, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0xf0, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0xf0, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0xf0, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0xf0, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0xf0, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0xf0, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0xf0, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0xf0, 0x10, 7, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0xc0, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0xc0, 0x10, 14, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0xc0, 0x10, 16, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0xc0, 0x10, 20, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xf0, 0x10, 19, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xf0, 0x10, 23, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xf0, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xf0, 0x10, 27, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xf0, 0x10, 25, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0xc0, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0xc0, 0x10, 4, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0xc0, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0xc0, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0xc0, 0x10, 7, 1), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0xc0, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0xc0, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0xc0, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1), + PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x80, 0x10, 14, 1), + PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x80, 0x10, 15, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1), + PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x80, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x80, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x80, 0x10, 13, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x70, 0x10, 13, 1), + PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x70, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x70, 0x10, 8, 1), + PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x70, 0x10, 9, 1), + PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x70, 0x10, 10, 1), + PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x70, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = { + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1), + PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x50, 0x10, 15, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x50, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = { + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1), + PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x40, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x00, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x00, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x20, 0x10, 9, 3), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x20, 0x10, 12, 3), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x20, 0x10, 6, 3), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x20, 0x10, 21, 3), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x20, 0x10, 24, 3), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x20, 0x10, 15, 3), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x20, 0x10, 18, 3), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x00, 0x10, 2, 3), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x00, 0x10, 5, 3), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x00, 0x10, 8, 3), + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x10, 0x10, 2, 3), + PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x10, 0x10, 5, 3), +}; + +static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x60, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x60, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x60, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x60, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x40, 0x10, 16, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x40, 0x10, 19, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x40, 0x10, 20, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x60, 0x10, 18, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x60, 0x10, 19, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x60, 0x10, 22, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x60, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x60, 0x10, 26, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x60, 0x10, 24, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x40, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x70, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x70, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x70, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x70, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x70, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x50, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x50, 0x10, 16, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x50, 0x10, 19, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x50, 0x10, 20, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 19, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 22, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 26, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 24, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x50, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x80, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x80, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x80, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x80, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x80, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x80, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x80, 0x10, 7, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x60, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x60, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x60, 0x10, 14, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x60, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x60, 0x10, 16, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x60, 0x10, 19, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x60, 0x10, 20, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x80, 0x10, 18, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x80, 0x10, 19, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x80, 0x10, 22, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x80, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x80, 0x10, 26, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x80, 0x10, 24, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x60, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x60, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x60, 0x10, 10, 1), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x60, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x60, 0x10, 4, 1), +}; + +static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7986a_pins[] = { + MT7986_PIN(0, "SYS_WATCHDOG"), + MT7986_PIN(1, "WF2G_LED"), + MT7986_PIN(2, "WF5G_LED"), + MT7986_PIN(3, "I2C_SCL"), + MT7986_PIN(4, "I2C_SDA"), + MT7986_PIN(5, "GPIO_0"), + MT7986_PIN(6, "GPIO_1"), + MT7986_PIN(7, "GPIO_2"), + MT7986_PIN(8, "GPIO_3"), + MT7986_PIN(9, "GPIO_4"), + MT7986_PIN(10, "GPIO_5"), + MT7986_PIN(11, "GPIO_6"), + MT7986_PIN(12, "GPIO_7"), + MT7986_PIN(13, "GPIO_8"), + MT7986_PIN(14, "GPIO_9"), + MT7986_PIN(15, "GPIO_10"), + MT7986_PIN(16, "GPIO_11"), + MT7986_PIN(17, "GPIO_12"), + MT7986_PIN(18, "GPIO_13"), + MT7986_PIN(19, "GPIO_14"), + MT7986_PIN(20, "GPIO_15"), + MT7986_PIN(21, "PWM0"), + MT7986_PIN(22, "PWM1"), + MT7986_PIN(23, "SPI0_CLK"), + MT7986_PIN(24, "SPI0_MOSI"), + MT7986_PIN(25, "SPI0_MISO"), + MT7986_PIN(26, "SPI0_CS"), + MT7986_PIN(27, "SPI0_HOLD"), + MT7986_PIN(28, "SPI0_WP"), + MT7986_PIN(29, "SPI1_CLK"), + MT7986_PIN(30, "SPI1_MOSI"), + MT7986_PIN(31, "SPI1_MISO"), + MT7986_PIN(32, "SPI1_CS"), + MT7986_PIN(33, "SPI2_CLK"), + MT7986_PIN(34, "SPI2_MOSI"), + MT7986_PIN(35, "SPI2_MISO"), + MT7986_PIN(36, "SPI2_CS"), + MT7986_PIN(37, "SPI2_HOLD"), + MT7986_PIN(38, "SPI2_WP"), + MT7986_PIN(39, "UART0_RXD"), + MT7986_PIN(40, "UART0_TXD"), + MT7986_PIN(41, "PCIE_PERESET_N"), + MT7986_PIN(42, "UART1_RXD"), + MT7986_PIN(43, "UART1_TXD"), + MT7986_PIN(44, "UART1_CTS"), + MT7986_PIN(45, "UART1_RTS"), + MT7986_PIN(46, "UART2_RXD"), + MT7986_PIN(47, "UART2_TXD"), + MT7986_PIN(48, "UART2_CTS"), + MT7986_PIN(49, "UART2_RTS"), + MT7986_PIN(50, "EMMC_DATA_0"), + MT7986_PIN(51, "EMMC_DATA_1"), + MT7986_PIN(52, "EMMC_DATA_2"), + MT7986_PIN(53, "EMMC_DATA_3"), + MT7986_PIN(54, "EMMC_DATA_4"), + MT7986_PIN(55, "EMMC_DATA_5"), + MT7986_PIN(56, "EMMC_DATA_6"), + MT7986_PIN(57, "EMMC_DATA_7"), + MT7986_PIN(58, "EMMC_CMD"), + MT7986_PIN(59, "EMMC_CK"), + MT7986_PIN(60, "EMMC_DSL"), + MT7986_PIN(61, "EMMC_RSTB"), + MT7986_PIN(62, "PCM_DTX"), + MT7986_PIN(63, "PCM_DRX"), + MT7986_PIN(64, "PCM_CLK"), + MT7986_PIN(65, "PCM_FS"), + MT7986_PIN(66, "MT7531_INT"), + MT7986_PIN(67, "SMI_MDC"), + MT7986_PIN(68, "SMI_MDIO"), + MT7986_PIN(69, "WF0_DIG_RESETB"), + MT7986_PIN(70, "WF0_CBA_RESETB"), + MT7986_PIN(71, "WF0_XO_REQ"), + MT7986_PIN(72, "WF0_TOP_CLK"), + MT7986_PIN(73, "WF0_TOP_DATA"), + MT7986_PIN(74, "WF0_HB1"), + MT7986_PIN(75, "WF0_HB2"), + MT7986_PIN(76, "WF0_HB3"), + MT7986_PIN(77, "WF0_HB4"), + MT7986_PIN(78, "WF0_HB0"), + MT7986_PIN(79, "WF0_HB0_B"), + MT7986_PIN(80, "WF0_HB5"), + MT7986_PIN(81, "WF0_HB6"), + MT7986_PIN(82, "WF0_HB7"), + MT7986_PIN(83, "WF0_HB8"), + MT7986_PIN(84, "WF0_HB9"), + MT7986_PIN(85, "WF0_HB10"), + MT7986_PIN(86, "WF1_DIG_RESETB"), + MT7986_PIN(87, "WF1_CBA_RESETB"), + MT7986_PIN(88, "WF1_XO_REQ"), + MT7986_PIN(89, "WF1_TOP_CLK"), + MT7986_PIN(90, "WF1_TOP_DATA"), + MT7986_PIN(91, "WF1_HB1"), + MT7986_PIN(92, "WF1_HB2"), + MT7986_PIN(93, "WF1_HB3"), + MT7986_PIN(94, "WF1_HB4"), + MT7986_PIN(95, "WF1_HB0"), + MT7986_PIN(96, "WF1_HB0_B"), + MT7986_PIN(97, "WF1_HB5"), + MT7986_PIN(98, "WF1_HB6"), + MT7986_PIN(99, "WF1_HB7"), + MT7986_PIN(100, "WF1_HB8"), +}; + +static const struct mtk_pin_desc mt7986b_pins[] = { + MT7986_PIN(0, "SYS_WATCHDOG"), + MT7986_PIN(1, "WF2G_LED"), + MT7986_PIN(2, "WF5G_LED"), + MT7986_PIN(3, "I2C_SCL"), + MT7986_PIN(4, "I2C_SDA"), + MT7986_PIN(5, "GPIO_0"), + MT7986_PIN(6, "GPIO_1"), + MT7986_PIN(7, "GPIO_2"), + MT7986_PIN(8, "GPIO_3"), + MT7986_PIN(9, "GPIO_4"), + MT7986_PIN(10, "GPIO_5"), + MT7986_PIN(11, "GPIO_6"), + MT7986_PIN(12, "GPIO_7"), + MT7986_PIN(13, "GPIO_8"), + MT7986_PIN(14, "GPIO_9"), + MT7986_PIN(15, "GPIO_10"), + MT7986_PIN(16, "GPIO_11"), + MT7986_PIN(17, "GPIO_12"), + MT7986_PIN(18, "GPIO_13"), + MT7986_PIN(19, "GPIO_14"), + MT7986_PIN(20, "GPIO_15"), + MT7986_PIN(21, "PWM0"), + MT7986_PIN(22, "PWM1"), + MT7986_PIN(23, "SPI0_CLK"), + MT7986_PIN(24, "SPI0_MOSI"), + MT7986_PIN(25, "SPI0_MISO"), + MT7986_PIN(26, "SPI0_CS"), + MT7986_PIN(27, "SPI0_HOLD"), + MT7986_PIN(28, "SPI0_WP"), + MT7986_PIN(29, "SPI1_CLK"), + MT7986_PIN(30, "SPI1_MOSI"), + MT7986_PIN(31, "SPI1_MISO"), + MT7986_PIN(32, "SPI1_CS"), + MT7986_PIN(33, "SPI2_CLK"), + MT7986_PIN(34, "SPI2_MOSI"), + MT7986_PIN(35, "SPI2_MISO"), + MT7986_PIN(36, "SPI2_CS"), + MT7986_PIN(37, "SPI2_HOLD"), + MT7986_PIN(38, "SPI2_WP"), + MT7986_PIN(39, "UART0_RXD"), + MT7986_PIN(40, "UART0_TXD"), + MT7986_NOT_BALLOUT_PIN(41), + MT7986_NOT_BALLOUT_PIN(42), + MT7986_NOT_BALLOUT_PIN(43), + MT7986_NOT_BALLOUT_PIN(44), + MT7986_NOT_BALLOUT_PIN(45), + MT7986_NOT_BALLOUT_PIN(46), + MT7986_NOT_BALLOUT_PIN(47), + MT7986_NOT_BALLOUT_PIN(48), + MT7986_NOT_BALLOUT_PIN(49), + MT7986_NOT_BALLOUT_PIN(50), + MT7986_NOT_BALLOUT_PIN(51), + MT7986_NOT_BALLOUT_PIN(52), + MT7986_NOT_BALLOUT_PIN(53), + MT7986_NOT_BALLOUT_PIN(54), + MT7986_NOT_BALLOUT_PIN(55), + MT7986_NOT_BALLOUT_PIN(56), + MT7986_NOT_BALLOUT_PIN(57), + MT7986_NOT_BALLOUT_PIN(58), + MT7986_NOT_BALLOUT_PIN(59), + MT7986_NOT_BALLOUT_PIN(60), + MT7986_NOT_BALLOUT_PIN(61), + MT7986_NOT_BALLOUT_PIN(62), + MT7986_NOT_BALLOUT_PIN(63), + MT7986_NOT_BALLOUT_PIN(64), + MT7986_NOT_BALLOUT_PIN(65), + MT7986_PIN(66, "MT7531_INT"), + MT7986_PIN(67, "SMI_MDC"), + MT7986_PIN(68, "SMI_MDIO"), + MT7986_PIN(69, "WF0_DIG_RESETB"), + MT7986_PIN(70, "WF0_CBA_RESETB"), + MT7986_PIN(71, "WF0_XO_REQ"), + MT7986_PIN(72, "WF0_TOP_CLK"), + MT7986_PIN(73, "WF0_TOP_DATA"), + MT7986_PIN(74, "WF0_HB1"), + MT7986_PIN(75, "WF0_HB2"), + MT7986_PIN(76, "WF0_HB3"), + MT7986_PIN(77, "WF0_HB4"), + MT7986_PIN(78, "WF0_HB0"), + MT7986_PIN(79, "WF0_HB0_B"), + MT7986_PIN(80, "WF0_HB5"), + MT7986_PIN(81, "WF0_HB6"), + MT7986_PIN(82, "WF0_HB7"), + MT7986_PIN(83, "WF0_HB8"), + MT7986_PIN(84, "WF0_HB9"), + MT7986_PIN(85, "WF0_HB10"), + MT7986_PIN(86, "WF1_DIG_RESETB"), + MT7986_PIN(87, "WF1_CBA_RESETB"), + MT7986_PIN(88, "WF1_XO_REQ"), + MT7986_PIN(89, "WF1_TOP_CLK"), + MT7986_PIN(90, "WF1_TOP_DATA"), + MT7986_PIN(91, "WF1_HB1"), + MT7986_PIN(92, "WF1_HB2"), + MT7986_PIN(93, "WF1_HB3"), + MT7986_PIN(94, "WF1_HB4"), + MT7986_PIN(95, "WF1_HB0"), + MT7986_PIN(96, "WF1_HB0_B"), + MT7986_PIN(97, "WF1_HB5"), + MT7986_PIN(98, "WF1_HB6"), + MT7986_PIN(99, "WF1_HB7"), + MT7986_PIN(100, "WF1_HB8"), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +static int mt7986_watchdog_pins[] = { 0, }; +static int mt7986_watchdog_funcs[] = { 1, }; + +static int mt7986_wifi_led_pins[] = { 1, 2, }; +static int mt7986_wifi_led_funcs[] = { 1, 1, }; + +static int mt7986_i2c_pins[] = { 3, 4, }; +static int mt7986_i2c_funcs[] = { 1, 1, }; + +static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; +static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; +static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_pwm1_1_pins[] = { 20, }; +static int mt7986_pwm1_1_funcs[] = { 2, }; + +static int mt7986_pwm0_pins[] = { 21, }; +static int mt7986_pwm0_funcs[] = { 1, }; + +static int mt7986_pwm1_0_pins[] = { 22, }; +static int mt7986_pwm1_0_funcs[] = { 1, }; + +static int mt7986_emmc_45_pins[] = { + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, }; +static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; +static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; + +static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; +static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; +static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; + +static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; +static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; +static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; +static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; + +static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; +static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; +static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; + +static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; +static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; +static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; + +static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; +static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; + +static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; +static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; + +static int mt7986_uart0_pins[] = { 39, 40, }; +static int mt7986_uart0_funcs[] = { 1, 1, }; + +static int mt7986_pcie_reset_pins[] = { 41, }; +static int mt7986_pcie_reset_funcs[] = { 1, }; + +static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; +static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; +static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_emmc_51_pins[] = { + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, }; +static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; +static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; +static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_switch_int_pins[] = { 66, }; +static int mt7986_switch_int_funcs[] = { 1, }; + +static int mt7986_mdc_mdio_pins[] = { 67, 68, }; +static int mt7986_mdc_mdio_funcs[] = { 1, 1, }; + +static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; +static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; +static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static int mt7986_wf_dbdc_pins[] = { + 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, }; +static int mt7986_wf_dbdc_funcs[] = { + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +static int mt7986_pcie_clk_pins[] = { 9, }; +static int mt7986_pcie_clk_funcs[] = { 1, }; + +static int mt7986_pcie_wake_pins[] = { 10, }; +static int mt7986_pcie_wake_funcs[] = { 1, }; + +static const struct group_desc mt7986_groups[] = { + PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog), + PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), + PINCTRL_PIN_GROUP("i2c", mt7986_i2c), + PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), + PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), + PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), + PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), + PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1), + PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0), + PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0), + PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45), + PINCTRL_PIN_GROUP("snfi", mt7986_snfi), + PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), + PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), + PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), + PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2), + PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0), + PINCTRL_PIN_GROUP("spi0", mt7986_spi0), + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), + PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), + PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx), + PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts), + PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3), + PINCTRL_PIN_GROUP("uart0", mt7986_uart0), + PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int), + PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio), + PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset), + PINCTRL_PIN_GROUP("uart1", mt7986_uart1), + PINCTRL_PIN_GROUP("uart2", mt7986_uart2), + PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51), + PINCTRL_PIN_GROUP("pcm", mt7986_pcm), + PINCTRL_PIN_GROUP("i2s", mt7986_i2s), + PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g), + PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g), + PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ + +static const char *mt7986_audio_groups[] = { "pcm", "i2s" }; +static const char *mt7986_emmc_groups[] = { "emmc_45", "emmc_51", }; +static const char *mt7986_ethernet_groups[] = { "switch_int", "mdc_mdio", }; +static const char *mt7986_i2c_groups[] = { "i2c", }; +static const char *mt7986_led_groups[] = { "wifi_led", }; +static const char *mt7986_flash_groups[] = { "snfi", }; +static const char *mt7986_pcie_groups[] = { + "pcie_clk", "pcie_wake", "pcie_pereset" }; +static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", }; +static const char *mt7986_spi_groups[] = { + "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; + +static const char *mt7986_uart_groups[] = { + "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", + "uart2_0", "uart2_1", "uart0", "uart1", "uart2", +}; +static const char *mt7986_wdt_groups[] = { "watchdog", }; +static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", }; + +static const struct function_desc mt7986_functions[] = { + {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)}, + {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)}, + {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)}, + {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)}, + {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)}, + {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)}, + {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)}, + {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)}, + {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)}, + {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)}, + {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)}, + {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)}, +}; + +static const struct mtk_eint_hw mt7986a_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7986a_pins), + .db_cnt = 16, +}; + +static const struct mtk_eint_hw mt7986b_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7986b_pins), + .db_cnt = 16, +}; + +static struct mtk_pin_soc mt7986a_data = { + .reg_cal = mt7986_reg_cals, + .pins = mt7986a_pins, + .npins = ARRAY_SIZE(mt7986a_pins), + .grps = mt7986_groups, + .ngrps = ARRAY_SIZE(mt7986_groups), + .funcs = mt7986_functions, + .nfuncs = ARRAY_SIZE(mt7986_functions), + .eint_hw = &mt7986a_eint_hw, + .gpio_m = 0, + .ies_present = false, + .base_names = mt7986_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static struct mtk_pin_soc mt7986b_data = { + .reg_cal = mt7986_reg_cals, + .pins = mt7986b_pins, + .npins = ARRAY_SIZE(mt7986b_pins), + .grps = mt7986_groups, + .ngrps = ARRAY_SIZE(mt7986_groups), + .funcs = mt7986_functions, + .nfuncs = ARRAY_SIZE(mt7986_functions), + .eint_hw = &mt7986b_eint_hw, + .gpio_m = 0, + .ies_present = false, + .base_names = mt7986_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static const struct of_device_id mt7986a_pinctrl_of_match[] = { + {.compatible = "mediatek,mt7986a-pinctrl",}, + {} +}; + +static const struct of_device_id mt7986b_pinctrl_of_match[] = { + {.compatible = "mediatek,mt7986b-pinctrl",}, + {} +}; + +static int mt7986a_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7986a_data); +} + +static int mt7986b_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7986b_data); +} + +static struct platform_driver mt7986a_pinctrl_driver = { + .driver = { + .name = "mt7986a-pinctrl", + .of_match_table = mt7986a_pinctrl_of_match, + }, + .probe = mt7986a_pinctrl_probe, +}; + +static struct platform_driver mt7986b_pinctrl_driver = { + .driver = { + .name = "mt7986b-pinctrl", + .of_match_table = mt7986b_pinctrl_of_match, + }, + .probe = mt7986b_pinctrl_probe, +}; + +static int __init mt7986a_pinctrl_init(void) +{ + return platform_driver_register(&mt7986a_pinctrl_driver); +} + +static int __init mt7986b_pinctrl_init(void) +{ + return platform_driver_register(&mt7986b_pinctrl_driver); +} + +arch_initcall(mt7986a_pinctrl_init); +arch_initcall(mt7986b_pinctrl_init); From patchwork Tue Aug 17 07:45:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B82CC4320A for ; Tue, 17 Aug 2021 07:46:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 428CA60F5E for ; Tue, 17 Aug 2021 07:46:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239169AbhHQHra (ORCPT ); Tue, 17 Aug 2021 03:47:30 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:48454 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231500AbhHQHrM (ORCPT ); Tue, 17 Aug 2021 03:47:12 -0400 X-UUID: 70fb9f4f649a49bf93bf6b839e4a4a5d-20210817 X-UUID: 70fb9f4f649a49bf93bf6b839e4a4a5d-20210817 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1948333543; Tue, 17 Aug 2021 15:46:35 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:33 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [v2, 10/12] dt-bindings: watchdog: Add compatible for Mediatek MT7986 Date: Tue, 17 Aug 2021 15:45:55 +0800 Message-ID: <20210817074557.30953-11-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This commit adds dt-binding documentation of watchdog for Mediatek MT7986 SoC Platform. Signed-off-by: Sam Shih Acked-by: Rob Herring Reviewed-by: Guenter Roeck --- v2: added an Acked-by tag and a Reviewed-by tag --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 416d716403f6..a4e31ce96e0e 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -13,6 +13,7 @@ Required properties: "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 + "mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986 "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 "mediatek,mt8192-wdt": for MT8192 From patchwork Tue Aug 17 07:45:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8EEEC25AEC for ; Tue, 17 Aug 2021 07:46:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C258060F5E for ; Tue, 17 Aug 2021 07:46:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239185AbhHQHra (ORCPT ); Tue, 17 Aug 2021 03:47:30 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:48608 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S239009AbhHQHrP (ORCPT ); Tue, 17 Aug 2021 03:47:15 -0400 X-UUID: ea9bf17ee3c64f79999fbd7d0a5f7a9b-20210817 X-UUID: ea9bf17ee3c64f79999fbd7d0a5f7a9b-20210817 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 343370493; Tue, 17 Aug 2021 15:46:38 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:36 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:36 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [v2,11/12] arm64: dts: mediatek: add mt7986a support Date: Tue, 17 Aug 2021 15:45:56 +0800 Message-ID: <20210817074557.30953-12-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add basic chip support for Mediatek mt7986a, include uart nodes with correct clocks, rng node with correct clock, and watchdog node and mt7986a pinctrl node. Add cpu node, timer node, gic node, psci and reserved-memory node for ARM Trusted Firmware, Add clock controller nodes, include 40M clock source, topckgen, infracfg, apmixedsys and ethernet subsystem. Signed-off-by: Sam Shih --- v2: modified clock and uart node due to clock driver updated --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 49 ++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 227 +++++++++++++++++++ 3 files changed, 277 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 4f68ebed2e31..e6c3a73b9e4a 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts new file mode 100644 index 000000000000..a58347c09ab2 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7986a.dtsi" + +/ { + model = "MediaTek MT7986a RFB"; + compatible = "mediatek,mt7986a-rfb"; + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11002000"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&pio { + uart1_pins: uart1-pins-42-to-45 { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart1-pins-46-to-49 { + mux { + function = "uart"; + groups = "uart2"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi new file mode 100644 index 000000000000..dfe3e7101031 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +#include +#include +#include + +/ { + compatible = "mediatek,mt7986a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk40m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "clkxtal"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + enable-method = "psci"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + #cooling-cells = <2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + clock-frequency = <13000000>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c080000 0 0x200000>; + interrupts = ; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7986-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7986-topckgen", "syscon"; + reg = <0 0x1001B000 0 0x1000>; + #clock-cells = <1>; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + status = "disabled"; + }; + + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7986-apmixedsys"; + reg = <0 0x1001E000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7986a-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c30000 0 0x1000>, + <0 0x11c40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base", + "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base", + "iocfg_tl_base", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 100>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7986-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7986-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + + trng: trng@1020f000 { + compatible = "mediatek,mt7986-rng", + "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&infracfg CLK_INFRA_TRNG_CK>; + clock-names = "rng"; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART0_SEL>, + <&infracfg CLK_INFRA_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART1_SEL>, + <&infracfg CLK_INFRA_UART1_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART2_SEL>, + <&infracfg CLK_INFRA_UART2_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; + status = "disabled"; + }; + + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7986-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + }; + +};