From patchwork Mon Aug 23 13:19:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 501604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D8F8C4338F for ; Mon, 23 Aug 2021 13:19:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4287461373 for ; Mon, 23 Aug 2021 13:19:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237353AbhHWNUO (ORCPT ); Mon, 23 Aug 2021 09:20:14 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:43102 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236627AbhHWNUM (ORCPT ); Mon, 23 Aug 2021 09:20:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1629724769; x=1661260769; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GfCpqfwty9G95EZgsnU3OM+Vn0Fn3zNv5DURgJ4uTms=; b=x/O83CYbpT73YqvD9La3gXJQkjduyEvcAALHDXf8WI1gQr1gX0TjvqLg TtW/eKJ1wAU/FVP/Pm7Z3aHQ/dtREcyIPbGctAT3EkaN3BRAuqfzNUUrX pMOXhtmm2Fe1mWKCW8waSTSR+G+zfSvYzsrp/n0XFgiBCF4HcnGgL9xXF ahINLIJjS5CsOjVjiDd8tQT+u17SA7q/TMVs6upx1sJ0EI3xO9dwRHbXa K11Q5D2z3qjSJ16McfOXwtg9mEaDkW7hAPNJhO5JeZwb3TcfpFjqZ+tZy 3GcKnbGRlJcEUKwIQ5L6r/aczMbbCYs8bECSL0zHhi0K11rdchy1WJxYx Q==; IronPort-SDR: igVBdNFePGPVYkV2RAbHC7IIXkVO3lfU//duS+5uB5EZ63JVQouAdxSHkEhzfL3WW+CK+q3Xn4 ofmUHnSwgy+vUfHBw7Kvu8YHis5lqZOHy431xJifleY4TSIAZ2XFNQYLbKMFcCRAhcYzz4WU/h Cx42jO5eB2d8EpC+0JrmhS2LCEKjL4ESLOe1DJzLg3AXmxzTgnR9AvPR14A+qdVKi1m3D4x6e6 VjwOyRaz8RuFQ0unhGpBZwS9Pvd4D+aEED4TsXoLG1d5Kr1+xbTYJqtU5cTG6bXCzIjy266jgx rmL6ewbAjoL3JA5lv/oPZSXA X-IronPort-AV: E=Sophos;i="5.84,344,1620716400"; d="scan'208";a="129239608" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Aug 2021 06:19:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 23 Aug 2021 06:19:28 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 23 Aug 2021 06:19:24 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v2 2/4] ARM: dts: at91: sama7g5: add ram controllers Date: Mon, 23 Aug 2021 16:19:13 +0300 Message-ID: <20210823131915.23857-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210823131915.23857-1-claudiu.beznea@microchip.com> References: <20210823131915.23857-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add RAM and RAMC PHY controllers. These are necessary for platform specific power management code. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/sama7g5.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index cc6be6db7b80..ecabab4343b6 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -515,6 +515,18 @@ spi11: spi@400 { }; }; + uddrc: uddrc@e3800000 { + compatible = "microchip,sama7g5-uddrc"; + reg = <0xe3800000 0x4000>; + status = "okay"; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7g5-ddr3phy"; + reg = <0xe3804000 0x1000>; + status = "okay"; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; From patchwork Mon Aug 23 13:19:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 501603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9FE6C4338F for ; Mon, 23 Aug 2021 13:19:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AB7426124D for ; Mon, 23 Aug 2021 13:19:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237405AbhHWNUV (ORCPT ); Mon, 23 Aug 2021 09:20:21 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:3607 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237413AbhHWNUS (ORCPT ); Mon, 23 Aug 2021 09:20:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1629724776; x=1661260776; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hXKewkY3I5EwIJrxw8uwLa2pmaIf9I3+13mak8dkkWs=; b=Tv7SWmVStK5RaLXp+VJMCZhEfmFGTWFn2MnWoYDDV9W7dAeRTM/T2rjT FwKGarnZeSjFmqyXIRAHNlhG+3LnffCcBY/riaAaxEC7E4cKUxHzcWBKA 8ius8Yr6mNqSEJ0IRaNckkNuEg15B10IsW78mQ+mCkBK24PwKvkxDvwU7 d/7BASre+mM3GVaHJOST+L3jDJ6bZo/XYx0luJjqo1Un8D9Y6a0GhkUvT CGGUu9TpCzM2N0djNybSxQgav5zMHMtx3zhB3UznhCL5hbRtO80d3CiMP W+gsgi5OmTXF6r26BcvY/KiNesp6hGZo8Wp4PiM9DzHAW5Jl9w3HzhMVc Q==; IronPort-SDR: LHPG1INUjLfWYeFnBcqoM/60j6oFKLYLCY7cCF2ay5xroGu03OZ5bRfAVXbi9qIz62cc7df8i8 TUAiyh/shREtrZEqK3xSAVjKnaXqBo/ffiKRqHjZG4J3m70aJHZvQSIuinUiS6aCkFb3tmk2mm g0aZtsjIR+njEZNHowVHDgvkY5/gauY27TUVVr+JYI18w45XkHHUYfNTrdq/OuecObtMrMR0i0 AWqOLBCjCm4aQ24XoDDwCOcRQjxpvr+5+lFjPD6PQMgGGwjftAkz8mJ7gcNCvMd1MmtQJA2Lfx QT94oaXm7no3u2WrBBCTTmkV X-IronPort-AV: E=Sophos;i="5.84,344,1620716400"; d="scan'208";a="126756936" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Aug 2021 06:19:35 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 23 Aug 2021 06:19:35 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 23 Aug 2021 06:19:32 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v2 4/4] ARM: dts: at91: sama7g5: add shdwc node Date: Mon, 23 Aug 2021 16:19:15 +0300 Message-ID: <20210823131915.23857-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210823131915.23857-1-claudiu.beznea@microchip.com> References: <20210823131915.23857-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add shutdown controller node and enable it. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sama7g5ek.dts | 9 +++++++++ arch/arm/boot/dts/sama7g5.dtsi | 11 +++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 4cbed98cc2f4..8b13b031a167 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -634,6 +634,15 @@ &sdmmc2 { pinctrl-0 = <&pinctrl_sdmmc2_default>; }; +&shdwc { + atmel,shdwc-debouncer = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + &spdifrx { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spdifrx_default>; diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 3a4315ac0eb0..e50806cf7660 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -122,6 +122,17 @@ pmc: pmc@e0018000 { clock-names = "td_slck", "md_slck", "main_xtal"; }; + shdwc: shdwc@e001d010 { + compatible = "microchip,sama7g5-shdwc", "syscon"; + reg = <0xe001d010 0x10>; + clocks = <&clk32k 0>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + rtt: rtt@e001d020 { compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; reg = <0xe001d020 0x30>;