From patchwork Wed Aug 25 22:25:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 502974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5043C4320E for ; Wed, 25 Aug 2021 22:24:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A973C6109E for ; Wed, 25 Aug 2021 22:24:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232848AbhHYWZe (ORCPT ); Wed, 25 Aug 2021 18:25:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232444AbhHYWZc (ORCPT ); Wed, 25 Aug 2021 18:25:32 -0400 Received: from mail-oi1-x22b.google.com (mail-oi1-x22b.google.com [IPv6:2607:f8b0:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F334C0613C1 for ; Wed, 25 Aug 2021 15:24:46 -0700 (PDT) Received: by mail-oi1-x22b.google.com with SMTP id s20so1605996oiw.3 for ; Wed, 25 Aug 2021 15:24:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vXLLp5GIbOEgi1J75PRebsAuxo8nGrsWkSS0/ujVn1w=; b=lmAfSC2C4y4sGEBFjrDXuzJzhQOQyubDGp7PohABf7xAjOKBnEoY1LXs7EQtQ936LU K4gVPvR7wk3xiaRIbCF9TNFaSH7LOzwH37FtYfcNAEp5MbCcGtyJUQSoVXedi+y/xZQw EhIxcTEPMdcR6wYGjR/dhpUTZ/pC3+nkgIxwYRQNoOf45s17kbktLkIq0w24s0yYsJPv ZvusE/wXq7V0Y/ZGMOEUg94DN8e3Z+veiqQTJ2BHfGwHasOmkBiP0YZoOE9V7hCZhW5I DdMy8zGVug/mo3IfMj+L6vQi5eB9pGKvB+1ogeSDYXLSlytC03HEcr+UPZ4OvPOgNrMt DFHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vXLLp5GIbOEgi1J75PRebsAuxo8nGrsWkSS0/ujVn1w=; b=SCBn5QQJyDUNGl0f+7gf4iXADsJ+EUnXa9Kr7ASRc5d24M6imYzuPHHJa7gm7J5kxn 4rP8myuoq1MScHQpRVQaMVArnpPVT3wGRJ2ygk25Mcw464Qc6DTYrCPJGPbFovZ3YhIQ 8Mg4M8ONdcq4Q/J26LM4fBxv8CaH85oEp3eAN9nmT/UiWQiniea/SqWXvP1xEECmMig5 Nz6mNn3S1zaQDQ4LJFm7hHh2Wp52UlY5ETzS2KCQeu/R/DFOjQDidcj/fbeUvpiT8vEi Pt76YK8DNA3zGvSew8TmlEb/BZffpnjdkqrrBU/al9LY4/bRudRLFLd/l5pMImIYaDG0 Rvww== X-Gm-Message-State: AOAM530x/x/Jc9KInhMyVGZFGCPKWA2yxwIqDurtETDXSUACr313AB63 7uGYY3iSvXNYttzszgH2GcauvA== X-Google-Smtp-Source: ABdhPJwHRIt2gKLaM2qqqQhcQoev7y64yQvWWdsdrlXDJ/LIM9saCuxmamvlXDwtDy92YqCOvp+XPg== X-Received: by 2002:a05:6808:1886:: with SMTP id bi6mr218519oib.138.1629930285445; Wed, 25 Aug 2021 15:24:45 -0700 (PDT) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id u19sm263721oiv.28.2021.08.25.15.24.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 15:24:44 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Abhinav Kumar Cc: Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 1/5] dt-bindings: msm/dp: Change reg definition Date: Wed, 25 Aug 2021 15:25:53 -0700 Message-Id: <20210825222557.1499104-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210825222557.1499104-1-bjorn.andersson@linaro.org> References: <20210825222557.1499104-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org reg was defined as one region covering the entire DP block, but the memory map is actually split in 4 regions and obviously the size of these regions differs between platforms. Switch the reg to require that all four regions are specified instead. It is expected that the implementation will handle existing DTBs, even though the schema defines the new layout. Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson --- Changes since v1: - Include the p1 region (although unused by the implementation for now) .../bindings/display/msm/dp-controller.yaml | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 64d8d9e5e47a..f915dc080cbc 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -19,7 +19,12 @@ properties: - qcom,sc7180-dp reg: - maxItems: 1 + items: + - description: ahb register block + - description: aux register block + - description: link register block + - description: p0 register block + - description: p1 register block interrupts: maxItems: 1 @@ -100,7 +105,11 @@ examples: displayport-controller@ae90000 { compatible = "qcom,sc7180-dp"; - reg = <0xae90000 0x1400>; + reg = <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0xc00>, + <0xae91000 0x400>, + <0xae91400 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, From patchwork Wed Aug 25 22:25:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 502320 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1022560jab; Wed, 25 Aug 2021 15:24:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwyCrsCigO4TzD/vz1HJKdnh4/jtuZ1rM6tooDnWDi8aacoTCXvtthwatFHNLWQMRwkMYEq X-Received: by 2002:a5d:818b:: with SMTP id u11mr553132ion.43.1629930296720; Wed, 25 Aug 2021 15:24:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629930296; cv=none; d=google.com; s=arc-20160816; b=Dntj/R4FN/opGTyp45d+QV6nZ6mZoYy7RvcIUA73RYfH89yh/1tZaUPD60EhCvfbGe vD34h9y6VwrLC44V098IJjXlWKXQ1S4pY9ptC/3jRYKW8SJtjsH6PDuioOweH5AFqcmg 4X0oiwknEc2zLfCBixtd7F8+WJ6L5UVEdZ4aBYe/pLuakR0DpZxKaoPPqcjPemY+Cdz2 Q/tY1IbrKafCSykTwrhqlikiz4KBAQ3ecpg5L8FIY8yo+VN1UbsQbm72bTFx0T1ysguo V/XAvxsWngb/jQeilFDy7KcOeyHMi5sXkLnaPdAfWSVKT5F+lWBxj2FR48HDkHGOe8SI gSRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=J4aVSShQAfZChFaza0fhmy7POKfSYqt3Cdubgt9SAys=; b=gdJB3ZB5Ea5+ZljqCFESWMG34pJN2vBMY6tprNOD1w+6t/lB5oZmMJIKNbUcd6vc41 lV0KHtglhJOcjsf4K/zW95G4pv671P0ic2NaX2i9kEiqqi/Pt/OSGDDBiU7fHN5V6WfZ Pk5XcZkaUCtiPCspqIdnD6oSEXCoWhJx2NWj9BuFObaZ4qbDnRILPx+MQ3uOK4GUi+UB mqkoRSZS+pQyV6A9LtzIlok4EtzGOWY00R+lZjoUx/AVPn2JWNGdkXRRT7oYp7bK3p+W nqH5D/R5tyw2WTAA8coqIE/E69fxPin5BBHT4P+B7JTMCQaYbU7oEOfaQoUYSqoaGcCF YZUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v3qNOwbS; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id u19sm263721oiv.28.2021.08.25.15.24.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 15:24:46 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Abhinav Kumar Cc: Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] drm/msm/dp: Use devres for ioremap() Date: Wed, 25 Aug 2021 15:25:54 -0700 Message-Id: <20210825222557.1499104-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210825222557.1499104-1-bjorn.andersson@linaro.org> References: <20210825222557.1499104-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The non-devres version of ioremap is used, which requires manual cleanup. But the code paths leading here is mixed with other devres users, so rely on this for ioremap as well to simplify the code. Reviewed-by: Abhinav Kumar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson --- Changes since v1: - Picked up R-bs drivers/gpu/drm/msm/dp/dp_parser.c | 29 ++++------------------------- 1 file changed, 4 insertions(+), 25 deletions(-) -- 2.29.2 diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 0519dd3ac3c3..c064ced78278 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -32,7 +32,7 @@ static int msm_dss_ioremap(struct platform_device *pdev, } io_data->len = (u32)resource_size(res); - io_data->base = ioremap(res->start, io_data->len); + io_data->base = devm_ioremap(&pdev->dev, res->start, io_data->len); if (!io_data->base) { DRM_ERROR("%pS->%s: ioremap failed\n", __builtin_return_address(0), __func__); @@ -42,22 +42,6 @@ static int msm_dss_ioremap(struct platform_device *pdev, return 0; } -static void msm_dss_iounmap(struct dss_io_data *io_data) -{ - if (io_data->base) { - iounmap(io_data->base); - io_data->base = NULL; - } - io_data->len = 0; -} - -static void dp_parser_unmap_io_resources(struct dp_parser *parser) -{ - struct dp_io *io = &parser->io; - - msm_dss_iounmap(&io->dp_controller); -} - static int dp_parser_ctrl_res(struct dp_parser *parser) { int rc = 0; @@ -67,19 +51,14 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) rc = msm_dss_ioremap(pdev, &io->dp_controller); if (rc) { DRM_ERROR("unable to remap dp io resources, rc=%d\n", rc); - goto err; + return rc; } io->phy = devm_phy_get(&pdev->dev, "dp"); - if (IS_ERR(io->phy)) { - rc = PTR_ERR(io->phy); - goto err; - } + if (IS_ERR(io->phy)) + return PTR_ERR(io->phy); return 0; -err: - dp_parser_unmap_io_resources(parser); - return rc; } static int dp_parser_misc(struct dp_parser *parser) From patchwork Wed Aug 25 22:25:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 502319 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1022542jab; Wed, 25 Aug 2021 15:24:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMDY5vrxSViGfrngItvbLCS6IOfPO6upr4tmkNfSaN0XXpjgffL0sNv45klnF4fx8LkZyT X-Received: by 2002:a92:d790:: with SMTP id d16mr407529iln.147.1629930294333; Wed, 25 Aug 2021 15:24:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629930294; cv=none; d=google.com; s=arc-20160816; b=FIJ9mJzxLdwrxRgo2T2k/q+Zjd3rorzySHPtudvfhY9CyYxpcojCPSSlYQ+kfs8IlM 43udKn1qzvYnlXh9Y8JDHKk5Zs06KdiKcEMfKMJWNaHTWtIEtZsj3vGsLhIvfRZ+ofRu NGT6FpET5Y4iLEKuwrOIrxPGf3UsWxwXBpDYf4s2RU11LPQqCcfXPS5MR8IS/Bd3C1Dn MZU4lKRISXauFFy0qcvUamDN1rTWuak+faU5Xa8lLjEfZj27bBopWYhb9sqjjGKDVD6K V+4HwX5HRed+LPt2f4Qi7fsiCikILZMCyDvhowN23oxIkLWlJZg34dxzlcje3+k6T6FA oWsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wf37F7O7IL2IiPzK/k4sYEedZBRYlQXH7AwChdDZqEk=; b=eii3b8LW3xbQz8EXXTTt8LpfseSND1XyaLj7HRrs4ybbLRza+votVaDyEL4Im844/g PDLssd75z9rQ36WdxrFvkid5mtjeCPKVnWs1mVhACpAOlfBzFMblugw12LYcUQfbz6cW MtwckcTNg+MV9qP83ReGtAY6Y4ZbMITw2/lFARocaJxRVtw+Fa3x8m9Q5bjvHD5WAnFV uILQ1BF9jTZe1KkZ8jnD9BPWnSqATmEK61a9tXmnn/CPikIE7zpAFdcXemVO2Q9JNeNU vLbQMYX3+eddywVNhaN99KHw3xxqG+bq6W7tV+d6yHcwe1XtXg+G1CmnbzCuN97WurIb lFDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qKY0grhT; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id u19sm263721oiv.28.2021.08.25.15.24.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 15:24:47 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Abhinav Kumar Cc: Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] drm/msm/dp: Refactor ioremap wrapper Date: Wed, 25 Aug 2021 15:25:55 -0700 Message-Id: <20210825222557.1499104-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210825222557.1499104-1-bjorn.andersson@linaro.org> References: <20210825222557.1499104-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In order to deal with multiple memory ranges in the following commit change the ioremap wrapper to not poke directly into the dss_io_data struct. While at it, devm_ioremap_resource() already prints useful error messages on failure, so omit the unnecessary prints from the caller. Signed-off-by: Bjorn Andersson --- Changes since v1: - Dropped initialization of "res" - Fixed devm_ioremap() return value check - Dropped error prints (as devm_ioremap() already does that) drivers/gpu/drm/msm/dp/dp_parser.c | 30 ++++++++++-------------------- drivers/gpu/drm/msm/dp/dp_parser.h | 2 +- 2 files changed, 11 insertions(+), 21 deletions(-) -- 2.29.2 diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index c064ced78278..215065336268 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -19,40 +19,30 @@ static const struct dp_regulator_cfg sdm845_dp_reg_cfg = { }, }; -static int msm_dss_ioremap(struct platform_device *pdev, - struct dss_io_data *io_data) +static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len) { - struct resource *res = NULL; + struct resource *res; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + res = platform_get_resource(pdev, IORESOURCE_MEM, idx); if (!res) { DRM_ERROR("%pS->%s: msm_dss_get_res failed\n", __builtin_return_address(0), __func__); - return -ENODEV; + return ERR_PTR(-ENODEV); } - io_data->len = (u32)resource_size(res); - io_data->base = devm_ioremap(&pdev->dev, res->start, io_data->len); - if (!io_data->base) { - DRM_ERROR("%pS->%s: ioremap failed\n", - __builtin_return_address(0), __func__); - return -EIO; - } - - return 0; + *len = resource_size(res); + return devm_ioremap_resource(&pdev->dev, res); } static int dp_parser_ctrl_res(struct dp_parser *parser) { - int rc = 0; struct platform_device *pdev = parser->pdev; struct dp_io *io = &parser->io; + struct dss_io_data *dss = &io->dp_controller; - rc = msm_dss_ioremap(pdev, &io->dp_controller); - if (rc) { - DRM_ERROR("unable to remap dp io resources, rc=%d\n", rc); - return rc; - } + dss->base = dp_ioremap(pdev, 0, &dss->len); + if (IS_ERR(dss->base)) + return PTR_ERR(dss->base); io->phy = devm_phy_get(&pdev->dev, "dp"); if (IS_ERR(io->phy)) diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 34b49628bbaf..dc62e70b1640 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -26,7 +26,7 @@ enum dp_pm_type { }; struct dss_io_data { - u32 len; + size_t len; void __iomem *base; }; From patchwork Wed Aug 25 22:25:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 502318 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1022533jab; Wed, 25 Aug 2021 15:24:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz0v8c6aJAkYqL1p9dhc7IyvW2pD7f7uFpDka8OvzXPC/f01c22JahoggPKwPRx4TmEDgzg X-Received: by 2002:a02:9695:: with SMTP id w21mr632559jai.64.1629930293548; Wed, 25 Aug 2021 15:24:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629930293; cv=none; d=google.com; s=arc-20160816; b=IX3TV+WRxMp3Gu5KgxUqswQ0VQn7PSg3Mzqua3vI28+xT2GmcyKKxEeiT4A9bHkYeT oNBoockN10F6S348QaDV4dJRvrbCxWG7R+3I0lh7ab6aFhA8ms46vucIb+uAD8DmPZe7 1io0IpGI7AiGJw8kccdVOeJjMdGHtfdscEqv39lL8PWU/xcWhK3UVvH0s1gn6X4ioy4T SDw8Wz30VkHZJqtf87P0Dg7H/7UR0KzS2Ga4K39h0Dt5MFNCx/oO8ApKNI79OKzr9vVt jT/aNRW3LXsj4GESrWGVIPf7wNp34hkVvtzjILae63m5Mh9fz9L3zRpGzvzEsbqsHbZw pxVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sbJDvJ7/k7vSzJlT/cQdUuPB8pNiUCSXkLRC0Zxkhq4=; b=j3brVQBleezruqnO7EpwOwMBSiTt3Fp7v5sscv7i+uRFV9ESN8ZeOBHJmKXWntGtEZ kwBxJZKmSOX75W+g321IEhgyDy1qyBEw6gPaGslRIg6bOeL+/wIhcRGvV/FrEP4Y79z6 /q3Z/UtzVjw3efePHJUAmvY/kDEGO/r495kDiZJ6ngb02/xFHBFVTqa4D5Uq7Sx7V0kz ucK9KygAhblg3ThqG7Wi70jYMJAMQUPYAzvkr5bEYtvl+pEzHJcyds/qq4ANz1t2IfG/ W5JaX2tVBPsdXl4pmvV1NeOS6leR0WrQelgksT1HRXADF0v6E7RDBq9V6QsEBTk+e0TS jYgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gD03EoGJ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id u19sm263721oiv.28.2021.08.25.15.24.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 15:24:48 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Abhinav Kumar Cc: Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] drm/msm/dp: Store each subblock in the io region Date: Wed, 25 Aug 2021 15:25:56 -0700 Message-Id: <20210825222557.1499104-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210825222557.1499104-1-bjorn.andersson@linaro.org> References: <20210825222557.1499104-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Not all platforms has DP_P0 at offset 0x1000 from the beginning of the DP block. So split the dss_io_data memory region into a set of sub-regions, to make it possible in the next patch to specify each of the sub-regions individually. Signed-off-by: Bjorn Andersson --- Changes since v1: - Fixed nonsensical commit message - Introduced dss_io_region to group base and len drivers/gpu/drm/msm/dp/dp_catalog.c | 64 +++++++++-------------------- drivers/gpu/drm/msm/dp/dp_parser.c | 28 +++++++++++-- drivers/gpu/drm/msm/dp/dp_parser.h | 11 ++++- 3 files changed, 54 insertions(+), 49 deletions(-) -- 2.29.2 Reviewed-by: Stephen Boyd diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index cc2bb8295329..6ae9b29044b6 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -24,15 +24,6 @@ #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 #define DP_INTERRUPT_STATUS_MASK_SHIFT 2 -#define MSM_DP_CONTROLLER_AHB_OFFSET 0x0000 -#define MSM_DP_CONTROLLER_AHB_SIZE 0x0200 -#define MSM_DP_CONTROLLER_AUX_OFFSET 0x0200 -#define MSM_DP_CONTROLLER_AUX_SIZE 0x0200 -#define MSM_DP_CONTROLLER_LINK_OFFSET 0x0400 -#define MSM_DP_CONTROLLER_LINK_SIZE 0x0C00 -#define MSM_DP_CONTROLLER_P0_OFFSET 0x1000 -#define MSM_DP_CONTROLLER_P0_SIZE 0x0400 - #define DP_INTERRUPT_STATUS1 \ (DP_INTR_AUX_I2C_DONE| \ DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ @@ -66,82 +57,77 @@ void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *d { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + struct dss_io_data *dss = &catalog->io->dp_controller; - msm_disp_snapshot_add_block(disp_state, catalog->io->dp_controller.len, - catalog->io->dp_controller.base, "dp_ctrl"); + msm_disp_snapshot_add_block(disp_state, dss->ahb.len, dss->ahb.base, "dp_ahb"); + msm_disp_snapshot_add_block(disp_state, dss->aux.len, dss->aux.base, "dp_aux"); + msm_disp_snapshot_add_block(disp_state, dss->link.len, dss->link.base, "dp_link"); + msm_disp_snapshot_add_block(disp_state, dss->p0.len, dss->p0.base, "dp_p0"); } static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_AUX_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.aux.base + offset); } static inline void dp_write_aux(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_AUX_OFFSET; /* * To make sure aux reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.aux.base + offset); } static inline u32 dp_read_ahb(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_AHB_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.ahb.base + offset); } static inline void dp_write_ahb(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_AHB_OFFSET; /* * To make sure phy reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.ahb.base + offset); } static inline void dp_write_p0(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_P0_OFFSET; /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.p0.base + offset); } static inline u32 dp_read_p0(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_P0_OFFSET; /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.p0.base + offset); } static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_LINK_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.link.base + offset); } static inline void dp_write_link(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_LINK_OFFSET; /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.link.base + offset); } /* aux related catalog functions */ @@ -276,29 +262,21 @@ static void dump_regs(void __iomem *base, int len) void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) { - u32 offset, len; struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + struct dss_io_data *io = &catalog->io->dp_controller; pr_info("AHB regs\n"); - offset = MSM_DP_CONTROLLER_AHB_OFFSET; - len = MSM_DP_CONTROLLER_AHB_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->ahb.base, io->ahb.len); pr_info("AUXCLK regs\n"); - offset = MSM_DP_CONTROLLER_AUX_OFFSET; - len = MSM_DP_CONTROLLER_AUX_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->aux.base, io->aux.len); pr_info("LCLK regs\n"); - offset = MSM_DP_CONTROLLER_LINK_OFFSET; - len = MSM_DP_CONTROLLER_LINK_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->link.base, io->link.len); pr_info("P0CLK regs\n"); - offset = MSM_DP_CONTROLLER_P0_OFFSET; - len = MSM_DP_CONTROLLER_P0_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->p0.base, io->p0.len); } u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog) @@ -493,8 +471,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; /* Poll for mainlink ready status */ - ret = readx_poll_timeout(readl, catalog->io->dp_controller.base + - MSM_DP_CONTROLLER_LINK_OFFSET + + ret = readx_poll_timeout(readl, catalog->io->dp_controller.link.base + REG_DP_MAINLINK_READY, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -541,8 +518,7 @@ bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog) struct dp_catalog_private, dp_catalog); /* Poll for mainlink ready status */ - ret = readl_poll_timeout(catalog->io->dp_controller.base + - MSM_DP_CONTROLLER_LINK_OFFSET + + ret = readl_poll_timeout(catalog->io->dp_controller.link.base + REG_DP_MAINLINK_READY, data, data & DP_MAINLINK_READY_FOR_VIDEO, POLLING_SLEEP_US, POLLING_TIMEOUT_US); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 215065336268..4a7dad86159f 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -11,6 +11,15 @@ #include "dp_parser.h" #include "dp_reg.h" +#define DP_DEFAULT_AHB_OFFSET 0x0000 +#define DP_DEFAULT_AHB_SIZE 0x0200 +#define DP_DEFAULT_AUX_OFFSET 0x0200 +#define DP_DEFAULT_AUX_SIZE 0x0200 +#define DP_DEFAULT_LINK_OFFSET 0x0400 +#define DP_DEFAULT_LINK_SIZE 0x0C00 +#define DP_DEFAULT_P0_OFFSET 0x1000 +#define DP_DEFAULT_P0_SIZE 0x0400 + static const struct dp_regulator_cfg sdm845_dp_reg_cfg = { .num = 2, .regs = { @@ -40,9 +49,22 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) struct dp_io *io = &parser->io; struct dss_io_data *dss = &io->dp_controller; - dss->base = dp_ioremap(pdev, 0, &dss->len); - if (IS_ERR(dss->base)) - return PTR_ERR(dss->base); + dss->ahb.base = dp_ioremap(pdev, 0, &dss->ahb.len); + if (IS_ERR(dss->ahb.base)) + return PTR_ERR(dss->ahb.base); + + if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + DRM_ERROR("legacy memory region not large enough\n"); + return -EINVAL; + } + + dss->ahb.len = DP_DEFAULT_AHB_SIZE; + dss->aux.base = dss->ahb.base + DP_DEFAULT_AUX_OFFSET; + dss->aux.len = DP_DEFAULT_AUX_SIZE; + dss->link.base = dss->ahb.base + DP_DEFAULT_LINK_OFFSET; + dss->link.len = DP_DEFAULT_LINK_SIZE; + dss->p0.base = dss->ahb.base + DP_DEFAULT_P0_OFFSET; + dss->p0.len = DP_DEFAULT_P0_SIZE; io->phy = devm_phy_get(&pdev->dev, "dp"); if (IS_ERR(io->phy)) diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index dc62e70b1640..a95b05dbb11c 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -25,9 +25,16 @@ enum dp_pm_type { DP_MAX_PM }; -struct dss_io_data { - size_t len; +struct dss_io_region { void __iomem *base; + size_t len; +}; + +struct dss_io_data { + struct dss_io_region ahb; + struct dss_io_region aux; + struct dss_io_region link; + struct dss_io_region p0; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id u19sm263721oiv.28.2021.08.25.15.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 15:24:49 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Abhinav Kumar Cc: Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] drm/msm/dp: Allow sub-regions to be specified in DT Date: Wed, 25 Aug 2021 15:25:57 -0700 Message-Id: <20210825222557.1499104-6-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210825222557.1499104-1-bjorn.andersson@linaro.org> References: <20210825222557.1499104-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Not all platforms has P0 at an offset of 0x1000 from the base address, so add support for specifying each sub-region in DT. The code falls back to the predefined offsets in the case that only a single reg is specified, in order to support existing DT. Reviewed-by: Stephen Boyd Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson --- Changes since v1: - Reworked on top of changes in 4/5 drivers/gpu/drm/msm/dp/dp_parser.c | 49 +++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 11 deletions(-) -- 2.29.2 diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 4a7dad86159f..a5412ddade53 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -53,18 +53,45 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) if (IS_ERR(dss->ahb.base)) return PTR_ERR(dss->ahb.base); - if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { - DRM_ERROR("legacy memory region not large enough\n"); - return -EINVAL; - } + dss->aux.base = dp_ioremap(pdev, 1, &dss->aux.len); + if (IS_ERR(dss->aux.base)) { + /* + * The initial binding had a single reg, but in order to + * support variation in the sub-region sizes this was split. + * dp_ioremap() will fail with -ENODEV here if only a single + * reg is specified, so fill in the sub-region offsets and + * lengths based on this single region. + */ + if (PTR_ERR(dss->aux.base) == -ENODEV) { + if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + DRM_ERROR("legacy memory region not large enough\n"); + return -EINVAL; + } + + dss->ahb.len = DP_DEFAULT_AHB_SIZE; + dss->aux.base = dss->ahb.base + DP_DEFAULT_AUX_OFFSET; + dss->aux.len = DP_DEFAULT_AUX_SIZE; + dss->link.base = dss->ahb.base + DP_DEFAULT_LINK_OFFSET; + dss->link.len = DP_DEFAULT_LINK_SIZE; + dss->p0.base = dss->ahb.base + DP_DEFAULT_P0_OFFSET; + dss->p0.len = DP_DEFAULT_P0_SIZE; + } else { + DRM_ERROR("unable to remap aux region: %pe\n", dss->aux.base); + return PTR_ERR(dss->aux.base); + } + } else { + dss->link.base = dp_ioremap(pdev, 2, &dss->link.len); + if (IS_ERR(dss->link.base)) { + DRM_ERROR("unable to remap link region: %pe\n", dss->link.base); + return PTR_ERR(dss->link.base); + } - dss->ahb.len = DP_DEFAULT_AHB_SIZE; - dss->aux.base = dss->ahb.base + DP_DEFAULT_AUX_OFFSET; - dss->aux.len = DP_DEFAULT_AUX_SIZE; - dss->link.base = dss->ahb.base + DP_DEFAULT_LINK_OFFSET; - dss->link.len = DP_DEFAULT_LINK_SIZE; - dss->p0.base = dss->ahb.base + DP_DEFAULT_P0_OFFSET; - dss->p0.len = DP_DEFAULT_P0_SIZE; + dss->p0.base = dp_ioremap(pdev, 3, &dss->p0.len); + if (IS_ERR(dss->p0.base)) { + DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0.base); + return PTR_ERR(dss->p0.base); + } + } io->phy = devm_phy_get(&pdev->dev, "dp"); if (IS_ERR(io->phy))