From patchwork Tue Jan 24 08:57:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Feng X-Patchwork-Id: 92301 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1615151qgi; Tue, 24 Jan 2017 01:00:28 -0800 (PST) X-Received: by 10.99.123.3 with SMTP id w3mr37315118pgc.155.1485248428572; Tue, 24 Jan 2017 01:00:28 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q10si18434422pfc.45.2017.01.24.01.00.28; Tue, 24 Jan 2017 01:00:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751227AbdAXI7v (ORCPT + 25 others); Tue, 24 Jan 2017 03:59:51 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:34568 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751089AbdAXI7s (ORCPT ); Tue, 24 Jan 2017 03:59:48 -0500 Received: from 172.24.1.36 (EHLO SZXEML423-HUB.china.huawei.com) ([172.24.1.36]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DYG89007; Tue, 24 Jan 2017 16:57:41 +0800 (CST) Received: from vm163-62.huawei.com (10.184.163.62) by SZXEML423-HUB.china.huawei.com (10.82.67.154) with Microsoft SMTP Server id 14.3.235.1; Tue, 24 Jan 2017 16:57:30 +0800 From: Chen Feng To: , , , , , , , , CC: , , , , , Subject: [V3 1/3] document: dt: add binding for Hi3660 SoC Date: Tue, 24 Jan 2017 16:57:27 +0800 Message-ID: <1485248249-117383-1-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.184.163.62] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.58871707.009A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 14966ab7f2abfc4afa3e485631fa4113 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding for hisilicon Hi3660 SoC and HiKey960 Board. Signed-off-by: Chen Feng Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 7df79a7..6de2398 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -8,6 +8,10 @@ Hi6220 SoC Required root node properties: - compatible = "hisilicon,hi6220"; +Hi3660 SoC +Required root node properties: + - compatible = "hisilicon,hi3660"; + HiKey Board Required root node properties: - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; From patchwork Tue Jan 24 08:57:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Feng X-Patchwork-Id: 92298 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1614853qgi; Tue, 24 Jan 2017 00:59:37 -0800 (PST) X-Received: by 10.55.38.200 with SMTP id m69mr30141231qkm.100.1485248377299; Tue, 24 Jan 2017 00:59:37 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [65.50.211.133]) by mx.google.com with ESMTPS id m70si12702751qki.44.2017.01.24.00.59.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Jan 2017 00:59:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 65.50.211.133 as permitted sender) client-ip=65.50.211.133; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 65.50.211.133 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cVwwx-0005kA-2Z; Tue, 24 Jan 2017 08:59:35 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cVwwK-0004zU-BB for linux-arm-kernel@lists.infradead.org; Tue, 24 Jan 2017 08:59:04 +0000 Received: from 172.24.1.36 (EHLO SZXEML423-HUB.china.huawei.com) ([172.24.1.36]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DYG89009; Tue, 24 Jan 2017 16:57:42 +0800 (CST) Received: from vm163-62.huawei.com (10.184.163.62) by SZXEML423-HUB.china.huawei.com (10.82.67.154) with Microsoft SMTP Server id 14.3.235.1; Tue, 24 Jan 2017 16:57:31 +0800 From: Chen Feng To: , , , , , , , , Subject: [V3 2/3] arm64: dts: Add dts files for Hisilicon Hi3660 SoC Date: Tue, 24 Jan 2017 16:57:28 +0800 Message-ID: <1485248249-117383-2-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1485248249-117383-1-git-send-email-puck.chen@hisilicon.com> References: <1485248249-117383-1-git-send-email-puck.chen@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.184.163.62] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.5887170C.00ED, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 9c6b52f68de2accf38ff44d026f60f57 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170124_005859_478114_45F0EC25 X-CRM114-Status: GOOD ( 15.19 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] 0.0 T_SPF_HELO_TEMPERROR SPF: test of HELO record failed (temperror) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dan.zhao@hisilicon.com, frong.fan@hisilicon.com, xuyiping@hisilicon.com, saberlily.xia@hisilicon.com, oliver.fu@hisilicon.com, lulu.luxiaobo@hisilicon.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Add initial dtsi file to support Hisilicon Hi3660 SoC with support of Octal core CPUs in two clusters(4 * A53 & 4 * A73). Also add dts file to support HiKey960 development board which based on Hi3660 SoC. The output console is earlycon "earlycon=pl011,0xfdf05000". And the con_init uart5 with a fixed clock, which already configured at bootloader. When clock is available, the uart5 will be modified. Tested on HiKey960 Board. Signed-off-by: Chen Feng --- arch/arm64/boot/dts/hisilicon/Makefile | 1 + arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 35 +++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 160 ++++++++++++++++++++++ 3 files changed, 196 insertions(+) create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660.dtsi -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile index c8b8f80..c3a6c19 100644 --- a/arch/arm64/boot/dts/hisilicon/Makefile +++ b/arch/arm64/boot/dts/hisilicon/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts new file mode 100644 index 0000000..9ed9e68 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -0,0 +1,35 @@ +/* + * dts file for Hisilicon HiKey960 Development Board + * + * Copyright (C) 2016, Hisilicon Ltd. + * + */ + +/dts-v1/; + +#include "hi3660.dtsi" + +/ { + model = "HiKey960"; + compatible = "hisilicon,hi3660"; + + aliases { + serial5 = &uart5; /* console UART */ + }; + + chosen { + stdout-path = "serial5:115200n8"; + }; + + memory@0 { + device_type = "memory"; + /* rewrite this at bootloader */ + reg = <0x0 0x0 0x0 0x0>; + }; + + soc { + uart5: uart@fdf05000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi new file mode 100644 index 0000000..3983086 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -0,0 +1,160 @@ +/* + * dts file for Hisilicon Hi3660 SoC + * + * Copyright (C) 2016, Hisilicon Ltd. + */ + +#include + +/ { + compatible = "hisilicon,hi3660"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller@e82b0000 { + compatible = "arm,gic-400"; + reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ + <0x0 0xe82b2000 0 0x2000>, /* GICC */ + <0x0 0xe82b4000 0 0x2000>, /* GICH */ + <0x0 0xe82b6000 0 0x2000>; /* GICV */ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fixed_uart5: fixed_19_2M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "fixed:uart5"; + }; + + uart5: uart@fdf05000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf05000 0x0 0x1000>; + interrupts = ; + clocks = <&fixed_uart5 &fixed_uart5>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; From patchwork Tue Jan 24 08:57:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Feng X-Patchwork-Id: 92297 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1614807qgi; Tue, 24 Jan 2017 00:59:28 -0800 (PST) X-Received: by 10.84.233.206 with SMTP id m14mr50239930pln.104.1485248368316; Tue, 24 Jan 2017 00:59:28 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c8si18432026plk.79.2017.01.24.00.59.28; Tue, 24 Jan 2017 00:59:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751000AbdAXI7V (ORCPT + 25 others); Tue, 24 Jan 2017 03:59:21 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:34457 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750824AbdAXI7T (ORCPT ); Tue, 24 Jan 2017 03:59:19 -0500 Received: from 172.24.1.36 (EHLO SZXEML423-HUB.china.huawei.com) ([172.24.1.36]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DYG89008; Tue, 24 Jan 2017 16:57:41 +0800 (CST) Received: from vm163-62.huawei.com (10.184.163.62) by SZXEML423-HUB.china.huawei.com (10.82.67.154) with Microsoft SMTP Server id 14.3.235.1; Tue, 24 Jan 2017 16:57:32 +0800 From: Chen Feng To: , , , , , , , , CC: , , , , , Subject: [V3 3/3] dt-bindings: Add a support cpu type for cortex-a73 Date: Tue, 24 Jan 2017 16:57:29 +0800 Message-ID: <1485248249-117383-3-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1485248249-117383-1-git-send-email-puck.chen@hisilicon.com> References: <1485248249-117383-1-git-send-email-puck.chen@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.184.163.62] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.58871707.00BD, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ce61f4526c4ca692378c02ebbb2d58e3 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add arm cpu type cortex-a73 Signed-off-by: Chen Feng --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index a1bcfee..d748774 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -158,6 +158,7 @@ nodes to be present and contain the properties described below. "arm,cortex-a53" "arm,cortex-a57" "arm,cortex-a72" + "arm,cortex-a73" "arm,cortex-m0" "arm,cortex-m0+" "arm,cortex-m1"