From patchwork Mon Oct 15 13:07:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148830 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3776169lji; Mon, 15 Oct 2018 06:08:55 -0700 (PDT) X-Google-Smtp-Source: ACcGV60zFDG3dWTOmzrsxatfVSe/YJHkhVkXJMA2GsYgWMxruDw2dwQ7dvRoHqwJeTIMMZPNFlBX X-Received: by 2002:a62:4bd2:: with SMTP id d79-v6mr17507415pfj.38.1539608935625; Mon, 15 Oct 2018 06:08:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539608935; cv=none; d=google.com; s=arc-20160816; b=si38XLRd17iq/t7jI+YMPCkSBBVOl7Ny/X4rTLksQBLcNwFxnG6w1MX1GzpOtBAgqP OcUmnuxbswg5aV36I4bG13Y0HmDFy8XRY9pvDGjX3dNEn/MDKnwVtKqOSbsYPYGADUuN qCsBbUYFihY1G63TjPcJoSUUqeGbfvrnDkrDKFtNzOjBPoykSaKHbHXuq7yT+U8SwmFy vtT7ryWlgx5nVHsVQsYiBscXXcyoC/YtmCA978EmaSEzUx9emaxJSH+iFq2MKT4yId1h m/x7wBuTCvjfdr+qxqTE1DQRmOvMt7t798GhE86qAkhkvvkquSkIV9trghHtJrk6AvDR NrIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=iBGFjwERlyNXfssV0mhi5P70SxiWNRCvnKhKGvOqAU0=; b=Lce+7gtuOxSaQkd/FYkKjyN0nTbeuI+ZN9AhupoYgshs3KMeimfWeDPOCQTfIPnb9t nmYVK43M95VnHoSp9qkP9FVzJ+6iREaClbwKbLLQz5qVjR2CT9zSl+4F14YXjXw40y8o J1v5hvaAxy8lWDf7m70+XeA27F57MpBHDvf14cflqpEhr5o9C3eq+Bi3joERlr9XKFgd 6CZOXlE6JswkqJIh0h4hL6BUbgfIKuY1O+VNHOg248lZpEFevQ7GxnCOyHSjdwQOOKV1 lObXflku6DIFRQd+l7x75HiedDwWvLqSk8YlnGguVH/j2vtLUwncmAEJLP+CvPYPSmdq rtbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UaBdacgj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.08.49; Mon, 15 Oct 2018 06:08:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UaBdacgj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726614AbeJOUxm (ORCPT + 32 others); Mon, 15 Oct 2018 16:53:42 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:43352 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726422AbeJOUxl (ORCPT ); Mon, 15 Oct 2018 16:53:41 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD82O4089099; Mon, 15 Oct 2018 08:08:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608882; bh=iBGFjwERlyNXfssV0mhi5P70SxiWNRCvnKhKGvOqAU0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UaBdacgj9aso7wuuExr7YoxQcc93EjRbftDWxGdVz7TZQsDC/wrEkXveIVTYVPQ6J M4eyoReIDjhWqdtry7j5Ce1EsUab6SwVLB415Q/+H/vTMSw9Il7XGfM2AmY1hTA47N qu8pVAPQVfzGUoDkafxiTGgpWYgkmKuwoDhlZ4P4= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD8211010630; Mon, 15 Oct 2018 08:08:02 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:08:02 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:08:02 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tL4009433; Mon, 15 Oct 2018 08:07:59 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 01/19] PCI: keystone: Use quirk to limit MRRS for K2G Date: Mon, 15 Oct 2018 18:37:03 +0530 Message-ID: <20181015130721.5535-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCI controller in K2G also has a limitation that memory read request size (MRRS) must not exceed 256 bytes. Use the quirk to limit MRRS (added for K2HK, K2L and K2E) for K2G as well. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e88bd221fffe..7d43e10a03b0 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -36,6 +36,7 @@ #define PCIE_RC_K2HK 0xb008 #define PCIE_RC_K2E 0xb009 #define PCIE_RC_K2L 0xb00a +#define PCIE_RC_K2G 0xb00b #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) @@ -50,6 +51,8 @@ static void quirk_limit_mrrs(struct pci_dev *dev) .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, { 0, }, }; From patchwork Mon Oct 15 13:07:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148832 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3776423lji; Mon, 15 Oct 2018 06:09:07 -0700 (PDT) X-Google-Smtp-Source: ACcGV632DNL32sGjpiQsUbvoZIhkkucrVZ31IiOFXREw6/LqwZEf3JmztnMKe9vNBiK1a5+2b0Vg X-Received: by 2002:a62:8490:: with SMTP id k138-v6mr17541545pfd.177.1539608947361; Mon, 15 Oct 2018 06:09:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539608947; cv=none; d=google.com; s=arc-20160816; b=BqUyVjc1C8OH3aJFfuaNgbT51SOm9ayByvK0uHwdDdJ7I+dm6uv/2w/dX+FJYJJoAj Kuy1hdIyruiws0qL+lzGpvkXb2feLUX2zQa8QyAfaEoO0e3Fm2qoUnLURuRwoVBptCV9 6D0yUDG6wxZVWkdXbz4BabCCjk3wZ41f+e+BcYwcPiDmXnSotLWQDFRWARdsEGsbWcaA 9ws4S/76J92uMqYKAZB0nGGnvxIGFbzSjRJwLreUmquHVvFDIFP5jLxg2mSDNNV4Fh2r JFeuSVuVOKDecY9zSP+Ms5nJ6w3RGZMj4MOr0ysQD/BUdpHE4wpFUUP/9KWRlYp0Ynq5 aC8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=CywUeyvOfH1tI2pu+soQCfVILjgvnQbtM9JU52QtGcs=; b=cQaBr/MvhSRvOXPBQOqvyf70YbAvmWSX3GuQgRr+WfujtzVb89+MZePEOxdqjP88EW ZORpAuw30Lfk5feoPYoPA9EPL2d/uDkHrTaOtqQ9CzoBgZYu54rRHYm5BoM+x9Obw9H4 9OnC4sQpf/ZS2Lczd+hcRACEuuxRd0pGlAYX5UObEoA684819366iL/pdEVU2yjtSAgW +27/JshTuMdPybbvxKpZS6HuiJjWewFQW+tfhoB3ISgEuyunn+1mcEW/a5v+/HmCa2u9 eUXbe2KTDgBa29trbcUxkFpu4UV7bGd9gx6VUw3ztoNvFYPigQODBnz6H1chTY4O/TTZ gQPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QD9fPqYF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.09.01; Mon, 15 Oct 2018 06:09:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QD9fPqYF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726690AbeJOUxr (ORCPT + 32 others); Mon, 15 Oct 2018 16:53:47 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:56446 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726524AbeJOUxp (ORCPT ); Mon, 15 Oct 2018 16:53:45 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD86jG085901; Mon, 15 Oct 2018 08:08:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608886; bh=CywUeyvOfH1tI2pu+soQCfVILjgvnQbtM9JU52QtGcs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QD9fPqYFdf/kn6F2Qy4oaWjmRp11QPZiuZBdts3vH89PWQDat1S8dp6Z0GhRjoajd cLISb3o5CvsclZTTBNL6fRb/kc+S/rcYVzjH63tbwQRwPDrioWG7aCT88ktMBfYjzd p+n084POcX58Smj9Aw1BRmBtKB8iBcGclGwRfhmw= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD86ps010927; Mon, 15 Oct 2018 08:08:06 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:08:05 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:08:06 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tL5009433; Mon, 15 Oct 2018 08:08:02 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 02/19] PCI: keystone: Use quirk to set MRRS for PCI host bridge Date: Mon, 15 Oct 2018 18:37:04 +0530 Message-ID: <20181015130721.5535-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reuse the already existing quirk to set MRRS for PCI host bridge instead of explicitly setting MRRS in ks_pcie_host_init. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 37 +++++++++-------------- 1 file changed, 15 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 7d43e10a03b0..5d9c5d199ada 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -43,7 +43,7 @@ static void quirk_limit_mrrs(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; - struct pci_dev *bridge = bus->self; + struct pci_dev *bridge; static const struct pci_device_id rc_pci_devids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, @@ -57,7 +57,7 @@ static void quirk_limit_mrrs(struct pci_dev *dev) }; if (pci_is_root_bus(bus)) - return; + bridge = dev; /* look for the host bridge */ while (!pci_is_root_bus(bus)) { @@ -65,18 +65,19 @@ static void quirk_limit_mrrs(struct pci_dev *dev) bus = bus->parent; } - if (bridge) { - /* - * Keystone PCI controller has a h/w limitation of - * 256 bytes maximum read request size. It can't handle - * anything higher than this. So force this limit on - * all downstream devices. - */ - if (pci_match_id(rc_pci_devids, bridge)) { - if (pcie_get_readrq(dev) > 256) { - dev_info(&dev->dev, "limiting MRRS to 256\n"); - pcie_set_readrq(dev, 256); - } + if (!bridge) + return; + + /* + * Keystone PCI controller has a h/w limitation of + * 256 bytes maximum read request size. It can't handle + * anything higher than this. So force this limit on + * all downstream devices. + */ + if (pci_match_id(rc_pci_devids, bridge)) { + if (pcie_get_readrq(dev) > 256) { + dev_info(&dev->dev, "limiting MRRS to 256\n"); + pcie_set_readrq(dev, 256); } } } @@ -264,7 +265,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - u32 val; ks_pcie_establish_link(ks_pcie); ks_dw_pcie_setup_rc_app_regs(ks_pcie); @@ -275,13 +275,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) /* update the Vendor ID */ writew(ks_pcie->device_id, pci->dbi_base + PCI_DEVICE_ID); - /* update the DEV_STAT_CTRL to publish right mrrs */ - val = readl(pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); - val &= ~PCI_EXP_DEVCTL_READRQ; - /* set the mrrs to 256 bytes */ - val |= BIT(12); - writel(val, pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); - /* * PCIe access errors that result into OCP errors are caught by ARM as * "External aborts" From patchwork Mon Oct 15 13:07:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148833 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3776544lji; Mon, 15 Oct 2018 06:09:13 -0700 (PDT) X-Google-Smtp-Source: ACcGV61KoEcQuMXccjfE4gnTyYzO4ILXtfAzjvZTliNVvBPBBb7oegmdsIIVjsQuWxwl7C57w8b1 X-Received: by 2002:a17:902:9895:: with SMTP id s21-v6mr5073161plp.102.1539608953207; Mon, 15 Oct 2018 06:09:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539608953; cv=none; d=google.com; s=arc-20160816; b=xq78f6wYoaJbVMj7NQvsUPFpVegTYmdJh4IIW+R2ZGcVq7IRKzNRCt7aTukQToBlbI FYmBUxsLTmu1w7u7nZcuE6iXtcumAu/xhT98z1PKZ2X0bJ3nMkYWE5nTAnMuPhKUql1S MNUuEM4DVps90ujRTT6PpR3E9uJQo84NbAsmp2Mq+L9feLckH8cOao+YvTVvGMKIk3LD hvm703rF/VpWfvqXn35vTyImVehHG1VJC1AFqHo0MIbFgikRIatvw1nDeNC6TlJkLwc9 YGxmDU9D/Tye4n9VWeSntZVQ827MvF9StoSPelw++bqtdkpPqKT5RyzQHdr+wjOL3t/t rGVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=gQ0+pQEKb3K+sriSc3X3V9ettXr93wDRpE/j2uyHhZs=; b=U7XEqEcS+pj+I1udAmUaD2vRuUFdnEJHniqEoHhUP67BNsRVZ9Fq21WfdspaTIiYDV 3G+CMxRl/QQKOXXFSw/y8WBtAZSrUqCuuOfFogmTbBSXA0eUqDkrl+ZMoYyCz7TgxZVJ zNJ0L1XDJZ64Oub1nri6nC9s4rVLeAHDdaqJ6xW9fsm67Pryrd51EqjHc6XmbZGzCPSl n8BhtQKxFzhyT179JNIQgRHHwi7nSmaUElGr06JAml7PjpuLMmQsVPZNuCCJiMGcVEvP dQYdGeWlfd+dWXZLMT7EdlfyuDIMifjCbnR0fSe15dTW4YcMrbfg/CiJHYKRmbWyy0uq Cf4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FEPjW3Ua; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.09.07; Mon, 15 Oct 2018 06:09:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FEPjW3Ua; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726719AbeJOUxt (ORCPT + 32 others); Mon, 15 Oct 2018 16:53:49 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:38760 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726524AbeJOUxs (ORCPT ); Mon, 15 Oct 2018 16:53:48 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD89L6119664; Mon, 15 Oct 2018 08:08:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608889; bh=gQ0+pQEKb3K+sriSc3X3V9ettXr93wDRpE/j2uyHhZs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FEPjW3UaTJnbAFq4v0kErrUsBLCfKdxNXgEUEYgkbUigy9mRJ4l3uNIlbE8O6d6r5 nPSugZ83x+IwmAwxtNaJm+mlqjJH62CCvpSGjDqN8R7eP84tO9R/AbBuUQpF6p60Xk ZGSeEYSHiPakoSJ2o3HCb/KLGGRt6PMUKybdCInw= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD89OW032597; Mon, 15 Oct 2018 08:08:09 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:08:09 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:08:09 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tL6009433; Mon, 15 Oct 2018 08:08:06 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 03/19] PCI: keystone: Move dw_pcie_setup_rc out of ks_pcie_establish_link() Date: Mon, 15 Oct 2018 18:37:05 +0530 Message-ID: <20181015130721.5535-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Move dw_pcie_setup_rc out of ks_pcie_establish_link() so that ks_pcie_establish_link can be used only to start the link. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 5d9c5d199ada..afb948372077 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -86,12 +86,9 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs); static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) { struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; struct device *dev = pci->dev; unsigned int retries; - dw_pcie_setup_rc(pp); - if (dw_pcie_link_up(pci)) { dev_info(dev, "Link already up\n"); return 0; @@ -266,6 +263,8 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + dw_pcie_setup_rc(pp); + ks_pcie_establish_link(ks_pcie); ks_dw_pcie_setup_rc_app_regs(ks_pcie); ks_pcie_setup_interrupts(ks_pcie); From patchwork Mon Oct 15 13:07:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148837 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3778554lji; Mon, 15 Oct 2018 06:10:44 -0700 (PDT) X-Google-Smtp-Source: ACcGV61SH84jx66I9I280XbrWV2haeb2JQyTmMje5VfF42K3HXBIs7DH+6hxJudXsm7FJJoyj5q0 X-Received: by 2002:a65:66c9:: with SMTP id c9-v6mr16047883pgw.55.1539609043959; Mon, 15 Oct 2018 06:10:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539609043; cv=none; d=google.com; s=arc-20160816; b=udMQFq2NJag65Sam/IBOZrrpnUnHrMNpIJM7Q7byyQ0Gl9YfW7MaEXuCKoh+Qy3JRo 2/6Vz0QROBmk1ld+pvTE1FIXfMg+ecL4tlgdO91/ofNY3lvrqzkCuwitAJDAME0I4Grk 4x4C81NqRmyhUMw72kWsWF79U/5qODF2R+nTqzyFogvB5VleyHK1S1IoYelKFvJjqLOk tZ8k/RUUPdI4uNOquQPvxKtAGmjroqC2AaZ0AuYa1zYmqQRRze+90nX6hJHn69ye4faz tNV3eNRbCmo+IiWNUpcUbPD1EXHjwUgbEj8YSS6/wlNqS8yoq1WeQ7Zq4ROOBsGNnCq9 QFjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=3AdF0VMpgtkV9yWrrnXvabWcf4Spt+07w4PmTvQYyH8=; b=zIHUw0IwTz54mYXhgOjwPNq/+QeIfE96N2Ao9dcGF2VKRTgIR319pqQjQYCS/37w41 p58JlHecv7QwQoXGe4cGqWRkU7qRMzxpy8tWiJtZtcDve+dsYZJRipyjcs/j6XtWCSkF P2v0AMVQ6Ako7ZpZZF8k3iFWmXoi7gTxuGeclT+Xbw74/T09cBjvhtqOeYHoQTIGaQzX F2Ifn551ADZZr8+FeN9PxULgGHlDJ0J+SRlYf2munMSOGNtMDZmZkuRfj2BL3e7FDDQ5 05Tzc5iw5hSrPYQgpvXB2ljRzUkmHb1NxFxKxbbUDl6yJtmjnlSbppCFMPsaRiaJOeRQ KKtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mSEePOxL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.10.35; Mon, 15 Oct 2018 06:10:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mSEePOxL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726915AbeJOUy2 (ORCPT + 32 others); Mon, 15 Oct 2018 16:54:28 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:38748 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726620AbeJOUxo (ORCPT ); Mon, 15 Oct 2018 16:53:44 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD8C1l119730; Mon, 15 Oct 2018 08:08:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608892; bh=3AdF0VMpgtkV9yWrrnXvabWcf4Spt+07w4PmTvQYyH8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mSEePOxLDDPeC5VLFMwIzaewWuZBK7ZbIPNBbCQvFj1hWXTySTLxWaZJTHptRro3B DAKROCH86labCFOGWPTztonauFU9LsAWGrI6rg+A6TkanNsIOqgDEjsDpmCtZP16rQ pp3jSDa3TdXi/5Av/nkwUXAI7/2t4GP928ez1WbI= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD8C3N032668; Mon, 15 Oct 2018 08:08:12 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:08:12 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:08:12 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tL7009433; Mon, 15 Oct 2018 08:08:09 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 04/19] PCI: keystone: Do not initiate link training multiple times Date: Mon, 15 Oct 2018 18:37:06 +0530 Message-ID: <20181015130721.5535-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit 886bc5ceb5cc3ad4b219502d72 ("PCI: designware: Add generic dw_pcie_wait_for_link()") while adding a generic dw_pcie_wait_for_link() performed a special handling (initiate link training multiple times) for keystone which is not required. This also resulted in unncessarily waiting for more time to establish the link even when no PCI device is connected. Remove it and make it look similar to other dwc based PCIe drivers. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index afb948372077..aa7e706fc37d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -87,19 +87,17 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) { struct dw_pcie *pci = ks_pcie->pci; struct device *dev = pci->dev; - unsigned int retries; if (dw_pcie_link_up(pci)) { dev_info(dev, "Link already up\n"); return 0; } + ks_dw_pcie_initiate_link_train(ks_pcie); + /* check if the link is up or not */ - for (retries = 0; retries < 5; retries++) { - ks_dw_pcie_initiate_link_train(ks_pcie); - if (!dw_pcie_wait_for_link(pci)) - return 0; - } + if (!dw_pcie_wait_for_link(pci)) + return 0; dev_err(dev, "phy link never came up\n"); return -ETIMEDOUT; From patchwork Mon Oct 15 13:07:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148831 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3776268lji; Mon, 15 Oct 2018 06:09:01 -0700 (PDT) X-Google-Smtp-Source: ACcGV61CmtBJPRVLaq/2jLfucJLhcLe0c0WuTP4k5l9ncUSJKQNBcdOxrjyvt3qNA6tioNu0mm4M X-Received: by 2002:a62:da1a:: with SMTP id c26-v6mr6415718pfh.52.1539608941313; Mon, 15 Oct 2018 06:09:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539608941; cv=none; d=google.com; s=arc-20160816; b=1LNRP7uiTem3xOrGd4/33/Vvrfn4yEgd08p2rZVcgQMsR2HeQDiV893Kgmb2Qdo0GE SuCZuIYOVn09Bs3qtAPaJKCMcG+Rnzls+xXRa3nNCvbmJIXqddXjoC831eI7BbyweWw6 or2U9LLUUzN1WxSY0buW18R/jD6fFM2cv7eCl4k5sBP0ZwdwUJqxkINmR6B1kZvohLPu m9/pUORaM2fQ0M+wkmAWD/eaKKAhLWk4SjKJrtWhX8kf5kHPTbV+3MHaOJJSqXaNw7qq oI8LzQ4j/KNRl4wdldrW0R4Ekv6+4kXHyq/ISXn1u6CvOpLE+RSDgSi0dQUsk1mIOjzN Fjfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=NL93FqjXfL5GmS7Q7CEcO9WJ0fDK7IYqMoegnb1ILGg=; b=xDuAWVWrKuslWd37Y+r2CpY3Pm2zayil/DCker1tnxKxJWMAyP96MIcw+TSWtU322Q h5PFSNer0qY88gWXklWD3cFPdPwZc1RA/Uyu3UJYB53Yj9q0IQarZiq9RVViVWlh5Jzc 6Zy9F4E2w1EAtiJ7eNkXD1jKAA0h4kTCqrGa/r3OjV6wATilhloVuwHCFqAO2hcI8oa3 5AbcFq9guWNtzeAymdMnAEdInG77jtGOsvKsNpbxXHpZdgO6kUUy32Wn9ZmuabGAFX94 LzgxbIaMcVPj0/YOPdQxGJ0vWmwn036aUX/snROCtr7nRQ9+0fkkrPw6MU7GR9liefZ8 +yyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gLTV3u5u; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.08.55; Mon, 15 Oct 2018 06:09:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gLTV3u5u; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726651AbeJOUxp (ORCPT + 32 others); Mon, 15 Oct 2018 16:53:45 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:56444 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726422AbeJOUxo (ORCPT ); Mon, 15 Oct 2018 16:53:44 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD8G58085920; Mon, 15 Oct 2018 08:08:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608896; bh=NL93FqjXfL5GmS7Q7CEcO9WJ0fDK7IYqMoegnb1ILGg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gLTV3u5uN8lkXG0w06Dtnl0qVXQP7u1WhscTReLWNkFlXqp/NRw6zeWdRYdQwgCu/ 7zyb5EowfqgM2dEJ3N5xbwgoMAkvjAMXnq1a/vViluyAB4HURbnXmffyb7Jux+APfs GDFP59n40pqX+/FS3rIW2ljqLtSrr9hGnIyFLKmI= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD8Gw1032707; Mon, 15 Oct 2018 08:08:16 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:08:16 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:08:16 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tL8009433; Mon, 15 Oct 2018 08:08:12 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 05/19] PCI: keystone: Remove unused argument from ks_dw_pcie_host_init() Date: Mon, 15 Oct 2018 18:37:07 +0530 Message-ID: <20181015130721.5535-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Remove unused "msi_intc_np" argument from ks_dw_pcie_host_init(). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone-dw.c | 3 +-- drivers/pci/controller/dwc/pci-keystone.c | 2 +- drivers/pci/controller/dwc/pci-keystone.h | 3 +-- 3 files changed, 3 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone-dw.c b/drivers/pci/controller/dwc/pci-keystone-dw.c index 0682213328e9..4bd6c6e2b177 100644 --- a/drivers/pci/controller/dwc/pci-keystone-dw.c +++ b/drivers/pci/controller/dwc/pci-keystone-dw.c @@ -439,8 +439,7 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) * and call dw_pcie_v3_65_host_init() API to initialize the Keystone * PCI host controller. */ -int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie, - struct device_node *msi_intc_np) +int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie) { struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index aa7e706fc37d..f87ade2de711 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -341,7 +341,7 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, } pp->ops = &keystone_pcie_host_ops; - ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np); + ret = ks_dw_pcie_host_init(ks_pcie); if (ret) { dev_err(dev, "failed to initialize host\n"); return ret; diff --git a/drivers/pci/controller/dwc/pci-keystone.h b/drivers/pci/controller/dwc/pci-keystone.h index 8a13da391543..4eacc263f157 100644 --- a/drivers/pci/controller/dwc/pci-keystone.h +++ b/drivers/pci/controller/dwc/pci-keystone.h @@ -41,8 +41,7 @@ void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie); void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset); void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie); irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie); -int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie, - struct device_node *msi_intc_np); +int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie); int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, From patchwork Mon Oct 15 13:07:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148835 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3777475lji; Mon, 15 Oct 2018 06:09:56 -0700 (PDT) X-Google-Smtp-Source: ACcGV63M2jLy33dc8SfDxgby7sUv53mX7SvHWlAbYdpxy6Yl6xCBWqB8vU1bEGG03XZYgUKUFQ3E X-Received: by 2002:a62:174e:: with SMTP id 75-v6mr9302756pfx.117.1539608996504; Mon, 15 Oct 2018 06:09:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539608996; cv=none; d=google.com; s=arc-20160816; b=xign7Oz5phydy/sapooZmlfbRK7kbJl1TKJH9/8xFSv2cFbJAHEmbjI4hkZ6mcEY7t R7LIwR1mrB7BdqJ/7hW5373OzYNVcZoZM96mNdV9lrAIKh87PTHTSSY3o9v9hzNaBFeh rWhpc2wmGCT+e+H2FYQlDNneCkmV1Vm+pjVVACinCaUV+E9OhQs/5sCpwK+cpG06+YgC FjlnriRYv3p7r4It2/+s0ibDcZgyZ1W/GWhB5FvZaVYKn4YFC+Jz3lHVM98x/UBaVjUb wWjdqMcnQJQcHAlNsE05FYPO3pLZ0jXHnLVQ6sELkiG+DTQ1jRsHAwf0nmMzlpip69Eu 6huw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=A3B7m156w4JW4GKL6NESpqJCfKj0ubYIPGRpxQW6oQM=; b=Fcxl74auPxvKIPO2Ts2su/GSsr6MWc46vIl8hNMiPmY4wesgzBBzKFpFI6K8KX7SFU n/KFzfdwIkDbYC0fnqj7gLN+iQxYRp0jGaPdpvSBKz/JV+P0xWwAgfY1d7X2zQcYFohU uTaQ8NuLiSK42Gdsab32HHyEAOf1uinwDK4Hl7hGKAWBJPiuDD7b1HjKKPrmYxBB/hnu ZN6PocuJAEZMo6+UXOuw1ubMvKHZpHj5D80KZWjcRuxm9PK1HagrzadOV4WqkqccnT9H /SR7aL2jM9dE5XfYWWjj8DphTf30CufpOF56LpnX9LvYqwNuzwB1DksB9i5ers/pbtvz r2zA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=puozyviQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.09.49; Mon, 15 Oct 2018 06:09:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=puozyviQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726856AbeJOUyJ (ORCPT + 32 others); Mon, 15 Oct 2018 16:54:09 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:47914 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726778AbeJOUyJ (ORCPT ); Mon, 15 Oct 2018 16:54:09 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD8NTT123740; Mon, 15 Oct 2018 08:08:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608903; bh=A3B7m156w4JW4GKL6NESpqJCfKj0ubYIPGRpxQW6oQM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=puozyviQ4k0vSYJ9tqikFas558vFH9fUqvdKWvCjcWr0HF//8j2MSjNU0bpKGKo8y 2kWGECN0UHY52rghRtspwwMdjfGf6+/g0dzW7zmcDAHrK9waK0RNlj8ixyNfJZtvFN qHScR5OU4IwTpJiD0ytv/gT/pvC4xkzlrieoRnDA= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD8NhD000397; Mon, 15 Oct 2018 08:08:23 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:08:22 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:08:22 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tLA009433; Mon, 15 Oct 2018 08:08:19 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 07/19] PCI: keystone: Remove redundant platform_set_drvdata Date: Mon, 15 Oct 2018 18:37:09 +0530 Message-ID: <20181015130721.5535-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Remove redundant platform_set_drvdata invocation in ks_pcie_probe(). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 2 -- 1 file changed, 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 337464d15775..926e345dc965 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -912,8 +912,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (ret) return ret; - platform_set_drvdata(pdev, ks_pcie); - ret = ks_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto fail_clk; From patchwork Mon Oct 15 13:07:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148838 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3778567lji; Mon, 15 Oct 2018 06:10:44 -0700 (PDT) X-Google-Smtp-Source: ACcGV60n4amXTbiqTF4773y9SZ027AunPh5eixBAQyVYyWp3zR/jtEHHG5m8F52/e2dKKLnl1LBF X-Received: by 2002:a17:902:70c4:: with SMTP id l4-v6mr16885029plt.194.1539609044321; Mon, 15 Oct 2018 06:10:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539609044; cv=none; d=google.com; s=arc-20160816; b=x2BoD/uLNJwoLXO2BW8QSSJSae22rjSsdJGj060/sNHy4lWpRvWYY7rYsR1Zte1w6d 1OQ45MJZK8PGA2ueFrnLlMWSKLgfybnQiraM2h9q4ItOEgiWhYgsH1o3d3mcGGLd3Kc/ sOlEj/yZafQF0YzDwTdqHA4bAFMU9NBulBQaCVdVL6Gszf9N+vSCq8Wvx4nBJoHLpCf+ 5XxjuSdx19Ym+COZrqP0lvIH0mTn/qZcaH/8SykNpzFoXcPoTWmC+0qrMsYgU0yVjrWm 7gNImpSr7fgRv/30KTPnL8yh5EZJLYS04rgHZnN2oW7nMyOa1FgH1vkTJHL1KfrlsTNw 34xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=aIWECn7gGDwTU+WA2PGT3h1/IWT5Yz9oSBMzs0OKbVQ=; b=bgzoUgaZLHgzT8YLba/QW24DqKjym3Ht0RMxp7aEjSdipo+rGNWHkFG18VF0eRyN5M AEAAYp+4tiLtaEE+T6IGTLe5dFlHJqqiJRpD/dYBDJc6/UiEnm0hbtOw1Ug7hDzutyJK UnO1+CGOHEkf+zzXonkP7L6KASkunM5D8gBQdAvfCqVZY2M0yiH72hbeUK9eWvn5nh5y xz0qpofsq0XvrEbW/DN5sYCezQPR0UuCldK/ugKDikxPFcLWdVJVYjKexf8uvNFhbxHh J2EP9DJtkcu+5EpbJpVaF/hppYULggmawdIexYNmZ1Lf97AqZPua29XqtuGIq2YE0Fgz I9Nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=N75uY8Yc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.10.44; Mon, 15 Oct 2018 06:10:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=N75uY8Yc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726937AbeJOUyc (ORCPT + 32 others); Mon, 15 Oct 2018 16:54:32 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:43440 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726918AbeJOUyb (ORCPT ); Mon, 15 Oct 2018 16:54:31 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD8Q0w089277; Mon, 15 Oct 2018 08:08:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608906; bh=aIWECn7gGDwTU+WA2PGT3h1/IWT5Yz9oSBMzs0OKbVQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=N75uY8YcMmtkRRAuvoTRkWME1O0NhMgCge6H2doI2lXyHUjMelrNsjbe2WXX7z8FA vg7u7Ekdia8qNhu0Zgccna+427Dtm2aAlaw1hp7c9b/B/cgXRcBo1zyeWoDmqF+WCL 9hdEuAdx7pNnxFT9lgffNlO60P8krxh/aqUaKFa8= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD8QjQ011485; Mon, 15 Oct 2018 08:08:26 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:08:25 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:08:25 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tLB009433; Mon, 15 Oct 2018 08:08:23 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 08/19] PCI: keystone: Use uniform function naming convention Date: Mon, 15 Oct 2018 18:37:10 +0530 Message-ID: <20181015130721.5535-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Some function names begin with ks_dw_pcie_* and some function names begin with ks_pcie_*. Modify it so that all function names begin with ks_pcie_*. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 221 +++++++++++----------- 1 file changed, 111 insertions(+), 110 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 926e345dc965..e2045b5d2af2 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -118,7 +118,7 @@ static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset, *bit_pos = offset >> 3; } -static phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp) +static phys_addr_t ks_pcie_get_msi_addr(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); @@ -126,17 +126,18 @@ static phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp) return ks_pcie->app.start + MSI_IRQ; } -static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset) +static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) { return readl(ks_pcie->va_app_base + offset); } -static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val) +static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, + u32 val) { writel(val, ks_pcie->va_app_base + offset); } -static void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) +static void ks_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) { struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; @@ -144,7 +145,7 @@ static void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) u32 pending, vector; int src, virq; - pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4)); + pending = ks_pcie_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4)); /* * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit @@ -161,7 +162,7 @@ static void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) } } -static void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp) +static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) { u32 reg_offset, bit_pos; struct keystone_pcie *ks_pcie; @@ -171,55 +172,55 @@ static void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp) ks_pcie = to_keystone_pcie(pci); update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4), - BIT(bit_pos)); - ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); + ks_pcie_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4), + BIT(bit_pos)); + ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); } -static void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) +static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq) { u32 reg_offset, bit_pos; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4), - BIT(bit_pos)); + ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4), + BIT(bit_pos)); } -static void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) +static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq) { u32 reg_offset, bit_pos; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4), - BIT(bit_pos)); + ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4), + BIT(bit_pos)); } -static int ks_dw_pcie_msi_host_init(struct pcie_port *pp) +static int ks_pcie_msi_host_init(struct pcie_port *pp) { return dw_pcie_allocate_domains(pp); } -static void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) +static void ks_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) { int i; for (i = 0; i < PCI_NUM_INTX; i++) - ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1); + ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1); } -static void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, - int offset) +static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, + int offset) { struct dw_pcie *pci = ks_pcie->pci; struct device *dev = pci->dev; u32 pending; int virq; - pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4)); + pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS + (offset << 4)); if (BIT(0) & pending) { virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); @@ -228,19 +229,19 @@ static void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, } /* EOI the INTx interrupt */ - ks_dw_app_writel(ks_pcie, IRQ_EOI, offset); + ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); } -static void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) +static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { - ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); + ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); } -static irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) +static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) { u32 status; - status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL; + status = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL; if (!status) return IRQ_NONE; @@ -249,83 +250,83 @@ static irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) status); /* Ack the IRQ; status bits are RW1C */ - ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status); + ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, status); return IRQ_HANDLED; } -static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d) +static void ks_pcie_ack_legacy_irq(struct irq_data *d) { } -static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d) +static void ks_pcie_mask_legacy_irq(struct irq_data *d) { } -static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d) +static void ks_pcie_unmask_legacy_irq(struct irq_data *d) { } -static struct irq_chip ks_dw_pcie_legacy_irq_chip = { +static struct irq_chip ks_pcie_legacy_irq_chip = { .name = "Keystone-PCI-Legacy-IRQ", - .irq_ack = ks_dw_pcie_ack_legacy_irq, - .irq_mask = ks_dw_pcie_mask_legacy_irq, - .irq_unmask = ks_dw_pcie_unmask_legacy_irq, + .irq_ack = ks_pcie_ack_legacy_irq, + .irq_mask = ks_pcie_mask_legacy_irq, + .irq_unmask = ks_pcie_unmask_legacy_irq, }; -static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d, - unsigned int irq, - irq_hw_number_t hw_irq) +static int ks_pcie_init_legacy_irq_map(struct irq_domain *d, + unsigned int irq, + irq_hw_number_t hw_irq) { - irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip, + irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip, handle_level_irq); irq_set_chip_data(irq, d->host_data); return 0; } -static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = { - .map = ks_dw_pcie_init_legacy_irq_map, +static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = { + .map = ks_pcie_init_legacy_irq_map, .xlate = irq_domain_xlate_onetwocell, }; /** - * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask + * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask * registers * * Since modification of dbi_cs2 involves different clock domain, read the * status back to ensure the transition is complete. */ -static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) +static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) { u32 val; - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); + ks_pcie_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val); do { - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); } while (!(val & DBI_CS2_EN_VAL)); } /** - * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode + * ks_pcie_clear_dbi_mode() - Disable DBI mode * * Since modification of dbi_cs2 involves different clock domain, read the * status back to ensure the transition is complete. */ -static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) +static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) { u32 val; - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); + ks_pcie_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val); do { - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); } while (val & DBI_CS2_EN_VAL); } -static void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) +static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) { struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; @@ -334,26 +335,26 @@ static void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) u32 val; /* Disable BARs for inbound access */ - ks_dw_pcie_set_dbi_mode(ks_pcie); + ks_pcie_set_dbi_mode(ks_pcie); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); - ks_dw_pcie_clear_dbi_mode(ks_pcie); + ks_pcie_clear_dbi_mode(ks_pcie); /* Set outbound translation size per window division */ - ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7); + ks_pcie_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7); tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M; /* Using Direct 1:1 mapping of RC <-> PCI memory space */ for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) { - ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1); - ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0); + ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1); + ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 0); start += tr_size; } /* Enable OB translation */ - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); + ks_pcie_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val); } /** @@ -394,13 +395,13 @@ static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus, if (bus != 1) regval |= BIT(24); - ks_dw_app_writel(ks_pcie, CFG_SETUP, regval); + ks_pcie_app_writel(ks_pcie, CFG_SETUP, regval); return pp->va_cfg0_base; } -static int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, - u32 *val) +static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, + u32 *val) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); @@ -412,9 +413,9 @@ static int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, return dw_pcie_read(addr + where, size, val); } -static int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, - u32 val) +static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, + u32 val) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); @@ -427,23 +428,23 @@ static int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, } /** - * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization + * ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization * * This sets BAR0 to enable inbound access for MSI_IRQ register */ -static void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) +static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); /* Configure and set up BAR0 */ - ks_dw_pcie_set_dbi_mode(ks_pcie); + ks_pcie_set_dbi_mode(ks_pcie); /* Enable BAR0 */ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); - ks_dw_pcie_clear_dbi_mode(ks_pcie); + ks_pcie_clear_dbi_mode(ks_pcie); /* * For BAR0, just setting bus address for inbound writes (MSI) should @@ -453,9 +454,9 @@ static void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) } /** - * ks_dw_pcie_link_up() - Check if link up + * ks_pcie_link_up() - Check if link up */ -static int ks_dw_pcie_link_up(struct dw_pcie *pci) +static int ks_pcie_link_up(struct dw_pcie *pci) { u32 val; @@ -463,28 +464,28 @@ static int ks_dw_pcie_link_up(struct dw_pcie *pci) return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; } -static void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) +static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) { u32 val; /* Disable Link training */ - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val &= ~LTSSM_EN_VAL; - ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); + ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); /* Initiate Link Training */ - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); + ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); } /** - * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware + * ks_pcie_dw_host_init() - initialize host for v3_65 dw hardware * * Ioremap the register resources, initialize legacy irq domain * and call dw_pcie_v3_65_host_init() API to initialize the Keystone * PCI host controller. */ -static int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie) +static int __init ks_pcie_dw_host_init(struct keystone_pcie *ks_pcie) { struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; @@ -517,7 +518,7 @@ static int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie) ks_pcie->legacy_irq_domain = irq_domain_add_linear(ks_pcie->legacy_intc_np, PCI_NUM_INTX, - &ks_dw_pcie_legacy_irq_domain_ops, + &ks_pcie_legacy_irq_domain_ops, NULL); if (!ks_pcie->legacy_irq_domain) { dev_err(dev, "Failed to add irq domain for legacy irqs\n"); @@ -527,7 +528,7 @@ static int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie) return dw_pcie_host_init(pp); } -static void quirk_limit_mrrs(struct pci_dev *dev) +static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; struct pci_dev *bridge; @@ -568,7 +569,7 @@ static void quirk_limit_mrrs(struct pci_dev *dev) } } } -DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs); +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) { @@ -580,7 +581,7 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) return 0; } - ks_dw_pcie_initiate_link_train(ks_pcie); + ks_pcie_initiate_link_train(ks_pcie); /* check if the link is up or not */ if (!dw_pcie_wait_for_link(pci)) @@ -607,7 +608,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc) * ack operation. */ chained_irq_enter(chip, desc); - ks_dw_pcie_handle_msi_irq(ks_pcie, offset); + ks_pcie_handle_msi_irq(ks_pcie, offset); chained_irq_exit(chip, desc); } @@ -636,7 +637,7 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) * ack operation. */ chained_irq_enter(chip, desc); - ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset); + ks_pcie_handle_legacy_irq(ks_pcie, irq_offset); chained_irq_exit(chip, desc); } @@ -708,7 +709,7 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) ks_pcie_legacy_irq_handler, ks_pcie); } - ks_dw_pcie_enable_legacy_irqs(ks_pcie); + ks_pcie_enable_legacy_irqs(ks_pcie); /* MSI IRQ */ if (IS_ENABLED(CONFIG_PCI_MSI)) { @@ -720,7 +721,7 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) } if (ks_pcie->error_irq > 0) - ks_dw_pcie_enable_error_irq(ks_pcie); + ks_pcie_enable_error_irq(ks_pcie); } /* @@ -728,8 +729,8 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) * bus error instead of returning 0xffffffff. This handler always returns 0 * for this kind of faults. */ -static int keystone_pcie_fault(unsigned long addr, unsigned int fsr, - struct pt_regs *regs) +static int ks_pcie_fault(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) { unsigned long instr = *(unsigned long *) instruction_pointer(regs); @@ -751,7 +752,7 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); ks_pcie_establish_link(ks_pcie); - ks_dw_pcie_setup_rc_app_regs(ks_pcie); + ks_pcie_setup_rc_app_regs(ks_pcie); ks_pcie_setup_interrupts(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), pci->dbi_base + PCI_IO_BASE); @@ -763,33 +764,33 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) * PCIe access errors that result into OCP errors are caught by ARM as * "External aborts" */ - hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0, + hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); return 0; } -static const struct dw_pcie_host_ops keystone_pcie_host_ops = { - .rd_other_conf = ks_dw_pcie_rd_other_conf, - .wr_other_conf = ks_dw_pcie_wr_other_conf, +static const struct dw_pcie_host_ops ks_pcie_host_ops = { + .rd_other_conf = ks_pcie_rd_other_conf, + .wr_other_conf = ks_pcie_wr_other_conf, .host_init = ks_pcie_host_init, - .msi_set_irq = ks_dw_pcie_msi_set_irq, - .msi_clear_irq = ks_dw_pcie_msi_clear_irq, - .get_msi_addr = ks_dw_pcie_get_msi_addr, - .msi_host_init = ks_dw_pcie_msi_host_init, - .msi_irq_ack = ks_dw_pcie_msi_irq_ack, - .scan_bus = ks_dw_pcie_v3_65_scan_bus, + .msi_set_irq = ks_pcie_msi_set_irq, + .msi_clear_irq = ks_pcie_msi_clear_irq, + .get_msi_addr = ks_pcie_get_msi_addr, + .msi_host_init = ks_pcie_msi_host_init, + .msi_irq_ack = ks_pcie_msi_irq_ack, + .scan_bus = ks_pcie_v3_65_scan_bus, }; -static irqreturn_t pcie_err_irq_handler(int irq, void *priv) +static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) { struct keystone_pcie *ks_pcie = priv; - return ks_dw_pcie_handle_error_irq(ks_pcie); + return ks_pcie_handle_error_irq(ks_pcie); } -static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, - struct platform_device *pdev) +static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, + struct platform_device *pdev) { struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; @@ -818,7 +819,7 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, if (ks_pcie->error_irq <= 0) dev_info(dev, "no error IRQ defined\n"); else { - ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler, + ret = request_irq(ks_pcie->error_irq, ks_pcie_err_irq_handler, IRQF_SHARED, "pcie-error-irq", ks_pcie); if (ret < 0) { dev_err(dev, "failed to request error IRQ %d\n", @@ -827,8 +828,8 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, } } - pp->ops = &keystone_pcie_host_ops; - ret = ks_dw_pcie_host_init(ks_pcie); + pp->ops = &ks_pcie_host_ops; + ret = ks_pcie_dw_host_init(ks_pcie); if (ret) { dev_err(dev, "failed to initialize host\n"); return ret; @@ -845,8 +846,8 @@ static const struct of_device_id ks_pcie_of_match[] = { { }, }; -static const struct dw_pcie_ops dw_pcie_ops = { - .link_up = ks_dw_pcie_link_up, +static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { + .link_up = ks_pcie_link_up, }; static int __exit ks_pcie_remove(struct platform_device *pdev) @@ -877,7 +878,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return -ENOMEM; pci->dev = dev; - pci->ops = &dw_pcie_ops; + pci->ops = &ks_pcie_dw_pcie_ops; ks_pcie->pci = pci; @@ -912,7 +913,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (ret) return ret; - ret = ks_add_pcie_port(ks_pcie, pdev); + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto fail_clk; From patchwork Mon Oct 15 13:07:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148836 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3777788lji; 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[209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.10.02; Mon, 15 Oct 2018 06:10:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fgizKdNv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726888AbeJOUyU (ORCPT + 32 others); Mon, 15 Oct 2018 16:54:20 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:47964 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726400AbeJOUyU (ORCPT ); Mon, 15 Oct 2018 16:54:20 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD8Xid123815; Mon, 15 Oct 2018 08:08:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608913; bh=I+8oB3slUMP8h64wG5S3UqrQQp1pEImCeexOuq//BTs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fgizKdNvy5mPKPo/4QrZKVnn5YTB7KYLVHhSJ0YpezWODF3V4aPFCDGePshJanU2d DxQ9sdf8wVfs5kQPjJtN51W2211/ASAMJCE+jNsgGo2oDdrbe6j7bYoWC/p6/8UEcW cU2dYfxFtpojYJPWhp4/AHcDCthXXgBXI0U3D8AY= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD8Xvn011585; Mon, 15 Oct 2018 08:08:33 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:08:32 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:08:32 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tLD009433; Mon, 15 Oct 2018 08:08:29 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 10/19] PCI: keystone: Use syscon APIs to get device id from control module Date: Mon, 15 Oct 2018 18:37:12 +0530 Message-ID: <20181015130721.5535-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Control module registers should be read using syscon APIs. pci-keystone.c uses platform_get_resource to get control module registers. Fix it here by using syscon APIs to get device id from control module. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 45 ++++++++++++++++------- 1 file changed, 32 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e2045b5d2af2..e22328f89c84 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -15,12 +15,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include @@ -28,6 +30,9 @@ #define DRIVER_NAME "keystone-pcie" +#define PCIE_VENDORID_MASK 0xffff +#define PCIE_DEVICEID_SHIFT 16 + /* DEV_STAT_CTRL */ #define PCIE_CAP_BASE 0x70 @@ -744,10 +749,34 @@ static int ks_pcie_fault(unsigned long addr, unsigned int fsr, return 0; } +static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) +{ + int ret; + unsigned int id; + struct regmap *devctrl_regs; + struct dw_pcie *pci = ks_pcie->pci; + struct device *dev = pci->dev; + struct device_node *np = dev->of_node; + + devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); + if (IS_ERR(devctrl_regs)) + return PTR_ERR(devctrl_regs); + + ret = regmap_read(devctrl_regs, 0, &id); + if (ret) + return ret; + + dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); + dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); + + return 0; +} + static int __init ks_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + int ret; dw_pcie_setup_rc(pp); @@ -757,8 +786,9 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), pci->dbi_base + PCI_IO_BASE); - /* update the Vendor ID */ - writew(ks_pcie->device_id, pci->dbi_base + PCI_DEVICE_ID); + ret = ks_pcie_init_id(ks_pcie); + if (ret < 0) + return ret; /* * PCIe access errors that result into OCP errors are caught by ARM as @@ -864,8 +894,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; - struct resource *res; - void __iomem *reg_p; struct phy *phy; int ret; @@ -893,15 +921,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return ret; } - /* index 2 is to read PCI DEVICE_ID */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 2); - reg_p = devm_ioremap_resource(dev, res); - if (IS_ERR(reg_p)) - return PTR_ERR(reg_p); - ks_pcie->device_id = readl(reg_p) >> 16; - devm_iounmap(dev, reg_p); - devm_release_mem_region(dev, res->start, resource_size(res)); - ks_pcie->np = dev->of_node; platform_set_drvdata(pdev, ks_pcie); ks_pcie->clk = devm_clk_get(dev, "pcie"); From patchwork Mon Oct 15 13:07:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148839 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3778574lji; Mon, 15 Oct 2018 06:10:44 -0700 (PDT) X-Google-Smtp-Source: ACcGV63Ocuix53IEk+1vaDWSCf9Z/s1XVaeTOh+eXXN4ox9Xd+NyBQrIH7bQIBmysdcWVRPM2pMv X-Received: by 2002:a17:902:b706:: with SMTP id d6-v6mr17163042pls.53.1539609044757; Mon, 15 Oct 2018 06:10:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539609044; cv=none; d=google.com; s=arc-20160816; b=JOUfim8YK1wYSO45RXgje9sI4kh1/YMBCjHriAVIAd4p1cCqBt1KbsdPNC3p7oDA3U d7W7D0ILIwige8mtdeAMv2tb9jKJm3v0gVqYA1+1IOVE+Zb3ApNyU/aRbE1fA7grSBya AMYoXQB1WaBGorWijqoNB7xIpVMgWGNrwM49SnW5U2G6alIxglA+juUADuimLEgil4EI RlonT0UtrxhN5beH1yHdB9CySulKZZ2IFY3Ni6cw7kctXF0kWNZp9bDClMxVOKgfaCJs 1mcDJlkjykLjwklKoPVu2Npj0iIAFXiVg1Y5eifYjvCtJxGPBsHZ0yH7EFu1zGCAvubi yOJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=uhWgEzyVP3VnG1Ezc4XH+0LTZ9iFYXuXx7tSC+ERFF4=; b=gafRvHRHVQNXh3xE/e0wnkYjqU1hmtu7rDyCpBX8PlOI4n32tVEOn+rB/nUTyzi89l qne3rFKW9REFsLooL+gsjnUSDBkuGnanfkB1m9eUtdoFnymLDgmccaeMkW0NTz+UoVUg +awV8t6MyMNJJqNoCAXZpEPQELU4KONzlBfBsZ+1lun/XBwTJhzW8eA+M/eJGXjmHKhx gNgy9fpWsOEeGA3a0/DbFZFmBnHcIWZCwkABSBirEWzpxAPla2PjjLBRxdr/skIEHZjR ACw8Pvwot4NxgPD4Em24VAgFq9e7Tv4uhJLRW/kHTL3WGC7eW37uYRJIh96BLqDSpQFc gNgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kRw816gW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.10.44; Mon, 15 Oct 2018 06:10:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kRw816gW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726956AbeJOUyf (ORCPT + 32 others); Mon, 15 Oct 2018 16:54:35 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:47994 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726687AbeJOUyf (ORCPT ); Mon, 15 Oct 2018 16:54:35 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD8aDx123858; Mon, 15 Oct 2018 08:08:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608916; bh=uhWgEzyVP3VnG1Ezc4XH+0LTZ9iFYXuXx7tSC+ERFF4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kRw816gWMq2ktssguB+lD5vIoWXAVk6hnegRjIkzkXqT2PmrZ/4qvYrYIGZEKtAYm MUTCGDrJ+sK1aeaUYHl78edTkzapXXYyXhNrghPCpXncqc3yBxO+Os6JKlE2ixtwgp bADMRXc06/WC7j+Vh1ELTgrAr6ztu3IFinSaKZEw= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD8aGT011714; Mon, 15 Oct 2018 08:08:36 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:08:36 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:08:36 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tLE009433; Mon, 15 Oct 2018 08:08:33 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 11/19] PCI: keystone: Cleanup PHY handling Date: Mon, 15 Oct 2018 18:37:13 +0530 Message-ID: <20181015130721.5535-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Cleanup PHY handling by using devm_phy_optional_get to get PHYs if the PHYs are optional, creating a device link between the PHY device and the controller device and disable PHY on error cases here. Also invoke phy_reset() as part of initializing PHY. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 126 +++++++++++++++++++--- 1 file changed, 110 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e22328f89c84..bf37609ad75b 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -105,6 +105,9 @@ struct keystone_pcie { int num_msi_host_irqs; int msi_host_irqs[MAX_MSI_HOST_IRQS]; + int num_lanes; + struct phy **phy; + struct device_link **link; struct device_node *msi_intc_np; struct irq_domain *legacy_irq_domain; struct device_node *np; @@ -880,22 +883,61 @@ static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .link_up = ks_pcie_link_up, }; -static int __exit ks_pcie_remove(struct platform_device *pdev) +static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) { - struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); + int num_lanes = ks_pcie->num_lanes; - clk_disable_unprepare(ks_pcie->clk); + while (num_lanes--) { + phy_power_off(ks_pcie->phy[num_lanes]); + phy_exit(ks_pcie->phy[num_lanes]); + } +} + +static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) +{ + int i; + int ret; + int num_lanes = ks_pcie->num_lanes; + + for (i = 0; i < num_lanes; i++) { + ret = phy_reset(ks_pcie->phy[i]); + if (ret < 0) + goto err_phy; + + ret = phy_init(ks_pcie->phy[i]); + if (ret < 0) + goto err_phy; + + ret = phy_power_on(ks_pcie->phy[i]); + if (ret < 0) { + phy_exit(ks_pcie->phy[i]); + goto err_phy; + } + } return 0; + +err_phy: + while (--i >= 0) { + phy_power_off(ks_pcie->phy[i]); + phy_exit(ks_pcie->phy[i]); + } + + return ret; } static int __init ks_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; - struct phy *phy; + struct device_link **link; + struct phy **phy; + u32 num_lanes; + char name[10]; int ret; + int i; ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) @@ -908,29 +950,59 @@ static int __init ks_pcie_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; - ks_pcie->pci = pci; + ret = of_property_read_u32(np, "num-lanes", &num_lanes); + if (ret) + num_lanes = 1; - /* initialize SerDes Phy if present */ - phy = devm_phy_get(dev, "pcie-phy"); - if (PTR_ERR_OR_ZERO(phy) == -EPROBE_DEFER) - return PTR_ERR(phy); + phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL); + if (!phy) + return -ENOMEM; - if (!IS_ERR_OR_NULL(phy)) { - ret = phy_init(phy); - if (ret < 0) - return ret; + link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL); + if (!link) + return -ENOMEM; + + for (i = 0; i < num_lanes; i++) { + snprintf(name, sizeof(name), "pcie-phy%d", i); + phy[i] = devm_phy_optional_get(dev, name); + if (IS_ERR(phy[i])) { + ret = PTR_ERR(phy[i]); + goto err_link; + } + + if (!phy[i]) + continue; + + link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); + if (!link[i]) { + ret = -EINVAL; + goto err_link; + } + } + + ks_pcie->np = np; + ks_pcie->pci = pci; + ks_pcie->link = link; + ks_pcie->num_lanes = num_lanes; + ks_pcie->phy = phy; + + ret = ks_pcie_enable_phy(ks_pcie); + if (ret) { + dev_err(dev, "failed to enable phy\n"); + goto err_link; } - ks_pcie->np = dev->of_node; platform_set_drvdata(pdev, ks_pcie); ks_pcie->clk = devm_clk_get(dev, "pcie"); if (IS_ERR(ks_pcie->clk)) { dev_err(dev, "Failed to get pcie rc clock\n"); - return PTR_ERR(ks_pcie->clk); + ret = PTR_ERR(ks_pcie->clk); + goto err_phy; } + ret = clk_prepare_enable(ks_pcie->clk); if (ret) - return ret; + goto err_phy; ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) @@ -940,9 +1012,31 @@ static int __init ks_pcie_probe(struct platform_device *pdev) fail_clk: clk_disable_unprepare(ks_pcie->clk); +err_phy: + ks_pcie_disable_phy(ks_pcie); + +err_link: + while (--i >= 0 && link[i]) + device_link_del(link[i]); + return ret; } +static int __exit ks_pcie_remove(struct platform_device *pdev) +{ + struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); + struct device_link **link = ks_pcie->link; + int num_lanes = ks_pcie->num_lanes; + + clk_disable_unprepare(ks_pcie->clk); + ks_pcie_disable_phy(ks_pcie); + + while (num_lanes--) + device_link_del(link[num_lanes]); + + return 0; +} + static struct platform_driver ks_pcie_driver __refdata = { .probe = ks_pcie_probe, .remove = __exit_p(ks_pcie_remove), From patchwork Mon Oct 15 13:07:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148840 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3778585lji; Mon, 15 Oct 2018 06:10:45 -0700 (PDT) X-Google-Smtp-Source: ACcGV61zkUTplkw4Uakq6ds+5EybMV3BIpe9/5UOVZtShz51vTQWPva98HoArSVyZukH1I8X64vg X-Received: by 2002:a62:241a:: with SMTP id r26-v6mr13085211pfj.74.1539609045212; Mon, 15 Oct 2018 06:10:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539609045; cv=none; d=google.com; s=arc-20160816; b=ZZzQvxwODMeATSYTNshod/jH+0DjzcnAJ4+h8I26ZPQl/p/TyHeXWR6Eld423Cj3E3 8o2AjWpMKyYk/NUrKgkR5ciz4fBpygocc0RGifuHoxVHIHuCnv+2BSYKpYUID0KfYHtc CCcSMzfFxwY68W4wSuWV/4dKfp3HZjeNI9oCzg8DZ55hxtTWQ8r/d/UM4G1/JWZNZdrL uaKBtW865HXUWNq7TmafuHs5Cx5QTH3F6/upKKTqI0PSQlLvjrcTSjVs+Rv9iqIsG2Wo XvNjczNbmMuyaA7sbmp72O2prMWwxofWQHXdX+y7HzzzUR1LdgvE8EXY7AMNrbMjKTqd a05w== ARC-Message-Signature: i=1; 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Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 28 ++++++++++------------- 1 file changed, 12 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index bf37609ad75b..891bdfc5921c 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -96,7 +96,6 @@ struct keystone_pcie { struct dw_pcie *pci; - struct clk *clk; /* PCI Device ID */ u32 device_id; int num_legacy_host_irqs; @@ -993,26 +992,22 @@ static int __init ks_pcie_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, ks_pcie); - ks_pcie->clk = devm_clk_get(dev, "pcie"); - if (IS_ERR(ks_pcie->clk)) { - dev_err(dev, "Failed to get pcie rc clock\n"); - ret = PTR_ERR(ks_pcie->clk); - goto err_phy; + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; } - ret = clk_prepare_enable(ks_pcie->clk); - if (ret) - goto err_phy; - ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) - goto fail_clk; + goto err_get_sync; return 0; -fail_clk: - clk_disable_unprepare(ks_pcie->clk); -err_phy: +err_get_sync: + pm_runtime_put(dev); + pm_runtime_disable(dev); ks_pcie_disable_phy(ks_pcie); err_link: @@ -1027,10 +1022,11 @@ static int __exit ks_pcie_remove(struct platform_device *pdev) struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); struct device_link **link = ks_pcie->link; int num_lanes = ks_pcie->num_lanes; + struct device *dev = &pdev->dev; - clk_disable_unprepare(ks_pcie->clk); + pm_runtime_put(dev); + pm_runtime_disable(dev); ks_pcie_disable_phy(ks_pcie); - while (num_lanes--) device_link_del(link[num_lanes]); From patchwork Mon Oct 15 13:07:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148842 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3778621lji; Mon, 15 Oct 2018 06:10:46 -0700 (PDT) X-Google-Smtp-Source: ACcGV635J8dDjxoYGqTlG3483KjQQhjF2TGPymTs7UmTsieW5kI2HsZUgDsN7V2G3SVotdw8xRy7 X-Received: by 2002:a63:66c3:: with SMTP id a186-v6mr16116276pgc.330.1539609046479; Mon, 15 Oct 2018 06:10:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539609046; cv=none; d=google.com; s=arc-20160816; b=KcElHMUQpNLngwcXuGJnaGPE/lFrMXbAzxxtBc9PvfoUtfi2UG5klTI1Auaje139eK nWTjYuSsxsuCC92PZ9qbQqTjsQ8K0jdFM0cmx9m4lnNHbWXR7IbIrqo2hOsWuv1Uc+FO 9KWuvPqynzWcccbF48i0IysVSrORhleOw+26qfDc9xHG1i/aGLu4l99lFy3FTwo3HEwl Aqe6mbLriihPtkX9t4CUi0lI3otmQxUT+FQdzfFxUG3pIqkTlsCZZH29QnGLHe9jYVLZ iJvAJKIqEgB5BKA9t+CGi11jttk0kPJwXeE4MPg5TOSL2sc5IADc1l1LT2T1s1VisKA4 tJ5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Mxqe0KM7Bxj85C0WPvfyIVhbaLgiQQe6fejwheakRvA=; b=Hq1dtQyojKC9cMEwygLczLjZ1pyf1sc0FN1ritWwNYU9QY82rsp6TLdsd0Hy9KQfqF h0O+xOR0pwRqnHg29gk701JBM7/Z1CSIs9LWwjnCv9L0x9swtb3WsbPs/T3viamNTvFL dnAEwC5bMOkjrcOFhYhnOSva8C0WW8iC83DsN+DkkUMu2QGxxl5NlB2WkJAJ/8jj8fBa 4LXDecDIs2qCYitnu3y3BN98FmrBFV6+MfoRvL7fLkbkOC65cUjEyHuHbYMOKh27BMsp 4tjDyjm0nYCrCTxkgFjcCRaPeGl+pmtjtShCOwY5fhQlwNwygCWmFkixg6CIBE9MKEmd dWiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mxsDPcC2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 70 +++++++---------------- 1 file changed, 20 insertions(+), 50 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 891bdfc5921c..adf98dc0035c 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -45,7 +45,13 @@ /* Application registers */ #define CMD_STATUS 0x004 + #define CFG_SETUP 0x008 +#define CFG_BUS(x) (((x) & 0xff) << 16) +#define CFG_DEVICE(x) (((x) & 0x1f) << 8) +#define CFG_FUNC(x) ((x) & 0x7) +#define CFG_TYPE1 BIT(24) + #define OB_SIZE 0x030 #define CFG_PCIM_WIN_SZ_IDX 3 #define CFG_PCIM_WIN_CNT 32 @@ -364,60 +370,21 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) ks_pcie_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val); } -/** - * ks_pcie_cfg_setup() - Set up configuration space address for a device - * - * @ks_pcie: ptr to keystone_pcie structure - * @bus: Bus number the device is residing on - * @devfn: device, function number info - * - * Forms and returns the address of configuration space mapped in PCIESS - * address space 0. Also configures CFG_SETUP for remote configuration space - * access. - * - * The address space has two regions to access configuration - local and remote. - * We access local region for bus 0 (as RC is attached on bus 0) and remote - * region for others with TYPE 1 access when bus > 1. As for device on bus = 1, - * we will do TYPE 0 access as it will be on our secondary bus (logical). - * CFG_SETUP is needed only for remote configuration access. - */ -static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus, - unsigned int devfn) -{ - u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn); - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - u32 regval; - - if (bus == 0) - return pci->dbi_base; - - regval = (bus << 16) | (device << 8) | function; - - /* - * Since Bus#1 will be a virtual bus, we need to have TYPE0 - * access only. - * TYPE 1 - */ - if (bus != 1) - regval |= BIT(24); - - ks_pcie_app_writel(ks_pcie, CFG_SETUP, regval); - return pp->va_cfg0_base; -} - static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - u8 bus_num = bus->number; - void __iomem *addr; + u32 reg; - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); + reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | + CFG_FUNC(PCI_FUNC(devfn)); + if (bus->parent->number != pp->root_bus_nr) + reg |= CFG_TYPE1; + ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); - return dw_pcie_read(addr + where, size, val); + return dw_pcie_read(pp->va_cfg0_base + where, size, val); } static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, @@ -426,12 +393,15 @@ static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - u8 bus_num = bus->number; - void __iomem *addr; + u32 reg; - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); + reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | + CFG_FUNC(PCI_FUNC(devfn)); + if (bus->parent->number != pp->root_bus_nr) + reg |= CFG_TYPE1; + ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); - return dw_pcie_write(addr + where, size, val); + return dw_pcie_write(pp->va_cfg0_base + where, size, val); } /** From patchwork Mon Oct 15 13:07:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148845 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3778701lji; Mon, 15 Oct 2018 06:10:49 -0700 (PDT) X-Google-Smtp-Source: ACcGV61XH++N4EGijsQiogiBK71fIjHbr6+sfd9aolVxmnFQmNlrNHc6/cPGf7G6A/ZQ5/WT8TAk X-Received: by 2002:a63:de46:: with SMTP id y6-v6mr15958490pgi.198.1539609049306; Mon, 15 Oct 2018 06:10:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539609049; cv=none; d=google.com; s=arc-20160816; b=TstYkaX/zDh4GYb5AKrXveRSshOMWwz1vim2+Xbd5KnFwJTAGbkrd8heJIY5gvWdkw Er6f1gOEFf73zhKa+kiHfa6ZXrJzYto8SYxJVHH3XqrYGP7VWma48wvQbpr4Ds+0sXc7 7w8yO9hoqDwYHQGRIqwsQ00M+E3pHgEOoTQeUj9tGPdr39q/kdpPNIob/AFdmbC0p9/j ZIfZBPd1JDiUzv+aBmVzxRsex0jPxhRbsXd1+3vv3DQdiVECvp2FLoB6VJ6ckCVc8TRY zfaofLh7hRx91yNFNmtn0+eYQPTLxIzniV6Yufx2qzqUgBCY0m4lkWkGEcELAkq3JXmN ka8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=AByttV0CbD6kHf0vx5L2FAk6NqqlvvyZAgV6B09W4eo=; b=RaBqQi+/cO+Yq87VOJkeIYB6FgYqfB20Gebhe5SdcpOm6mlT2VA2t4i6OFeII9Hn6Z WIKObC0/edsALSsfTyEy/6BjQ8IybJzm/Jr6DRXpjpJleOAPY5deX6urjYnY0HkmLU9K +wz2Rlkkx2tKjCki8L2Mx81v17Alw53RvcjrdKTv93sCUdhJOT+3S8UX4o+rGRAuRZ3/ PeH1nh1OzDLr5TDBvH8zazkrxKaMQMr6KV5V+2yBNCQW+IluXdilbT3thoPCufG4wSSp qqmraDyZvRwCT5qQYcJiXtpl1g1LBkzXpa3b1Fevdx9OUSn8D0uWlh94deYbSYLYnkF9 qeuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VEGYUpZf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.10.49; Mon, 15 Oct 2018 06:10:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VEGYUpZf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727027AbeJOUyr (ORCPT + 32 others); Mon, 15 Oct 2018 16:54:47 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:43470 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726697AbeJOUyq (ORCPT ); Mon, 15 Oct 2018 16:54:46 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD8q16089360; Mon, 15 Oct 2018 08:08:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608932; bh=AByttV0CbD6kHf0vx5L2FAk6NqqlvvyZAgV6B09W4eo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VEGYUpZfoEa8MicRkv4KD/J5dIz8oIyvoC5vRphyKA0oAGnW6hsqraRtdmcI89dc/ XRGQRUxoHTD82fKD4YNFsEeJvP/Gwg5WgUYvXM1igV4Nx0ENQDxUMWOsnAgrzo8ARJ 3oX9fLuJC7xmAfjIFrgAiM8s4xc3Hb8YAPeE9pkU= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD8qZV000957; Mon, 15 Oct 2018 08:08:52 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:08:51 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:08:51 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tLI009433; Mon, 15 Oct 2018 08:08:49 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 15/19] PCI: keystone: Cleanup set_dbi_mode and get_dbi_mode Date: Mon, 15 Oct 2018 18:37:17 +0530 Message-ID: <20181015130721.5535-16-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Use BIT() macro for DBI_CS2 and cleanup set_dbimode and get_dbi_mode Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 68b080aef3ac..7015a353a614 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -40,7 +40,7 @@ #define LTSSM_EN_VAL BIT(0) #define LTSSM_STATE_MASK 0x1f #define LTSSM_STATE_L0 0x11 -#define DBI_CS2_EN_VAL 0x20 +#define DBI_CS2 BIT(5) #define OB_XLAT_EN_VAL BIT(1) /* Application registers */ @@ -319,11 +319,12 @@ static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) u32 val; val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - ks_pcie_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val); + val |= DBI_CS2; + ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); do { val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - } while (!(val & DBI_CS2_EN_VAL)); + } while (!(val & DBI_CS2)); } /** @@ -337,11 +338,12 @@ static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) u32 val; val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - ks_pcie_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val); + val &= ~DBI_CS2; + ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); do { val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - } while (val & DBI_CS2_EN_VAL); + } while (val & DBI_CS2); } static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) From patchwork Mon Oct 15 13:07:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148841 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3778606lji; Mon, 15 Oct 2018 06:10:46 -0700 (PDT) X-Google-Smtp-Source: ACcGV62COZbNpo/xnYhhfLMQkMGFeVgOEN2BzSMJYH/LfBsFNLihKMsJDrfnemFfhwNEn0tHqXNs X-Received: by 2002:a62:ea03:: with SMTP id t3-v6mr18186091pfh.228.1539609045865; Mon, 15 Oct 2018 06:10:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539609045; cv=none; d=google.com; s=arc-20160816; b=GPavsFlEI9kSzC6W+GeSBGKZCT94Kaek8/x39gBYB+NpVkNbkCF7vWpGdlYwf5isi8 ZeiKkrqfdmVdfqe/txSwDzosZ0WvqaZ6KigaK17oj3HMbn2s7rOvaL1UPHPPhZiLgi69 doqSXTTSL80dY9n1j8WoFKf8AuABbw0LWx4xhlfsgY4SsDZazQ7k9k9CW1vGgEd0KR1c TPumxe0247kDK+W5vhs0B9Y/zYte7NHSDQo1FravuuZXQlKdQzMUqKOZ6NqsvX3dHUn4 8Rw6xVNwltNqnl+VqTFh+/nXru07NgFoiluurFpPA9FoitqxOziP0XB+IHrcGboF0caU G1xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=G9hq3x68WrRMbLheOnFYUO0lO7CLcco2NS7pcpSXcFw=; b=GW7U1CyilIQDxXPTV3fbJHuI8nNEloSKALq8SWjTfdQctN3avYCFTMBEbE+8WvhMTl 9i3ZJebz/hakHkiFAxqmIuvASbKv2KkOILXjb4Qh7CXImgBUsr3zHCUfvCliXIdfir6e hN/GWpLiU5p7a0ZFAUU8faAgW8mZ0RZqK/G2MAPorHVRoITw8l2nE2p0TsUbvASmOGgK QV3BL5ZXwSp23PnKJElfGn4CUFy3k3sYuqmqV9ztxa5iqQqdTkxrjlqnEAzq+PAqIdFF fRY9HX4H8Ny1aFvudUfPJelkJZg8HD/bOuXQdsadYb84MRLiXOr8Xs6NMdKg6hwSTGOl GYgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OpvkAwm3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.10.45; Mon, 15 Oct 2018 06:10:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OpvkAwm3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727005AbeJOUym (ORCPT + 32 others); Mon, 15 Oct 2018 16:54:42 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:48014 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726659AbeJOUyl (ORCPT ); Mon, 15 Oct 2018 16:54:41 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD8wki124006; Mon, 15 Oct 2018 08:08:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608938; bh=G9hq3x68WrRMbLheOnFYUO0lO7CLcco2NS7pcpSXcFw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OpvkAwm3jCXF79l5fgSW6AmJRc2T0KUV8LvUT1Xy1S6FKzI2UCjDQ7JXKYIuqT8kk ISIYGC2+nzlPZSW3UH34hoQSlbOUfIYmwGv6CGnxdfzbxo+EhGPySqA38h70FnrcyN /9JSj1pw44jgmoaYHC8O0VL/zElrdOJbppQ7BxGc= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD8w2w012053; Mon, 15 Oct 2018 08:08:58 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:08:58 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:08:58 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tLK009433; Mon, 15 Oct 2018 08:08:55 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 17/19] PCI: keystone: Add debug error message for all errors Date: Mon, 15 Oct 2018 18:37:19 +0530 Message-ID: <20181015130721.5535-18-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit 025dd3daeda77f61a280da87ae701 ("PCI: keystone: Add error IRQ handler") added dev_err() message only for ERR_AXI and ERR_FATAL. Add debug error message for ERR_SYS, ERR_NONFATAL, ERR_CORR and ERR_AER here. While at that avoid using ERR_IRQ_STATUS_RAW and use ERR_IRQ_STATUS instead. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 33 +++++++++++++++-------- 1 file changed, 22 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 67646a64c895..35ad3686d4a1 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -78,8 +78,6 @@ #define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */ #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ ERR_NONFATAL | ERR_FATAL | ERR_SYS) -#define ERR_FATAL_IRQ (ERR_FATAL | ERR_AXI) -#define ERR_IRQ_STATUS_RAW 0x1c0 #define ERR_IRQ_STATUS 0x1c4 #define ERR_IRQ_ENABLE_SET 0x1c8 #define ERR_IRQ_ENABLE_CLR 0x1cc @@ -251,18 +249,31 @@ static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) { - u32 status; + u32 reg; + struct device *dev = ks_pcie->pci->dev; + + reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS); + + if (reg & ERR_SYS) + dev_err(dev, "System Error\n"); + + if (reg & ERR_FATAL) + dev_err(dev, "Fatal Error\n"); + + if (reg & ERR_NONFATAL) + dev_dbg(dev, "Non Fatal Error\n"); + + if (reg & ERR_CORR) + dev_dbg(dev, "Correctable Error\n"); + + if (reg & ERR_AXI) + dev_err(dev, "AXI tag lookup fatal Error\n"); - status = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL; - if (!status) - return IRQ_NONE; + if (reg & ERR_AER) + dev_err(dev, "ECRC Error\n"); - if (status & ERR_FATAL_IRQ) - dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n", - status); + ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); - /* Ack the IRQ; status bits are RW1C */ - ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, status); return IRQ_HANDLED; } From patchwork Mon Oct 15 13:07:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 148848 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3778855lji; Mon, 15 Oct 2018 06:10:56 -0700 (PDT) X-Google-Smtp-Source: ACcGV61YaFtxfte9Vq3kAQKv1iM73TMQukNA/rxW/NK3NX4+PWcRRNJAsBXEFY16wQbtjs8R6L3c X-Received: by 2002:a17:902:101:: with SMTP id 1-v6mr17086589plb.15.1539609056258; Mon, 15 Oct 2018 06:10:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539609056; cv=none; d=google.com; s=arc-20160816; b=IrnTLTzt2/35Ri7MI3yEp4CkOY4lxZxMFIVAc0cb1LKOTt+XXoYQVx2+I5sbuBlR7M hi7y4s/Qt6sfb8yfqEbzuj7chbkL9c/QQYs4iPew0pVb/ltu7ttZuw0Zsr04R8/uHxgp /7NIatFP3poVn4U7jFGrHbTDcDQd0lv+jP+nj3IE6bLHskqqgdrwrD4bgTIPRL/X0rjE 0NEQRaOolhPn0nQ/BTIjftxsBZIJLbXe2uF7QQNJns1vg5QRz1ujV1o+cov7HgsjnWPY IpoNdRRJymrB+/YeWE5yImsAJw3bOpVU0cCGT5NJwtIX88/N8ZA5ve9veARrfCEczarw 7PUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=/Lop317aJeokhyczIggEMfoSTlt+zwGNePnrbHjKbE0=; b=YlS+HRvLZZ9hNVC9wGldWkh0FkxAksbWZzi2rTuz4fuHHmOLHx+edae8DGDkSj4jVc aEHrI3gIDG/6N9E2Z7VWMSY8R7+lAGAgf3Rj8uCO9i/nMj3L9z1tv1yiPGEN3AfEQ3hn VyDEdSNifAY3Fk1scH3nL2euChnEnuOFtW4iV4h0/VtL97s92ejFqUKfVUkTpdVIV3KY DOsq4p52kNVOo/ObaRzIDm7Ap4SrUA/vyvYNQEzuxqkB1tjo69fADuxEMikR0NfCkGeH bS4juNUxAHPNlRh8e32+C/n+jxkNrzpHtyc6/ddOotthoLwkyODjQ3wVUQsnGoPr/seK a3Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="w75gi9l/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3-v6si8169164plb.197.2018.10.15.06.10.56; Mon, 15 Oct 2018 06:10:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="w75gi9l/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726771AbeJOU4H (ORCPT + 32 others); Mon, 15 Oct 2018 16:56:07 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:38988 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726583AbeJOU4G (ORCPT ); Mon, 15 Oct 2018 16:56:06 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9FD92Ye120071; Mon, 15 Oct 2018 08:09:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539608942; bh=/Lop317aJeokhyczIggEMfoSTlt+zwGNePnrbHjKbE0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=w75gi9l/SdhkpIOGK08z5jXyouz9pffV6orQKolJTk467mjJ6ellAZ1T5dEKova5Y G/P6a6kthXpWQOZguDON93Tp3iGKgRtc6kherRyJSwqjF9L89UzNCzQTg/BIXTxGrk l8yf6E9L3rpKJ2TsqJgEtm9RKbhntFSuaKg3bHqM= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD92bK001247; Mon, 15 Oct 2018 08:09:02 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 15 Oct 2018 08:09:02 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 15 Oct 2018 08:09:02 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9FD7tLL009433; Mon, 15 Oct 2018 08:08:59 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH 18/19] PCI: keystone: Reorder header file in alphabetical order Date: Mon, 15 Oct 2018 18:37:20 +0530 Message-ID: <20181015130721.5535-19-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181015130721.5535-1-kishon@ti.com> References: <20181015130721.5535-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Reorder header file in alphabetical order. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 35ad3686d4a1..db40f60ce8ab 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -9,19 +9,19 @@ * Implementation based on pci-exynos.c and pcie-designware.c */ -#include #include #include +#include #include +#include #include -#include #include #include -#include #include +#include #include -#include #include +#include #include #include #include