From patchwork Tue Oct 16 13:35:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 148940 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp5100951lji; Tue, 16 Oct 2018 06:35:50 -0700 (PDT) X-Google-Smtp-Source: ACcGV635f8TN++GrAm2u0b8TxqH3NJY6NMT8ljVzTw/X7mBzsqq9SswWwcr/+0mKuNAAIadtArvW X-Received: by 2002:a17:902:6907:: with SMTP id j7-v6mr21651822plk.232.1539696950472; Tue, 16 Oct 2018 06:35:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539696950; cv=none; d=google.com; s=arc-20160816; b=fW3edhiw4P4fvXwU3zROLGQKNqpc5GeTKF4IfRMgUrLIj0lyWwCo7Iz3AsRVIevpQV KWbU9ENEy/REJ34f7b/CagZxPITznnKzS2NCpYXyee64BxGSMo7BiGx64KUbS4rQdlch OCYHxompAfyaMQYt0qFyk45HDZGogmGqX330htc2ldS6PfRzQIcFxWJq8k5JmSaOZzVQ xN8VVLL01EucgZvx4N5N0nzgCpbwmqQGZ7UGBXiVUAIhepVX5sIweP/0BabqZbCWJJeE FyEusUkqZ/UuBq3KCOpJpLGQxQbMeyxilmD8n5Ulpwqdzl401nHAQgffkHDUFU8ls+sf dsNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=wL/ER+PR+JDO0OBk89Q5MDiEPeEYtiD5fE01m0lgufE=; b=z5VvjJ0WaDZNiP8P9ofrsFJz8g5oAe9m0hoKK+4CcJHBbj+K11SUV/8n6tpR3jSJbZ hSZ3zxIPCpSXxTlcmL+Mrulxs/C5zuTOAy7x7MeTzyYqCNf0erMqkoZY7mZ2KK5xwWLQ SnXvcL682aQ4KiRcgK5dHubhqVs6TrPS2V0a+Jm3BuxSKS2alliFh/dHGLznW+hn/sBL r7Eq5J3FvSgDkoBXBI2jM+Zvcb0LuHZidv5Pwia8Z1a9suN8aoQlInwLICKNdLhNv5M/ vwyCsoiroXU31Z6JWqi2VWvdjx0j9tu8L07q1ZGpnKexnbeTuGIr+ltCV5kZNwXH1Fyc cM6g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w17-v6si13941674pgm.93.2018.10.16.06.35.46; Tue, 16 Oct 2018 06:35:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727223AbeJPV0P (ORCPT + 32 others); Tue, 16 Oct 2018 17:26:15 -0400 Received: from foss.arm.com ([217.140.101.70]:36424 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727003AbeJPV0O (ORCPT ); Tue, 16 Oct 2018 17:26:14 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2CF67A78; Tue, 16 Oct 2018 06:35:44 -0700 (PDT) Received: from sugar.kfn.arm.com (unknown [10.50.4.176]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BEC0A3F5D3; Tue, 16 Oct 2018 06:35:41 -0700 (PDT) From: Gilad Ben-Yossef To: Herbert Xu , "David S. Miller" , Rob Herring , Mark Rutland Cc: Ofir Drang , Yael Chemla , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] crypto: ccree: add support for CryptoCell 713 Date: Tue, 16 Oct 2018 14:35:31 +0100 Message-Id: <1539696935-4433-2-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539696935-4433-1-git-send-email-gilad@benyossef.com> References: <1539696935-4433-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Arm TrustZone CryptoCell 713. Note that this patch just enables using a 713 in backwards compatible mode to 712. Newer 713 specific features will follow. Signed-off-by: Gilad Ben-Yossef --- drivers/crypto/Kconfig | 2 +- drivers/crypto/ccree/cc_driver.c | 23 +++++++++++++++-------- drivers/crypto/ccree/cc_driver.h | 5 +++-- 3 files changed, 19 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index a8c4ce0..bea4de6 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -754,7 +754,7 @@ config CRYPTO_DEV_CCREE help Say 'Y' to enable a driver for the REE interface of the Arm TrustZone CryptoCell family of processors. Currently the - CryptoCell 712, 710 and 630 are supported. + CryptoCell 713, 712, 710 and 630 are supported. Choose this if you wish to use hardware acceleration of cryptographic operations on the system REE. If unsure say Y. diff --git a/drivers/crypto/ccree/cc_driver.c b/drivers/crypto/ccree/cc_driver.c index 1ff229c..630c598 100644 --- a/drivers/crypto/ccree/cc_driver.c +++ b/drivers/crypto/ccree/cc_driver.c @@ -43,6 +43,10 @@ struct cc_hw_data { /* Hardware revisions defs. */ +static const struct cc_hw_data cc713_hw = { + .name = "713", .rev = CC_HW_REV_713 +}; + static const struct cc_hw_data cc712_hw = { .name = "712", .rev = CC_HW_REV_712, .sig = 0xDCC71200U }; @@ -56,6 +60,7 @@ static const struct cc_hw_data cc630p_hw = { }; static const struct of_device_id arm_ccree_dev_of_match[] = { + { .compatible = "arm,cryptocell-713-ree", .data = &cc713_hw }, { .compatible = "arm,cryptocell-712-ree", .data = &cc712_hw }, { .compatible = "arm,cryptocell-710-ree", .data = &cc710_hw }, { .compatible = "arm,cryptocell-630p-ree", .data = &cc630p_hw }, @@ -297,15 +302,17 @@ static int init_cc_resources(struct platform_device *plat_dev) return rc; } - /* Verify correct mapping */ - signature_val = cc_ioread(new_drvdata, new_drvdata->sig_offset); - if (signature_val != hw_rev->sig) { - dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", - signature_val, hw_rev->sig); - rc = -EINVAL; - goto post_clk_err; + if (hw_rev->rev <= CC_HW_REV_712) { + /* Verify correct mapping */ + signature_val = cc_ioread(new_drvdata, new_drvdata->sig_offset); + if (signature_val != hw_rev->sig) { + dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", + signature_val, hw_rev->sig); + rc = -EINVAL; + goto post_clk_err; + } + dev_dbg(dev, "CC SIGNATURE=0x%08X\n", signature_val); } - dev_dbg(dev, "CC SIGNATURE=0x%08X\n", signature_val); /* Display HW versions */ dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n", diff --git a/drivers/crypto/ccree/cc_driver.h b/drivers/crypto/ccree/cc_driver.h index d608a4f..a06e5c9 100644 --- a/drivers/crypto/ccree/cc_driver.h +++ b/drivers/crypto/ccree/cc_driver.h @@ -36,12 +36,13 @@ extern bool cc_dump_desc; extern bool cc_dump_bytes; -#define DRV_MODULE_VERSION "4.0" +#define DRV_MODULE_VERSION "5.0" enum cc_hw_rev { CC_HW_REV_630 = 630, CC_HW_REV_710 = 710, - CC_HW_REV_712 = 712 + CC_HW_REV_712 = 712, + CC_HW_REV_713 = 713 }; #define CC_COHERENT_CACHE_PARAMS 0xEEE From patchwork Tue Oct 16 13:35:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 148941 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp5101046lji; Tue, 16 Oct 2018 06:35:55 -0700 (PDT) X-Google-Smtp-Source: ACcGV62Bevx4knWOBWaYZd2AFOKUUDjtkaBDJdGFgnZsH8B5kqjFRPWNLiN45IE+crjuzKi+/MP8 X-Received: by 2002:a62:8d16:: with SMTP id z22-v6mr22033877pfd.185.1539696955094; Tue, 16 Oct 2018 06:35:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539696955; cv=none; d=google.com; s=arc-20160816; b=chCdYhPjqHKU/XssgS6lTpcP3TLiFo2FrBBLt3uW9tQMYFjtKw0mATCHbLu1RfyzER Y7+47ap9EbDA6UL0DT7Bww5Nuy5ocvJxFqKfwHX/kBhDFyoJuipNJLH3H9LrZ1qhdfqi WjlNTi8E+gcSnWbNHwtSffpyjwIY/752LOdj1gOj235RnknxsKAp9SNkRvLz/qlC4/dY NjmD9HdIjB3sPi5Yl7aA+kv81Y9JRV/JtTgON83765hW9Bd43p+yYqu/LXS08dvAASMV 0EtV7F8KaWO2xNWbSRdcyf125DBP5EEifEmWF7a2SORU3gjIxu7muMM4pTFX6uTme1b5 42xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=Vc0XTU2oyh8iqIRaqyIRa7FbsqF3+3V4ncI+Kau+J1g=; b=TKNwv8fE9dGA3jy3QiB1RNzWhD+CAt1/fPQs2O3t9/1idaeguEaRxcHq5KiBcQSRdw +469TV5wZKKtSsJJ+zqn/ogNYcgwZDqdLdYgcFQwpd/2uH2OpqVfrBAUff/8n/g0YBtb JtLbsAZaKv7TQF9ya3YN8TC9YGrRlLiycBbyL+qle7P9NnQD9ccDKIJqk9FF+IEKC1OE 4NVwZYLavTKQ5RpRK+hpvRBdRC6FfZ76qdosDSbx5z1Qtp4W73tOD8mbsdFl/C2poKZt hSV7YSYQ5KQALYQule+L9a5ROGCESuz4gMyh1tl5V16JNSQ6hri9rp7c5KCiMrynJpIS Y7ew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w17-v6si13941674pgm.93.2018.10.16.06.35.51; Tue, 16 Oct 2018 06:35:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727254AbeJPV0T (ORCPT + 32 others); Tue, 16 Oct 2018 17:26:19 -0400 Received: from foss.arm.com ([217.140.101.70]:36436 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727003AbeJPV0S (ORCPT ); Tue, 16 Oct 2018 17:26:18 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 677A01596; Tue, 16 Oct 2018 06:35:48 -0700 (PDT) Received: from sugar.kfn.arm.com (unknown [10.50.4.176]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2C84A3F5D3; Tue, 16 Oct 2018 06:35:45 -0700 (PDT) From: Gilad Ben-Yossef To: Herbert Xu , "David S. Miller" , Rob Herring , Mark Rutland Cc: Ofir Drang , Yael Chemla , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] crypto: ccree: add dt bindings for ccree 713 Date: Tue, 16 Oct 2018 14:35:32 +0100 Message-Id: <1539696935-4433-3-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539696935-4433-1-git-send-email-gilad@benyossef.com> References: <1539696935-4433-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add device tree bindings associating Arm TrustZone CryptoCell 713 with the ccree driver. Signed-off-by: Gilad Ben-Yossef --- Documentation/devicetree/bindings/crypto/arm-cryptocell.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt index 999fb2a..880de07 100644 --- a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt +++ b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt @@ -1,8 +1,9 @@ Arm TrustZone CryptoCell cryptographic engine Required properties: -- compatible: Should be one of: "arm,cryptocell-712-ree", - "arm,cryptocell-710-ree" or "arm,cryptocell-630p-ree". +- compatible: Should be one of: "arm,cryptocell-713-ree", + "arm,cryptocell-712-ree", "arm,cryptocell-710-ree" or + "arm,cryptocell-630p-ree". - reg: Base physical address of the engine and length of memory mapped region. - interrupts: Interrupt number for the device. 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[209.132.180.67]) by mx.google.com with ESMTP id w17-v6si13941674pgm.93.2018.10.16.06.35.55; Tue, 16 Oct 2018 06:35:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727274AbeJPV0X (ORCPT + 32 others); Tue, 16 Oct 2018 17:26:23 -0400 Received: from foss.arm.com ([217.140.101.70]:36446 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727003AbeJPV0X (ORCPT ); Tue, 16 Oct 2018 17:26:23 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D8B2415AB; Tue, 16 Oct 2018 06:35:52 -0700 (PDT) Received: from sugar.kfn.arm.com (unknown [10.50.4.176]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9D6563F5D3; Tue, 16 Oct 2018 06:35:50 -0700 (PDT) From: Gilad Ben-Yossef To: Herbert Xu , "David S. Miller" , Rob Herring , Mark Rutland Cc: Ofir Drang , Yael Chemla , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] crypto: ccree: add SM4 support Date: Tue, 16 Oct 2018 14:35:33 +0100 Message-Id: <1539696935-4433-4-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539696935-4433-1-git-send-email-gilad@benyossef.com> References: <1539696935-4433-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for SM4 cipher in CryptoCell 713. Signed-off-by: Gilad Ben-Yossef --- drivers/crypto/Kconfig | 1 + drivers/crypto/ccree/cc_cipher.c | 66 +++++++++++++++++++++++++++++++++ drivers/crypto/ccree/cc_hw_queue_defs.h | 3 ++ 3 files changed, 70 insertions(+) -- 2.7.4 diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index bea4de6..c7e6f5d 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -751,6 +751,7 @@ config CRYPTO_DEV_CCREE select CRYPTO_ECB select CRYPTO_CTR select CRYPTO_XTS + select CRYPTO_SM4 help Say 'Y' to enable a driver for the REE interface of the Arm TrustZone CryptoCell family of processors. Currently the diff --git a/drivers/crypto/ccree/cc_cipher.c b/drivers/crypto/ccree/cc_cipher.c index 7623b299..989e70f 100644 --- a/drivers/crypto/ccree/cc_cipher.c +++ b/drivers/crypto/ccree/cc_cipher.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "cc_driver.h" @@ -83,6 +84,9 @@ static int validate_keys_sizes(struct cc_cipher_ctx *ctx_p, u32 size) if (size == DES3_EDE_KEY_SIZE || size == DES_KEY_SIZE) return 0; break; + case S_DIN_to_SM4: + if (size == SM4_KEY_SIZE) + return 0; default: break; } @@ -122,6 +126,17 @@ static int validate_data_size(struct cc_cipher_ctx *ctx_p, if (IS_ALIGNED(size, DES_BLOCK_SIZE)) return 0; break; + case S_DIN_to_SM4: + switch (ctx_p->cipher_mode) { + case DRV_CIPHER_CTR: + return 0; + case DRV_CIPHER_ECB: + case DRV_CIPHER_CBC: + if (IS_ALIGNED(size, SM4_BLOCK_SIZE)) + return 0; + default: + break; + } default: break; } @@ -522,6 +537,9 @@ static void cc_setup_cipher_data(struct crypto_tfm *tfm, case S_DIN_to_DES: flow_mode = DIN_DES_DOUT; break; + case S_DIN_to_SM4: + flow_mode = DIN_SM4_DOUT; + break; default: dev_err(dev, "invalid flow mode, flow_mode = %d\n", flow_mode); return; @@ -1324,6 +1342,54 @@ static const struct cc_alg_template skcipher_algs[] = { .flow_mode = S_DIN_to_DES, .min_hw_rev = CC_HW_REV_630, }, + { + .name = "cbc(sm4)", + .driver_name = "cbc-sm4-ccree", + .blocksize = SM4_BLOCK_SIZE, + .template_skcipher = { + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, + .min_keysize = SM4_KEY_SIZE, + .max_keysize = SM4_KEY_SIZE, + .ivsize = SM4_BLOCK_SIZE, + }, + .cipher_mode = DRV_CIPHER_CBC, + .flow_mode = S_DIN_to_SM4, + .min_hw_rev = CC_HW_REV_713, + }, + { + .name = "ecb(sm4)", + .driver_name = "ecb-sm4-ccree", + .blocksize = SM4_BLOCK_SIZE, + .template_skcipher = { + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, + .min_keysize = SM4_KEY_SIZE, + .max_keysize = SM4_KEY_SIZE, + .ivsize = 0, + }, + .cipher_mode = DRV_CIPHER_ECB, + .flow_mode = S_DIN_to_SM4, + .min_hw_rev = CC_HW_REV_713, + }, + { + .name = "ctr(sm4)", + .driver_name = "ctr-sm4-ccree", + .blocksize = SM4_BLOCK_SIZE, + .template_skcipher = { + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, + .min_keysize = SM4_KEY_SIZE, + .max_keysize = SM4_KEY_SIZE, + .ivsize = SM4_BLOCK_SIZE, + }, + .cipher_mode = DRV_CIPHER_CTR, + .flow_mode = S_DIN_to_SM4, + .min_hw_rev = CC_HW_REV_713, + }, }; static struct cc_crypto_alg *cc_create_alg(const struct cc_alg_template *tmpl, diff --git a/drivers/crypto/ccree/cc_hw_queue_defs.h b/drivers/crypto/ccree/cc_hw_queue_defs.h index a091ae5..6bd1922 100644 --- a/drivers/crypto/ccree/cc_hw_queue_defs.h +++ b/drivers/crypto/ccree/cc_hw_queue_defs.h @@ -107,6 +107,7 @@ enum cc_flow_mode { AES_to_AES_to_HASH_and_DOUT = 13, AES_to_AES_to_HASH = 14, AES_to_HASH_and_AES = 15, + DIN_SM4_DOUT = 16, DIN_AES_AESMAC = 17, HASH_to_DOUT = 18, /* setup flows */ @@ -114,9 +115,11 @@ enum cc_flow_mode { S_DIN_to_AES2 = 33, S_DIN_to_DES = 34, S_DIN_to_RC4 = 35, + S_DIN_to_SM4 = 36, S_DIN_to_HASH = 37, S_AES_to_DOUT = 38, S_AES2_to_DOUT = 39, + S_SM4_to_DOUT = 40, S_RC4_to_DOUT = 41, S_DES_to_DOUT = 42, S_HASH_to_DOUT = 43,