From patchwork Tue Oct 23 18:17:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149462 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1032232ljp; Tue, 23 Oct 2018 11:19:36 -0700 (PDT) X-Google-Smtp-Source: ACcGV60cgC7T0Bag3WhCu8+Rl23Ck1UrQb24hCGgNRC3sxLW0LWH7M5TQNzfjg9Y/DLgANpN7qpl X-Received: by 2002:a25:b94a:: with SMTP id s10-v6mr37108589ybm.130.1540318776340; Tue, 23 Oct 2018 11:19:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540318776; cv=none; d=google.com; s=arc-20160816; b=kn2BSfW457zTlzKzOGrKRIn/TH3N7q+xtl3FwGM95B00FBdiFfIbF75vqa94Tz2N0y 2wbIHhWCZT9vF9kYQxe6J0pnUfGNgPFV4kZI3gOy/bC+W7FXvM9eBft11DGbt5gzhOzN 13pplVH1eClTHYAI/4LLA5NhfoWoYcJgYfA+Olq3UONQeCQrZfARZ120og76HigUwfTL vQkBCm7uxdbJO/EYWlB4vbtP7PyuyK92O4CNEbUFh9Z7otANr4U8HJGtNcbr6/M/mqDc ofjAiKdt2JjCKOd7/WkEbB4lePaTGjTIn8eY4mBldm+x3v17Bzl50y1jnWwtSp59m4IN xlkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=1lwhZ29RAETizYYpikyyn2KC4scGM1EuddCNav2/QD0=; b=cO+72rCjWQGjsobfN4+Ydlx7Je7HeRc2xHNedlz3GjflpXF9ruquccPILc8x7XdntE XAhP0R8FdEMDOhfYE4v89RN+nMC5PlATRx4fO6X23NQt8saz6iHDPr1hsF8kLpTaj4dF HGT5UdAk0dNrd9v5EZonVLgmVarx6yGfUBeUVezTep8V1kj7nbgO5FQmKftDtWFkviG5 5NWnDVm/EM2avutrnZRQi+KegdtDEGoSuPr7qOxbsYARJ05ShFDyw3RNrNfr6Ec9Bxl3 zoBRRYc5h1uvsfkD0/AF5eFdDzzN55S5VSRnv+SCm4z2mOWCyi4v78Vrci4KNbgJ/8sJ 4+vQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 85-v6si1351364ywp.130.2018.10.23.11.19.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 11:19:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F3-0006Of-RF; Tue, 23 Oct 2018 18:17:21 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F2-0006OV-Lv for xen-devel@lists.xen.org; Tue, 23 Oct 2018 18:17:20 +0000 X-Inumbo-ID: 16127088-d6f0-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 16127088-d6f0-11e8-a6a9-d7ebe60f679a; Tue, 23 Oct 2018 18:18:48 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 712AEEBD; Tue, 23 Oct 2018 11:17:18 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8604C3F5D3; Tue, 23 Oct 2018 11:17:17 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 23 Oct 2018 19:17:06 +0100 Message-Id: <20181023181709.11883-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181023181709.11883-1-julien.grall@arm.com> References: <20181023181709.11883-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 1/4] xen/arm: gic: Ensure we have an ISB between ack and do_IRQ() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Devices that expose their interrupt status registers via system registers (e.g. Statistical profiling, CPU PMU, DynamIQ PMU, arch timer, vgic (although unused by Linux), ...) rely on a context synchronising operation on the CPU to ensure that the updated status register is visible to the CPU when handling the interrupt. This usually happens as a result of taking the IRQ exception in the first place, but there are two race scenarios where this isn't the case. For example, let's say we have two peripherals (X and Y), where Y uses a system register for its interrupt status. Case 1: 1. CPU takes an IRQ exception as a result of X raising an interrupt 2. Y then raises its interrupt line, but the update to its system register is not yet visible to the CPU 3. The GIC decides to expose Y's interrupt number first in the Ack register 4. The CPU runs the IRQ handler for Y, but the status register is stale Case 2: 1. CPU takes an IRQ exception as a result of X raising an interrupt 2. CPU reads the interrupt number for X from the Ack register and runs its IRQ handler 3. Y raises its interrupt line and the Ack register is updated, but again, the update to its system register is not yet visible to the CPU. 4. Since the GIC drivers poll the Ack register, we read Y's interrupt number and run its handler without a context synchronisation operation, therefore seeing the stale register value. In either case, we run the risk of missing an IRQ. This patch solves the problem by ensuring that we execute an ISB in the GIC drivers prior to invoking the interrupt handler. Based on Linux commit 39a06b67c2c1256bcf2361a1f67d2529f70ab206 "irqchip/gic: Ensure we have an ISB between ack and ->handle_irq". Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Acked-by: Stefano Stabellini --- This patch is a candidate for backporting up to Xen 4.9. --- xen/arch/arm/gic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 8d7e491060..305fbd66dd 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -388,12 +388,14 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq) if ( likely(irq >= 16 && irq < 1020) ) { local_irq_enable(); + isb(); do_IRQ(regs, irq, is_fiq); local_irq_disable(); } else if ( is_lpi(irq) ) { local_irq_enable(); + isb(); gic_hw_ops->do_LPI(irq); local_irq_disable(); } From patchwork Tue Oct 23 18:17:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149463 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1032278ljp; Tue, 23 Oct 2018 11:19:40 -0700 (PDT) X-Google-Smtp-Source: ACcGV638dQHxOEp10/Z44ejj6aeiIj4QVDXs0XIJkTWII/RZs9JoOF+J0yG4i0FFfzOcTKH9JwfQ X-Received: by 2002:a25:21d7:: with SMTP id h206-v6mr37258890ybh.16.1540318780169; Tue, 23 Oct 2018 11:19:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540318780; cv=none; d=google.com; s=arc-20160816; b=D4LKTNPc0iN6J5BCJp0GN/GWKgTSpqbmyfkJJQUaDFjFQKI7LWaVoPtcnG8yUI6W06 +4SC201AyQoHJFh6wYI8pdRA5/ApAz1daWVDptCYylqtRfCIo1MhN9FZJdHEhzCUcsjs PpR/GAqBmE0v3KxfSlVHBrncttm4YDF/IHGsKgs92kHeUwhtQLTiFMCXZiA0/HHRR5FP BbQ00sTsgOl+hABc8tTfjKGifrWTLEk1aEHEcDPmL+SqJnF6yk9Hbk+Zi8hZWZsnxa+N gzx3SVZYULBDc7GGuow2q+8IKYVMHrKjYGElTmquzMZXgIcB13ZqkHTvG04nQlkqxCEO hP1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=w+A9x2To7WLLw4oFD75Pu6RJiryrp5G1ckkIivDw+dM=; b=zd6E2rA9LsWoFrkSZNE68ALNIxRvHLADBBnkhANDMHE9/hSY+v605rMyqgkqz2eLTP StDVH+hZRWcAnjh5qyVchAOCicRcLHkp1UsDT/6ow/PhkSdTRtmHflrsZ0o/YXuZJBxm c3avqMhYnbtn8Etcl2PqFdQlQXD61efL8HCsbt2EIyKmdRNATIDjAX1nPe1sB8rmBFBS 4p36Or/s4SXdzBEoFO4n+o+KwztZ5p9KmBlfqsuDiYv7wFT2azyg5YKtRilS1CL6hgUa gK63cyO5RQB6QOYnThaVlPPPmeyBN4qh1FHhzRH7Szyh07x2dCguSUxO4HTHqIG1j4BF C1bQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id k186-v6si1384190ywb.357.2018.10.23.11.19.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 11:19:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F4-0006P1-Ee; Tue, 23 Oct 2018 18:17:22 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F3-0006Og-Us for xen-devel@lists.xen.org; Tue, 23 Oct 2018 18:17:21 +0000 X-Inumbo-ID: 78e08c14-d6ef-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 78e08c14-d6ef-11e8-a8a5-bc764e045a96; Tue, 23 Oct 2018 20:14:25 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9969B15AB; Tue, 23 Oct 2018 11:17:19 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AE1D53F5D3; Tue, 23 Oct 2018 11:17:18 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 23 Oct 2018 19:17:07 +0100 Message-Id: <20181023181709.11883-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181023181709.11883-1-julien.grall@arm.com> References: <20181023181709.11883-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 2/4] xen/arm: gic: Ensure ordering between read of INTACK and shared data X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When an IPI is generated by a CPU, the pattern looks roughly like: dsb(sy); On the receiving CPU we rely on the fact that, once we've taken the interrupt, then the freshly written shared data must be visible to us. Put another way, the CPU isn't going to speculate taking an interrupt. Unfortunately, this assumption turns out to be broken. Consider that CPUx wants to send an IPI to CPUy, which will cause CPUy to read some shared_data. Before CPUx has done anything, a random peripheral raises an IRQ to the GIC and the IRQ line on CPUy is raised. CPUy then takes the IRQ and starts executing the entry code, heading towards gic_handle_irq. Furthermore, let's assume that a bunch of the previous interrupts handled by CPUy were SGIs, so the branch predictor kicks in and speculates that irqnr will be <16 and we're likely to head into handle_IPI. The prefetcher then grabs a speculative copy of shared_data which contains a stale value. Meanwhile, CPUx gets round to updating shared_data and asking the GIC to send an SGI to CPUy. Internally, the GIC decides that the SGI is more important than the peripheral interrupt (which hasn't yet been ACKed) but doesn't need to do anything to CPUy, because the IRQ line is already raised. CPUy then reads the ACK register on the GIC, sees the SGI value which confirms the branch prediction and we end up with a stale shared_data value. This patch fixes the problem by adding an smp_rmb() to the IPI entry code in do_SGI. At the same time document the write barrier. Based on Linux commit f86c4fbd930ff6fecf3d8a1c313182bd0f49f496 "irqchip/gic: Ensure ordering between read of INTACK and shared data". Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Reviewed-by: Stefano Stabellini --- This patch is candidate for backporting up to Xen 4.9. --- xen/arch/arm/gic.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 305fbd66dd..30c0fba0d7 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -300,6 +300,11 @@ void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi) { ASSERT(sgi < 16); /* There are only 16 SGIs */ + /* + * Ensure that stores to Normal memory are visible to the other CPUs + * before issuing the IPI. + * Matches the read barrier in do_sgi. + */ dsb(sy); gic_hw_ops->send_SGI(sgi, SGI_TARGET_LIST, cpumask); } @@ -313,6 +318,11 @@ void send_SGI_self(enum gic_sgi sgi) { ASSERT(sgi < 16); /* There are only 16 SGIs */ + /* + * Ensure that stores to Normal memory are visible to the other CPUs + * before issuing the IPI. + * Matches the read barrier in do_sgi. + */ dsb(sy); gic_hw_ops->send_SGI(sgi, SGI_TARGET_SELF, NULL); } @@ -321,6 +331,11 @@ void send_SGI_allbutself(enum gic_sgi sgi) { ASSERT(sgi < 16); /* There are only 16 SGIs */ + /* + * Ensure that stores to Normal memory are visible to the other CPUs + * before issuing the IPI. + * Matches the read barrier in do_sgi. + */ dsb(sy); gic_hw_ops->send_SGI(sgi, SGI_TARGET_OTHERS, NULL); } @@ -356,6 +371,13 @@ static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi) /* Lower the priority */ gic_hw_ops->eoi_irq(desc); + /* + * Ensure any shared data written by the CPU sending + * the IPI is read after we've read the ACK register on the GIC. + * Matches the write barrier in send_SGI_* helpers. + */ + smp_rmb(); + switch (sgi) { case GIC_SGI_EVENT_CHECK: From patchwork Tue Oct 23 18:17:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149461 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1032189ljp; Tue, 23 Oct 2018 11:19:34 -0700 (PDT) X-Google-Smtp-Source: ACcGV60Z6rKWAf228uvqZ8gNc54o6fvFqkHAYAItB5hwAy40AJ2qtdyiR1g93UrJS82LGrSCGEPH X-Received: by 2002:a81:7109:: with SMTP id m9-v6mr36292521ywc.351.1540318773898; Tue, 23 Oct 2018 11:19:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540318773; cv=none; d=google.com; s=arc-20160816; b=F6Q+f53qTJPknKc1Uz/zMiujf+mxr/GaZW7tygZI/0PssjyW7917rO+EjQVyiQU7ge 7Li44y2SdPOluoiq6c9DOddfYuO/bNRZxbc8l60sG0zJZclBVbKTPUHO2YvisLVpPbIE 6vTv1nL6vtN/7ujBLsTuT7NsZjPa+qMG7sx5xVX+UUrFewTmnTPUQNy93fAHj0fAtDmX XgDXutBCzxXWv2bnz3WKChKpTEsHvLYtAnIF9To7qejnyfxrE3lrliV5wt4e0SKTtl6I c7XaphHC/P+HQtMuk5tizDJYF60eSBS/vi+VItvSw5IO/zXe9qCigU/CxPCX98VBMIR5 p3tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=M5SlpUZU9hUK8HZs6RYBrjyYnz8jWu2b9xi9i9M0TrA=; b=kbktxn6f5vlplDvjBNy45chV8K8dWXAtSVJItst8KS34UMZLtqFQTkLITT/9e+bBcA 1aSfLSl87vRge04rX/SpYe02TWBNJp6VIY2xhPgN0TwRq0AN+RsUVtu2QImF/fiC3gWs poDcZP1J3bfe9I9vIyhrwEEp16etDvCsWJHg2UqusqIWktQB0zosnKLYqeTvByRJ3f8h 8y4dcJeUEIY69W5+bCJlybtCXmCALRei4h99IBbS5uQgKHIxCAjbBImUzQG2JwyBmWMg wc36TU4cl7mluVT23dq+fM8v5fVLg/X4lYT3qHYExod6BRxTYA9dhBhG4jpBHwfM1kdO lKRw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 130-v6si1248411ywk.405.2018.10.23.11.19.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 11:19:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F4-0006P7-O2; Tue, 23 Oct 2018 18:17:22 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F4-0006Ok-1b for xen-devel@lists.xen.org; Tue, 23 Oct 2018 18:17:22 +0000 X-Inumbo-ID: 1784ef38-d6f0-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 1784ef38-d6f0-11e8-a6a9-d7ebe60f679a; Tue, 23 Oct 2018 18:18:51 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CA693A78; Tue, 23 Oct 2018 11:17:20 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D647E3F5D3; Tue, 23 Oct 2018 11:17:19 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 23 Oct 2018 19:17:08 +0100 Message-Id: <20181023181709.11883-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181023181709.11883-1-julien.grall@arm.com> References: <20181023181709.11883-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 3/4] xen/arm: gic: Remove duplicated comment in do_sgi X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Acked-by: Stefano Stabellini --- xen/arch/arm/gic.c | 1 - 1 file changed, 1 deletion(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 30c0fba0d7..0108e9603c 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -363,7 +363,6 @@ void gic_disable_cpu(void) static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi) { - /* Lower the priority */ struct irq_desc *desc = irq_to_desc(sgi); perfc_incr(ipis); From patchwork Tue Oct 23 18:17:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149464 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1032290ljp; Tue, 23 Oct 2018 11:19:40 -0700 (PDT) X-Google-Smtp-Source: AJdET5fYZTnQkilJWDNRs1NOprJrz05UpTcsEwuWDzdT6KZOA9i5P8ssKw6M0uNc7WIi0PDiuzV1 X-Received: by 2002:a5b:187:: with SMTP id r7-v6mr12512149ybl.517.1540318780770; Tue, 23 Oct 2018 11:19:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540318780; cv=none; d=google.com; s=arc-20160816; b=Rd3SfZQ+ZU628xBneqgcUpedPb9XdpZJnUXD0URJtxJDUQgerHEuKrKieOQ1ysS5V2 ynkDJdlP0CQj25Ez4qbAOTNin8czQjFy8ypF8IOkPQIf7CpM6n1SHPffQbJbZ+w5oMWx 7ai2RMw1Lc7Nh/DKaDoCUZfG6LG2W/HCG022zDQdpiAQOX9bOTAjletyCnMKgMzh1kRt F3/23bi8af7Mh2pvSkgTygwVDAYGeozplObErDdV/T3gXy0I2qn77KZPXFtTQe9NZWjb /MioGi/QzhTsV7+XMxisPCek7kwDTfvqE3XF/PLndq3+bZItLPhhejn2KjnV5phZA/rg B7bA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=wRdQpm+EdUVxlAk/sbCSeyXXa3zeQJlmBECWfXNpdVI=; b=rwX/OsHjFkOVtiG4Pf1lMoIm8CxvoT1Vwbx23irP4isrJ/eba9WL+si2+/E1GmPzuJ 9u0BvKCmmYQe0J0FyA2D3qyFAxuD61s50ZnsobtHfNAyQkuHYQrWbAr6Qlq8GQptl4Qt owdprsg2iWRzn/Pvla+NCcwUpPzIEHKZt7v3AcZrQEUOhXF33uA2W3FwgE/vXSHAFjLK XzSSRrto02hoxfkVEJV9eI++i2SYPVAmxYLsVCOMoCiMaebJITnKdLBtuBBtL78wVK9+ VZR0ZP6q5Ol9E93y/8i/ba//yjtZegRuqQ2UY4Wvp/SBeIQjByP/gOZM2jZoSBFJpvY8 1zfg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d186-v6si1337590ywe.352.2018.10.23.11.19.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 11:19:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F7-0006Py-6O; Tue, 23 Oct 2018 18:17:25 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F5-0006PD-90 for xen-devel@lists.xen.org; Tue, 23 Oct 2018 18:17:23 +0000 X-Inumbo-ID: 183798cf-d6f0-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 183798cf-d6f0-11e8-a6a9-d7ebe60f679a; Tue, 23 Oct 2018 18:18:52 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F28F6EBD; Tue, 23 Oct 2018 11:17:21 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 133C83F5D3; Tue, 23 Oct 2018 11:17:20 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 23 Oct 2018 19:17:09 +0100 Message-Id: <20181023181709.11883-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181023181709.11883-1-julien.grall@arm.com> References: <20181023181709.11883-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 4/4] xen/arm: gic: Relax barrier when sending an SGI X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When sending an SGI to another CPU, we require a barrier to ensure that any pending stores to normal memory are made visible to the recipient before the interrupt arrives. For GICv2, rather than using dsb(sy) before writel_gicd, we can instead use dsb(ishst), since we just need to ensure that any pending normal writes are visible within the inner-shareable domain before we poke the GIC. With this observation, we can then further weaken the barrier to a dmb(ishst), since other CPUs in the inner-shareable domain must observe the write to the distributor before the SGI is generated. A DMB instruction can be used to ensure the relative order of only memory accesses before and after the barrier. Since writes to system registers are not memory operations, barrier DMB is not sufficient for observalibility of memory accesses that occur before ICC_SGI1R_EL1 (GICv3). For GICv3, a DSB instruction ensures that no instructions that appear in program order after the DSB instruction, can execute until the DSB instruction has completed. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic-v2.c | 6 ++++++ xen/arch/arm/gic-v3.c | 6 ++++++ xen/arch/arm/gic.c | 18 ------------------ 3 files changed, 12 insertions(+), 18 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index e7eb01f30a..1a744c576f 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -455,6 +455,12 @@ static void gicv2_send_SGI(enum gic_sgi sgi, enum gic_sgi_mode irqmode, unsigned int mask = 0; cpumask_t online_mask; + /* + * Ensure that stores to Normal memory are visible to the other CPUs + * before they observe us issuing the IPI. + */ + dmb(ishst); + switch ( irqmode ) { case SGI_TARGET_OTHERS: diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 2952335d05..a0a1a45ba7 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -986,6 +986,12 @@ static void gicv3_send_sgi_list(enum gic_sgi sgi, const cpumask_t *cpumask) static void gicv3_send_sgi(enum gic_sgi sgi, enum gic_sgi_mode mode, const cpumask_t *cpumask) { + /* + * Ensure that stores to Normal memory are visible to the other CPUs + * before issuing the IPI. + */ + wmb(); + switch ( mode ) { case SGI_TARGET_OTHERS: diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 0108e9603c..077b941b79 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -300,12 +300,6 @@ void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi) { ASSERT(sgi < 16); /* There are only 16 SGIs */ - /* - * Ensure that stores to Normal memory are visible to the other CPUs - * before issuing the IPI. - * Matches the read barrier in do_sgi. - */ - dsb(sy); gic_hw_ops->send_SGI(sgi, SGI_TARGET_LIST, cpumask); } @@ -318,12 +312,6 @@ void send_SGI_self(enum gic_sgi sgi) { ASSERT(sgi < 16); /* There are only 16 SGIs */ - /* - * Ensure that stores to Normal memory are visible to the other CPUs - * before issuing the IPI. - * Matches the read barrier in do_sgi. - */ - dsb(sy); gic_hw_ops->send_SGI(sgi, SGI_TARGET_SELF, NULL); } @@ -331,12 +319,6 @@ void send_SGI_allbutself(enum gic_sgi sgi) { ASSERT(sgi < 16); /* There are only 16 SGIs */ - /* - * Ensure that stores to Normal memory are visible to the other CPUs - * before issuing the IPI. - * Matches the read barrier in do_sgi. - */ - dsb(sy); gic_hw_ops->send_SGI(sgi, SGI_TARGET_OTHERS, NULL); }