From patchwork Tue Sep 14 02:55:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 511022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CAC7C433EF for ; Tue, 14 Sep 2021 02:56:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 73C86610FB for ; Tue, 14 Sep 2021 02:56:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238226AbhINC5X (ORCPT ); Mon, 13 Sep 2021 22:57:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238100AbhINC5V (ORCPT ); Mon, 13 Sep 2021 22:57:21 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D936C061574 for ; Mon, 13 Sep 2021 19:56:04 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id e16so10780101pfc.6 for ; Mon, 13 Sep 2021 19:56:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Dn3xckHSVXxqG47sII5jEqzc6vxhCTbWGe5zWY1u2no=; b=JAr+HdDLsqwG1b4VQlMVSfDoeeLd+Ze/oCZkN2jLWc+Mqp63OZoC7P4zLxauacTJIH 6/lGImirLkQ659hQ+pfxFXLAQZz7LdubpUHB25KYMrUYPmgAijzlOxS0EFt5EOztXXFu JGKpjMHSajuBVQ8EKMTDy+zmdwTNAOQ8dyv0wAtxjNPgDMk7K0jxyJBscK1+ylxtj3RS 3Dx9ksgKIbu1PT7R6E7lDvHg/O7KOEOHnCXUPufe8L9FzJp3c9/4CeQIOXJjlR/0pprZ szEZeqRPhHyPqJmfIju8BGVrFTCSn/kNHquDhnCJ44SZ719ErSeUOJWvfHeD5Hde7ByU gHRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dn3xckHSVXxqG47sII5jEqzc6vxhCTbWGe5zWY1u2no=; b=3WykE5ZkYvLDWtnoHoHqHDQNDEUjRRyUAbo+fSMQ/7Qo7nlVEtCNdIZtcuRfmPQpox tMU5VMgpPWonntcNVdarmjOJtgF9YWA/0kmpGW7pO9jHlH5zyAtcKL96HzX8uni75YK1 pepIJ0Ct/c4wsYFbNVmRyTp0/wyJ17/ZX6lgkae/C8A27baddVvOWDtszpMJDL15uqQV omARv82x533Ax5X5BIfkQVKKQq+XKOA8OvurjDNUXNaLy4rpxphXqx0Z5UOaH7u+ziWU BWgnuxGEGiaO/N8B3bHHYsPQP7MgDLUJPo3p/oCl4wtYpE+jEQBs5/Gxgj5dluS+SE2h 6HeA== X-Gm-Message-State: AOAM533YTC8ySbTKMyRdfxB6J/bjrUQvoBiTdvJ8mjsxZ5HLBGty5dQM DXuOPhAjn5KGdDFqYjSB8njGQA== X-Google-Smtp-Source: ABdhPJzd1G7t0NmUtr9LZzb6c6zGc7P1e8tXFIKnFC8JpVDcFGlLop1cDWW+lULZWvfmLrc5rvR33Q== X-Received: by 2002:a05:6a00:22cd:b0:43c:9b41:e650 with SMTP id f13-20020a056a0022cd00b0043c9b41e650mr2553141pfj.60.1631588164108; Mon, 13 Sep 2021 19:56:04 -0700 (PDT) Received: from localhost.localdomain (80.251.214.228.16clouds.com. [80.251.214.228]) by smtp.gmail.com with ESMTPSA id r13sm9622654pgl.90.2021.09.13.19.56.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 19:56:03 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Rob Herring , Bjorn Andersson , Loic Poulain , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 1/3] clk: qcom: smd-rpm: Add rate hooks for clk_smd_rpm_branch_ops Date: Tue, 14 Sep 2021 10:55:52 +0800 Message-Id: <20210914025554.5686-2-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210914025554.5686-1-shawn.guo@linaro.org> References: <20210914025554.5686-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On QCM2290 platform, the clock xo_board runs at 38400000, while the child clock bi_tcxo needs to run at 19200000. That said, clk_smd_rpm_branch_ops needs the capability of setting rate. Add rate hooks into clk_smd_rpm_branch_ops to make it possible. Signed-off-by: Shawn Guo --- drivers/clk/qcom/clk-smd-rpm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 66d7807ee38e..2380e45b6247 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -416,6 +416,9 @@ static const struct clk_ops clk_smd_rpm_ops = { static const struct clk_ops clk_smd_rpm_branch_ops = { .prepare = clk_smd_rpm_prepare, .unprepare = clk_smd_rpm_unprepare, + .set_rate = clk_smd_rpm_set_rate, + .round_rate = clk_smd_rpm_round_rate, + .recalc_rate = clk_smd_rpm_recalc_rate, }; DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); From patchwork Tue Sep 14 02:55:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 511021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46D39C433EF for ; Tue, 14 Sep 2021 02:56:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D60F610FB for ; Tue, 14 Sep 2021 02:56:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238148AbhINC5g (ORCPT ); Mon, 13 Sep 2021 22:57:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238274AbhINC53 (ORCPT ); Mon, 13 Sep 2021 22:57:29 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C286C061767 for ; Mon, 13 Sep 2021 19:56:10 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id g14so10782099pfm.1 for ; Mon, 13 Sep 2021 19:56:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6z4EVDIxvmSYs4cCpIBDRML2cVV3ycANQaXgrnvaHVA=; b=n8Mu9j7bCyeMTYGI9pIjxvy3odYQeclkpbaZrvt1JTSq5xfTLG3GC7LmDlu8Zk0X6N 2ldtcBmjJzh4MgEHX6IVA1IIrLkNT9uULW0uC4K6rdSocHsmdVWJj+9jxGqZt8iQ90H2 3MKF/Tk5NVIN44zkuntaSbrwEGBdzUHjS8vu8SofW/a8I8ctAwBHiLCSzj5JCF7SCoDm DH2s5ASdoiaYM7+/A95a+D1XFP5dfKXw5RSWAtdsKce7Bjfj6S4Eevtka3OGH5hP5Otb 3WvMJUH+noKd+kFXyjxm6szqFVM4u5XQRcnYZqp9eSOuDwihYUGXXDYT3yvVOiJeglLw xRTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6z4EVDIxvmSYs4cCpIBDRML2cVV3ycANQaXgrnvaHVA=; b=p3EMSWdK1+3uwc/XZy4mUzQlYD5W6RD1efc5YoqzS+XpWhTUs//b8mP7ZzKRQZNzqZ Y3vhxBiv/cSn4o9DoB66gr/DNvGyDTC0JHeG7lBs+YeIcGAqrtKAmslqcq9iVZmkmVNm cKqFB51/RgIWNPN4p9D23z9UR1k24Owt5SUe6fDIF2q6j/aL4wSOtXkL5QkUOFI246pS kEd/i2qNhvW/Sf0/mPp/7zhFex7+3aYmCAJu7pWWhvETjvG233VhFzaUULl455eNqVUM htd/812Qown6HDDp3VG9J2BIYut71dGrOwI4msWw24GDZtpC8UnyAYP3kiuS18S0X/QJ zsGg== X-Gm-Message-State: AOAM532hthCa3FqZzE5IurRbFvGguEqFKhJX1z2abqjJX3x+wCwKgea8 QZHRI4d5cBU+RE5iJwwhUx5zVw== X-Google-Smtp-Source: ABdhPJzC3x+I0MEv0MGE/RAvJa/uIw5x37Owv5ZIgE6dUGPKxVP9w7cNqh2CPbQ7lES7DKTzv4a1Fw== X-Received: by 2002:a05:6a00:1396:b0:40d:bb7c:92d0 with SMTP id t22-20020a056a00139600b0040dbb7c92d0mr2620143pfg.38.1631588169776; Mon, 13 Sep 2021 19:56:09 -0700 (PDT) Received: from localhost.localdomain (80.251.214.228.16clouds.com. [80.251.214.228]) by smtp.gmail.com with ESMTPSA id r13sm9622654pgl.90.2021.09.13.19.56.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 19:56:09 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Rob Herring , Bjorn Andersson , Loic Poulain , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 3/3] clk: qcom: smd-rpm: Add QCM2290 RPM clock support Date: Tue, 14 Sep 2021 10:55:54 +0800 Message-Id: <20210914025554.5686-4-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210914025554.5686-1-shawn.guo@linaro.org> References: <20210914025554.5686-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for RPM-managed clocks on the QCM2290 platform. Signed-off-by: Shawn Guo --- drivers/clk/qcom/clk-smd-rpm.c | 59 ++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,rpmcc.h | 6 +++ include/linux/soc/qcom/smd-rpm.h | 2 + 3 files changed, 67 insertions(+) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 2380e45b6247..428830d800f6 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1070,6 +1070,64 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { .num_clks = ARRAY_SIZE(sm6115_clks), }; +/* QCM2290 */ +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2); +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6); + +DEFINE_CLK_SMD_RPM(qcm2290, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk, + QCOM_SMD_RPM_MEM_CLK, 1); +DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk, + QCOM_SMD_RPM_MEM_CLK, 2); + +static struct clk_smd_rpm *qcm2290_clks[] = { + [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, + [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk, + [RPM_SMD_LN_BB_CLK2] = &qcm2290_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &qcm2290_ln_bb_clk2_a, + [RPM_SMD_RF_CLK3] = &qcm2290_rf_clk3, + [RPM_SMD_RF_CLK3_A] = &qcm2290_rf_clk3_a, + [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, + [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, + [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, + [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, + [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, + [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, + [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, + [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, + [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, + [RPM_SMD_QPIC_CLK] = &qcm2290_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &qcm2290_qpic_a_clk, + [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk, + [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk, + [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk, + [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk, + [RPM_SMD_BIMC_GPU_CLK] = &qcm2290_bimc_gpu_clk, + [RPM_SMD_BIMC_GPU_A_CLK] = &qcm2290_bimc_gpu_a_clk, + [RPM_SMD_CPUSS_GNOC_CLK] = &qcm2290_cpuss_gnoc_clk, + [RPM_SMD_CPUSS_GNOC_A_CLK] = &qcm2290_cpuss_gnoc_a_clk, +}; + +static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { + .clks = qcm2290_clks, + .num_clks = ARRAY_SIZE(qcm2290_clks), +}; + static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 }, { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 }, @@ -1082,6 +1140,7 @@ static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 }, { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 }, + { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 }, { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 }, { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 }, diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index aa834d516234..fb624ff39273 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -159,5 +159,11 @@ #define RPM_SMD_SNOC_PERIPH_A_CLK 113 #define RPM_SMD_SNOC_LPASS_CLK 114 #define RPM_SMD_SNOC_LPASS_A_CLK 115 +#define RPM_SMD_HWKM_CLK 116 +#define RPM_SMD_HWKM_A_CLK 117 +#define RPM_SMD_PKA_CLK 118 +#define RPM_SMD_PKA_A_CLK 119 +#define RPM_SMD_CPUSS_GNOC_CLK 120 +#define RPM_SMD_CPUSS_GNOC_A_CLK 121 #endif diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index 60e66fc9b6bf..860dd8cdf9f3 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -38,6 +38,8 @@ struct qcom_smd_rpm; #define QCOM_SMD_RPM_IPA_CLK 0x617069 #define QCOM_SMD_RPM_CE_CLK 0x6563 #define QCOM_SMD_RPM_AGGR_CLK 0x72676761 +#define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768 +#define QCOM_SMD_RPM_PKA_CLK 0x616b70 int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, int state,