From patchwork Thu May 25 11:37:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 100496 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp719228qge; Thu, 25 May 2017 04:39:13 -0700 (PDT) X-Received: by 10.98.155.154 with SMTP id e26mr44930951pfk.24.1495712353615; Thu, 25 May 2017 04:39:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712353; cv=none; d=google.com; s=arc-20160816; b=o27R0Q8XF+8qib62A2AeI6kzl+e1+Jx9jcX2GKViXsKRdPO41xRx8Nje8/zchJ04MZ p/hi3z0+g6MAn2ogxMImjtGAB99z5ZZBvWeQfqu16O5hMte3euR04x3uHfQAYPv+xGkP m5v9+/65nXDdhg72uHhjG4+3ki3SEdqtAmB3gUzYqtqWg74I9NQ/os4d2rqSBuFUE/Ul z4Jnk9nKfnOMpEN66sMkxDoEWyff8N2/17+Ovb8pIIcLi22NU4fxjtL+5uPEk1VKAGP5 n9hH57ery0aZiwgqo74gKcYIG3vMmBwfM3221hS7hn1cWCM3dQrzq+O5idl1/2oVX7q4 7tKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=KFhkH2bz1MkYrLqoSbOgw2N+q/yUoZWKbLv2VZa7j70=; b=FKbz/ZmwV8qbZG66YQGpyY1YnTToyIJiEixljf3U6etIrVjC+yNy4cnD5StRMoBxdq rH4Q/i7l0KTo0Pw12RHXZg8z2801v7tFBuKoFtm1o1Dp2IkavAcQkLt4F6ZvnDILwEsk VE8lNfQrywKWulY/hL4Vcfg8FZiY+QfQeryPkfGOz0N8tkttPILWlvFagaB0FivFgoab OnirAcDXFD9gcOtaouxEajAqgETFSLIF0G0cEFxoVZOg/4JHGXqrKameYVVDw3gdpjlL ys3mNNNKQiulAw8zOiFVNvacE+1tAjfTIGk2y9z8HM7XMGSVxzUEYbro6EbjwpszvVUg 6ctQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c19si27611951pgk.90.2017.05.25.04.39.13; Thu, 25 May 2017 04:39:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1764911AbdEYLi5 (ORCPT + 8 others); Thu, 25 May 2017 07:38:57 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:6908 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1762786AbdEYLiq (ORCPT ); Thu, 25 May 2017 07:38:46 -0400 Received: from 172.30.72.55 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.55]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOG95728; Thu, 25 May 2017 19:38:41 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.156) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:38:30 +0800 From: Gabriele Paoloni To: , , , , , , , , CC: , , , , , , , , , , , , "zhichang.yuan" Subject: [PATCH v9 1/7] LIB: Introduce a generic PIO mapping method Date: Thu, 25 May 2017 12:37:22 +0100 Message-ID: <1495712248-5232-2-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1495712248-5232-1-git-send-email-gabriele.paoloni@huawei.com> References: <1495712248-5232-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.156] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5926C241.01D5, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: aed6b464dbf5035c6f22c5fb55a047e1 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org From: "zhichang.yuan" In 'commit 41f8bba7f555 ("of/pci: Add pci_register_io_range() and pci_pio_to_address()")' a new I/O space management was supported. With that driver, the I/O ranges configured for PCI/PCIE hosts on some architectures can be mapped to logical PIO, converted easily between CPU address and the corresponding logicial PIO. Based on this, PCI I/O devices can be accessed in a memory read/write way through the unified in/out accessors. But on some archs/platforms, there are bus hosts which access I/O peripherals with host-local I/O port addresses rather than memory addresses after memory-mapped. To support those devices, a more generic I/O mapping method is introduced here. Through this patch, both the CPU addresses and the host-local port can be mapped into the logical PIO space with different logical/fake PIOs. After this, all the I/O accesses to either PCI MMIO devices or host-local I/O peripherals can be unified into the existing I/O accessors defined in asm-generic/io.h and be redirected to the right device-specific hooks based on the input logical PIO. Signed-off-by: zhichang.yuan Signed-off-by: Gabriele Paoloni --- include/asm-generic/io.h | 50 +++++++++ include/linux/logic_pio.h | 110 ++++++++++++++++++ lib/Kconfig | 26 +++++ lib/Makefile | 2 + lib/logic_pio.c | 280 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 468 insertions(+) create mode 100644 include/linux/logic_pio.h create mode 100644 lib/logic_pio.c -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index 7ef015e..f7fbec3 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -351,6 +351,8 @@ static inline void writesq(volatile void __iomem *addr, const void *buffer, #define IO_SPACE_LIMIT 0xffff #endif +#include + /* * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be * implemented on hardware that needs an additional delay for I/O accesses to @@ -358,51 +360,75 @@ static inline void writesq(volatile void __iomem *addr, const void *buffer, */ #ifndef inb +#ifdef CONFIG_INDIRECT_PIO +#define inb logic_inb +#else #define inb inb static inline u8 inb(unsigned long addr) { return readb(PCI_IOBASE + addr); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef inw +#ifdef CONFIG_INDIRECT_PIO +#define inw logic_inw +#else #define inw inw static inline u16 inw(unsigned long addr) { return readw(PCI_IOBASE + addr); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef inl +#ifdef CONFIG_INDIRECT_PIO +#define inl logic_inl +#else #define inl inl static inline u32 inl(unsigned long addr) { return readl(PCI_IOBASE + addr); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef outb +#ifdef CONFIG_INDIRECT_PIO +#define outb logic_outb +#else #define outb outb static inline void outb(u8 value, unsigned long addr) { writeb(value, PCI_IOBASE + addr); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef outw +#ifdef CONFIG_INDIRECT_PIO +#define outw logic_outw +#else #define outw outw static inline void outw(u16 value, unsigned long addr) { writew(value, PCI_IOBASE + addr); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef outl +#ifdef CONFIG_INDIRECT_PIO +#define outl logic_outl +#else #define outl outl static inline void outl(u32 value, unsigned long addr) { writel(value, PCI_IOBASE + addr); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef inb_p @@ -459,54 +485,78 @@ static inline void outl_p(u32 value, unsigned long addr) */ #ifndef insb +#ifdef CONFIG_INDIRECT_PIO +#define insb logic_insb +#else #define insb insb static inline void insb(unsigned long addr, void *buffer, unsigned int count) { readsb(PCI_IOBASE + addr, buffer, count); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef insw +#ifdef CONFIG_INDIRECT_PIO +#define insw logic_insw +#else #define insw insw static inline void insw(unsigned long addr, void *buffer, unsigned int count) { readsw(PCI_IOBASE + addr, buffer, count); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef insl +#ifdef CONFIG_INDIRECT_PIO +#define insl logic_insl +#else #define insl insl static inline void insl(unsigned long addr, void *buffer, unsigned int count) { readsl(PCI_IOBASE + addr, buffer, count); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef outsb +#ifdef CONFIG_INDIRECT_PIO +#define outsb logic_outsb +#else #define outsb outsb static inline void outsb(unsigned long addr, const void *buffer, unsigned int count) { writesb(PCI_IOBASE + addr, buffer, count); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef outsw +#ifdef CONFIG_INDIRECT_PIO +#define outsw logic_outsw +#else #define outsw outsw static inline void outsw(unsigned long addr, const void *buffer, unsigned int count) { writesw(PCI_IOBASE + addr, buffer, count); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef outsl +#ifdef CONFIG_INDIRECT_PIO +#define outsl logic_outsl +#else #define outsl outsl static inline void outsl(unsigned long addr, const void *buffer, unsigned int count) { writesl(PCI_IOBASE + addr, buffer, count); } +#endif /* CONFIG_INDIRECT_PIO */ #endif #ifndef insb_p diff --git a/include/linux/logic_pio.h b/include/linux/logic_pio.h new file mode 100644 index 0000000..8e4dc65 --- /dev/null +++ b/include/linux/logic_pio.h @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2017 Hisilicon Limited, All Rights Reserved. + * Author: Gabriele Paoloni + * Author: Zhichang Yuan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __LINUX_LOGIC_PIO_H +#define __LINUX_LOGIC_PIO_H + +#ifdef __KERNEL__ + +#include + +#define PIO_INDIRECT 0x01UL /* indirect IO flag */ +#define PIO_CPU_MMIO 0x00UL /* memory mapped io flag */ + +struct logic_pio_hwaddr { + struct list_head list; + struct fwnode_handle *fwnode; + resource_size_t hw_start; + resource_size_t io_start; + resource_size_t size; /* range size populated */ + unsigned long flags; + + void *devpara; /* private parameter of the host device */ + struct hostio_ops *ops; /* ops operating on this node */ +}; + +struct hostio_ops { + u32 (*pfin)(void *devobj, unsigned long ptaddr, size_t dlen); + void (*pfout)(void *devobj, unsigned long ptaddr, u32 outval, + size_t dlen); + u32 (*pfins)(void *devobj, unsigned long ptaddr, void *inbuf, + size_t dlen, unsigned int count); + void (*pfouts)(void *devobj, unsigned long ptaddr, + const void *outbuf, size_t dlen, unsigned int count); +}; + +extern u8 logic_inb(unsigned long addr); +extern void logic_outb(u8 value, unsigned long addr); +extern void logic_outw(u16 value, unsigned long addr); +extern void logic_outl(u32 value, unsigned long addr); +extern u16 logic_inw(unsigned long addr); +extern u32 logic_inl(unsigned long addr); +extern void logic_outb(u8 value, unsigned long addr); +extern void logic_outw(u16 value, unsigned long addr); +extern void logic_outl(u32 value, unsigned long addr); +extern void logic_insb(unsigned long addr, void *buffer, unsigned int count); +extern void logic_insl(unsigned long addr, void *buffer, unsigned int count); +extern void logic_insw(unsigned long addr, void *buffer, unsigned int count); +extern void logic_outsb(unsigned long addr, const void *buffer, + unsigned int count); +extern void logic_outsw(unsigned long addr, const void *buffer, + unsigned int count); +extern void logic_outsl(unsigned long addr, const void *buffer, + unsigned int count); + +#ifdef CONFIG_INDIRECT_PIO +/* Below make 75% of IO Space for MMIO and the rest for Indirect IO */ +#define MMIO_UPPER_LIMIT (IO_SPACE_LIMIT - (IO_SPACE_LIMIT >> 2)) +#else +#define MMIO_UPPER_LIMIT IO_SPACE_LIMIT +#endif + +#ifdef CONFIG_LOGIC_PIO +extern struct logic_pio_hwaddr +*find_io_range_by_fwnode(struct fwnode_handle *fwnode); + +extern unsigned long logic_pio_trans_hwaddr(struct fwnode_handle *fwnode, + resource_size_t hw_addr); + +extern int logic_pio_register_range(struct logic_pio_hwaddr *newrange); +#else +static inline struct logic_pio_hwaddr +*find_io_range_by_fwnode(struct fwnode_handle *fwnode) +{ + return NULL; +} + +static inline unsigned long +logic_pio_trans_hwaddr(struct fwnode_handle *fwnode, resource_size_t hw_addr) +{ + return -1; +} + +static inline struct logic_pio_hwaddr +*logic_pio_register_range(struct logic_pio_hwaddr *newrange); +{ + return NULL; +} +#endif + +extern resource_size_t logic_pio_to_hwaddr(unsigned long pio); + +extern unsigned long logic_pio_trans_cpuaddr(resource_size_t hw_addr); + +#endif /* __KERNEL__ */ +#endif /* __LINUX_LOGIC_PIO_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 0c8b78a..503c2e0 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -59,6 +59,32 @@ config ARCH_USE_CMPXCHG_LOCKREF config ARCH_HAS_FAST_MULTIPLIER bool +config LOGIC_PIO + bool "Generic logical I/O management" + def_bool y if PCI && !X86 && !IA64 && !POWERPC + help + For some architectures, there are no IO space. To support the + accesses to legacy I/O devices on those architectures, kernel + implemented the memory mapped I/O mechanism based on bridge bus + supports. But for some buses which do not support MMIO, the + peripherals there should be accessed with device-specific way. + To abstract those different I/O accesses into unified I/O accessors, + this option provide a generic I/O space management way after mapping + the device I/O to system logical/fake I/O and help to hide all the + hardware detail. + +config INDIRECT_PIO + bool "Access I/O in non-MMIO mode" if LOGIC_PIO + help + On some platforms where no separate I/O space exist, there are I/O + hosts which can not be accessed in MMIO mode. Based on LOGIC_PIO + mechanism, the host-local I/O resource can be mapped into system + logic PIO space shared with MMIO hosts, such as PCI/PCIE, then system + can access the I/O devices with the mapped logic PIO through I/O + accessors. + This way has a little I/O performance cost. Please make sure your + devices really need this configure item enabled. + config CRC_CCITT tristate "CRC-CCITT functions" help diff --git a/lib/Makefile b/lib/Makefile index 0166fbc..1a27f6e 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -78,6 +78,8 @@ obj-$(CONFIG_HAS_IOMEM) += iomap_copy.o devres.o obj-$(CONFIG_CHECK_SIGNATURE) += check_signature.o obj-$(CONFIG_DEBUG_LOCKING_API_SELFTESTS) += locking-selftest.o +obj-$(CONFIG_LOGIC_PIO) += logic_pio.o + obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o obj-$(CONFIG_BTREE) += btree.o diff --git a/lib/logic_pio.c b/lib/logic_pio.c new file mode 100644 index 0000000..4a960cd --- /dev/null +++ b/lib/logic_pio.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2017 Hisilicon Limited, All Rights Reserved. + * Author: Gabriele Paoloni + * Author: Zhichang Yuan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +/* The unique hardware address list. */ +static LIST_HEAD(io_range_list); +static DEFINE_MUTEX(io_range_mutex); + +/* + * register a new io range node in the io range list. + * + * @newrange: pointer to the io range to be registered. + * + * returns 0 on success, the error code in case of failure + */ +int logic_pio_register_range(struct logic_pio_hwaddr *new_range) +{ + struct logic_pio_hwaddr *range; + int ret = 0; + resource_size_t start = new_range->hw_start; + resource_size_t end = new_range->hw_start + new_range->size; + resource_size_t allocated_mmio_size = 0; + resource_size_t allocated_iio_size = MMIO_UPPER_LIMIT; + + if (!new_range || !new_range->fwnode || !new_range->size) + return -EINVAL; + + mutex_lock(&io_range_mutex); + list_for_each_entry_rcu(range, &io_range_list, list) { + + if (range->fwnode == new_range->fwnode) { + /* range already there */ + ret = -EFAULT; + goto end_register; + } + if (range->flags == PIO_CPU_MMIO && + new_range->flags == PIO_CPU_MMIO) { + /* for MMIO ranges we need to check for overlap */ + if (start >= range->hw_start + range->size || + end < range->hw_start) + allocated_mmio_size += range->size; + else { + ret = -EFAULT; + goto end_register; + } + } else if (range->flags == PIO_INDIRECT && + new_range->flags == PIO_INDIRECT) { + allocated_iio_size += range->size; + } + } + + /* range not registered yet, check for available space */ + if (new_range->flags == PIO_CPU_MMIO) { + + if (allocated_mmio_size + new_range->size - 1 > + MMIO_UPPER_LIMIT) { + /* if it's too big check if 64K space can be reserved */ + if (allocated_mmio_size + SZ_64K - 1 > + MMIO_UPPER_LIMIT) { + ret = -E2BIG; + goto end_register; + } + new_range->size = SZ_64K; + pr_warn("Requested IO range too big, new size set to 64K\n"); + } + + new_range->io_start = allocated_mmio_size + new_range->size; + + } else if (new_range->flags == PIO_INDIRECT) { + + if (allocated_iio_size + new_range->size - 1 > + IO_SPACE_LIMIT) { + ret = -E2BIG; + goto end_register; + } + new_range->io_start = allocated_iio_size + new_range->size; + + } else { + /* invalid flag */ + ret = -EINVAL; + goto end_register; + } + + list_add_tail_rcu(&new_range->list, &io_range_list); + +end_register: + mutex_unlock(&io_range_mutex); + return ret; +} + +/* + * traverse the io_range_list to find the registered node whose device node + * and/or physical IO address match to. + */ +struct logic_pio_hwaddr *find_io_range_by_fwnode(struct fwnode_handle *fwnode) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (range->fwnode == fwnode) + return range; + } + return NULL; +} + +/* return a registered range given an input PIO token */ +static struct logic_pio_hwaddr *find_io_range(unsigned long pio) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (pio >= range->io_start && + pio < range->io_start + range->size) + return range; + } + pr_err("PIO entry token invalid\n"); + return NULL; +} + +/* + * Translate the input logical pio to the corresponding hardware address. + * The input pio should be unique in the whole logical PIO space. + */ +resource_size_t logic_pio_to_hwaddr(unsigned long pio) +{ + struct logic_pio_hwaddr *range; + resource_size_t hwaddr = -1; + + range = find_io_range(pio); + if (range) + hwaddr = range->hw_start + pio - range->io_start; + + return hwaddr; +} + +/* + * This function is generic for translating a hardware address to logical PIO. + * @hw_addr: the hardware address of host, can be CPU address or host-local + * address; + */ +unsigned long +logic_pio_trans_hwaddr(struct fwnode_handle *fwnode, resource_size_t addr) +{ + struct logic_pio_hwaddr *range; + + range = find_io_range_by_fwnode(fwnode); + if (!range || range->flags == PIO_CPU_MMIO) { + pr_err("range not found or invalid\n"); + return -1; + } + return addr - range->hw_start + range->io_start; +} + +unsigned long +logic_pio_trans_cpuaddr(resource_size_t addr) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (range->flags != PIO_CPU_MMIO) + continue; + if (addr >= range->hw_start && + addr < range->hw_start + range->size) + return addr - range->hw_start + + range->io_start; + } + pr_err("addr not registered in io_range_list\n"); + return -1; +} + +#if defined(CONFIG_INDIRECT_PIO) && defined(PCI_IOBASE) +#define BUILD_LOGIC_PIO(bw, type)\ +type logic_in##bw(unsigned long addr)\ +{\ + type ret = -1;\ +\ + if (addr < MMIO_UPPER_LIMIT) {\ + ret = read##bw(PCI_IOBASE + addr);\ + } else {\ + struct logic_pio_hwaddr *entry = find_io_range(addr);\ +\ + if (entry && entry->ops)\ + ret = entry->ops->pfin(entry->devpara,\ + addr, sizeof(type));\ + else\ + WARN_ON_ONCE(1);\ + } \ + return ret;\ +} \ +\ +void logic_out##bw(type value, unsigned long addr)\ +{\ + if (addr < MMIO_UPPER_LIMIT) {\ + write##bw(value, PCI_IOBASE + addr);\ + } else {\ + struct logic_pio_hwaddr *entry = find_io_range(addr);\ +\ + if (entry && entry->ops)\ + entry->ops->pfout(entry->devpara,\ + addr, value, sizeof(type));\ + else\ + WARN_ON_ONCE(1);\ + } \ +} \ +\ +void logic_ins##bw(unsigned long addr, void *buffer, unsigned int count)\ +{\ + if (addr < MMIO_UPPER_LIMIT) {\ + reads##bw(PCI_IOBASE + addr, buffer, count);\ + } else {\ + struct logic_pio_hwaddr *entry = find_io_range(addr);\ +\ + if (entry && entry->ops)\ + entry->ops->pfins(entry->devpara,\ + addr, buffer, sizeof(type), count);\ + else\ + WARN_ON_ONCE(1);\ + } \ +\ +} \ +\ +void logic_outs##bw(unsigned long addr, const void *buffer,\ + unsigned int count)\ +{\ + if (addr < MMIO_UPPER_LIMIT)\ + writes##bw(PCI_IOBASE + addr, buffer, count);\ + else {\ + struct logic_pio_hwaddr *entry = find_io_range(addr);\ +\ + if (entry && entry->ops)\ + entry->ops->pfouts(entry->devpara,\ + addr, buffer, sizeof(type), count);\ + else\ + WARN_ON_ONCE(1);\ + } \ +} + +BUILD_LOGIC_PIO(b, u8) + +EXPORT_SYMBOL(logic_inb); +EXPORT_SYMBOL(logic_outb); +EXPORT_SYMBOL(logic_insb); +EXPORT_SYMBOL(logic_outsb); + +BUILD_LOGIC_PIO(w, u16) + +EXPORT_SYMBOL(logic_inw); +EXPORT_SYMBOL(logic_outw); +EXPORT_SYMBOL(logic_insw); +EXPORT_SYMBOL(logic_outsw); + +BUILD_LOGIC_PIO(l, u32) + +EXPORT_SYMBOL(logic_inl); +EXPORT_SYMBOL(logic_outl); +EXPORT_SYMBOL(logic_insl); +EXPORT_SYMBOL(logic_outsl); +#endif /* CONFIG_INDIRECT_PIO && PCI_IOBASE */ From patchwork Thu May 25 11:37:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 100511 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp720969qge; Thu, 25 May 2017 04:44:34 -0700 (PDT) X-Received: by 10.98.130.1 with SMTP id w1mr44717121pfd.128.1495712674050; Thu, 25 May 2017 04:44:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712674; cv=none; d=google.com; s=arc-20160816; b=O3DXfMBB3Gcrmb6BJigv5CZVHvksXUK/kWXFeM4ITY2/F3s78jE8leMPw/QPyZdUTk 3czbBqX3khe83wkBBtzSN/uzqSlQM1ko4ptJGnrm+imTuv47E7IIczqKzmIFe+1FdJZK 440vpVQbTDih4A4TJwbnUM3+/nkGjVd/gXBijeg4n55SkMOni5gzR4fZyHnT5o59DvSD eGOJ5HYc4sOihm/j7urGd4PYcoKcQb0tW6fSPMA2ZifCuCB37czGMyJ4z0Xpp6fGdxdw RmZ4zZ+YxwJ+bh+Nf9aIJIyl4LXHh+6tDqe0dMGdCB30twRpEzb4cU52MWwsmnpn3u98 sjsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=GfhbMBOO1z7D+ScWCEeoNgGkRgPg/UgzCEULa9azwyI=; b=Rbgci7q56FKSKjJ7If2MJkU0t4FoyFUf17jx3lavfbY1oSXPdTzXXSozz7E3qvPv5k uKHr+KAZHnfnkuOvkbe8EbUNoj85taP1LV7lj1Z1mv/OEaAyhfzyHDycrSoKhAOVSbcP usCHumGQv5yBqCeISSrP9qa3aSrgNJOfTInaUc92QQo+Q7SZ9R4P2252QnUCwnB/1zUL kjSMBs3SLOZ+sxesp7Zj31bs5Jiq+b0bp38M+qmp2YH10mwnfB/DIXreNj75T2HUdpaA 2kJZktRU9s33zHOQStkIE+oF1guFtoWkP+Ler7p+8Uv2QT2D2OhGk8X3NIut6kg1jMrz YAkQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j91si2728606pld.115.2017.05.25.04.44.33; Thu, 25 May 2017 04:44:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1764916AbdEYLoc (ORCPT + 8 others); Thu, 25 May 2017 07:44:32 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6829 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763903AbdEYLob (ORCPT ); Thu, 25 May 2017 07:44:31 -0400 Received: from 172.30.72.53 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOF02160; Thu, 25 May 2017 19:39:22 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.156) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:39:09 +0800 From: Gabriele Paoloni To: , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v9 7/7] MANTAINERS: Add maintainer for HiSilicon LPC driver Date: Thu, 25 May 2017 12:37:28 +0100 Message-ID: <1495712248-5232-8-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1495712248-5232-1-git-send-email-gabriele.paoloni@huawei.com> References: <1495712248-5232-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.156] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5926C26A.00DD, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 910c08edf90a108b4d2eb81a8b79c539 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Added maintainer for drivers/bus/hisi_lpc.c Signed-off-by: Gabriele Paoloni --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/MAINTAINERS b/MAINTAINERS index 9e98464..8fb9006 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6061,6 +6061,14 @@ F: include/uapi/linux/if_hippi.h F: net/802/hippi.c F: drivers/net/hippi/ +HISILICON LPC BUS DRIVER +M: Gabriele Paoloni +L: linux-arm-kernel@lists.infradead.org +W: http://www.hisilicon.com +S: Maintained +F: drivers/bus/hisi_lpc.c +F: Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt + HISILICON NETWORK SUBSYSTEM DRIVER M: Yisen Zhuang M: Salil Mehta