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[209.85.220.65]) by mx.google.com with SMTPS id r205-v6sor11475077vke.56.2018.10.31.07.04.40 for (Google Transport Security); Wed, 31 Oct 2018 07:04:41 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CSbrSQHE; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rWF0dqxgEqfP5U9cY6deCiGeL5Nty3bM1X4B+VdAcLk=; b=CSbrSQHEPoDLRYKc1SpWzsUkxQ57WfCwShq0zUT6GABzzD/fn1ObgjYdvp+EWP7p5C XATJ11qvGOBVq/361jCRLnhn/PmL8wFTbTve6PAXIOHWH6dv0FYnGaqRpqW4ZkyuuwK7 HT7EgoBTgvI1lVIRdZ7j8K7zyTXdr9SmyuIME= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rWF0dqxgEqfP5U9cY6deCiGeL5Nty3bM1X4B+VdAcLk=; b=s9dFLEvqRMuOsVxKIWnyVrSJSTPQlQygVfKLbC2U52D5rPRpr+ciVvaCoYqOFb7/b5 B7fs/XOQ9JjfhjS52AHT4wN7fwH9oJ6Coi4zVreIX8EJvWlKvFuLMhvWM2Lo/Ini3hP0 bqOlZMuwXfbITRWuffzUqFoXGiupRGZLEUhoTRGXtGUzIMmlKMPUg74ZTOTAMaO9q5gU vbZpE/64WWPhEpaBH0Sm377XA6ktAA3kfbCUItEqfemE5oSYfBYwIpbkp6q6T0He0RuR +scJFqmy1n5O/G5eAm1TKBogFVDtgBvKZAjZu+qw9ISU9M3BwShelnQVtz574rB7M/av GHFA== X-Gm-Message-State: AGRZ1gKIJmukRHRyJLWaDsdYDmYWjFYK53/qREdJiXqaoYF83avxWcnj AeLWwawT68oE+kDa5f3B8lhGHYyP X-Google-Smtp-Source: AJdET5f1Oclc70QCqGAQmOTM1ng5pAPmJqx/cPIiIkq98tbnNaEnY8+de5uP3MHMlENTBh7xqGEpYA== X-Received: by 2002:a1f:a451:: with SMTP id n78mr1326650vke.37.1540994680365; Wed, 31 Oct 2018 07:04:40 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:39 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 01/18] ARM: add more CPU part numbers for Cortex and Brahma B15 CPUs Date: Wed, 31 Oct 2018 10:04:19 -0400 Message-Id: <20181031140436.2964-2-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit f5683e76f35b4ec5891031b6a29036efe0a1ff84 upstream. Add CPU part numbers for Cortex A53, A57, A72, A73, A75 and the Broadcom Brahma B15 CPU. Signed-off-by: Russell King Acked-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long --- arch/arm/include/asm/cputype.h | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.1 diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index e9d04f475929..76bb3bd060d1 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -74,8 +74,16 @@ #define ARM_CPU_PART_CORTEX_A12 0x4100c0d0 #define ARM_CPU_PART_CORTEX_A17 0x4100c0e0 #define ARM_CPU_PART_CORTEX_A15 0x4100c0f0 +#define ARM_CPU_PART_CORTEX_A53 0x4100d030 +#define ARM_CPU_PART_CORTEX_A57 0x4100d070 +#define ARM_CPU_PART_CORTEX_A72 0x4100d080 +#define ARM_CPU_PART_CORTEX_A73 0x4100d090 +#define ARM_CPU_PART_CORTEX_A75 0x4100d0a0 #define ARM_CPU_PART_MASK 0xff00fff0 +/* Broadcom cores */ +#define ARM_CPU_PART_BRAHMA_B15 0x420000f0 + #define ARM_CPU_XSCALE_ARCH_MASK 0xe000 #define ARM_CPU_XSCALE_ARCH_V1 0x2000 #define ARM_CPU_XSCALE_ARCH_V2 0x4000 From patchwork Wed Oct 31 14:04:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149821 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6835909ljp; Wed, 31 Oct 2018 07:04:42 -0700 (PDT) X-Received: by 2002:a1f:5286:: with SMTP id g128mr853835vkb.12.1540994682361; Wed, 31 Oct 2018 07:04:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994682; cv=none; d=google.com; s=arc-20160816; b=FNVJF929bua6dqY0yP52PGmCaE/PzOT8u7npyo1nS6K0Mb/7SRLSyd3+1+CPw8vlkf p4OvkFLiRKYfDkEMzJKmSEN/FqNoSEvdc3SELcTge9upp4oWJRc9i1F4KgpNJme/04MJ II6AYuJPLCzoNm7hkpT0ie7dk8YTcLNcrHmREZGO2Q5BuAc1a6r5WWUapFiZTQZ1F717 zD+oVFhrd3Um+eyrWIfSX/kxCD1j9Gg0N0EeTThelpP943AdTmWEA2/Qxrji7E6zS58B xms13yAC28LK92xZ4ZsZpk1uk9GcEma9GlfO/tOlJ85vblmGZoLIcczN6iQfweJLtHjJ f/Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZjSGP3GI5NRWS7wwGi0tHqjByJ8pD27pGt33fFGUHH0=; b=csP+xsurKW+9qbj5vs5BJRjEQ5V3bYshemGF08YU+uiacGBs48c3/e49tk0vUepVDW oMS7iXhaI/tvV5d7QPQj6H6wwKwawoA+l6RwzPEyydjt0rflZ2CFOXsdmuR+z7YmktDw e6FVLgGp619eo0M9xfrCdlObNzDZ8fM5x0O1p058AHmSZMxA0JVJ47CAjqHXvDhe+fy0 N6UJ29sj/OoxCT9wfBAtH1KEeXzeswcs3ShkxYFiM/AAAVNPMn16gURlHC/YggWu2PgS T1J82b0FtFDIyx9BPSnshUHlV36rOQeTPiYRbV2sUZlhOK06qJFH/xfHoWMp2Q78CYpi AuFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IZsxu8ta; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. 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Prepare the processor bug infrastructure so that it can be expanded to check for per-processor bugs. Signed-off-by: Russell King Reviewed-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long --- arch/arm/include/asm/bugs.h | 4 ++-- arch/arm/kernel/Makefile | 1 + arch/arm/kernel/bugs.c | 9 +++++++++ 3 files changed, 12 insertions(+), 2 deletions(-) create mode 100644 arch/arm/kernel/bugs.c -- 2.17.1 diff --git a/arch/arm/include/asm/bugs.h b/arch/arm/include/asm/bugs.h index a97f1ea708d1..ed122d294f3f 100644 --- a/arch/arm/include/asm/bugs.h +++ b/arch/arm/include/asm/bugs.h @@ -10,10 +10,10 @@ #ifndef __ASM_BUGS_H #define __ASM_BUGS_H -#ifdef CONFIG_MMU extern void check_writebuffer_bugs(void); -#define check_bugs() check_writebuffer_bugs() +#ifdef CONFIG_MMU +extern void check_bugs(void); #else #define check_bugs() do { } while (0) #endif diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 3c789496297f..f936cec24f72 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -30,6 +30,7 @@ else obj-y += entry-armv.o endif +obj-$(CONFIG_MMU) += bugs.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ISA_DMA_API) += dma.o obj-$(CONFIG_FIQ) += fiq.o fiqasm.o diff --git a/arch/arm/kernel/bugs.c b/arch/arm/kernel/bugs.c new file mode 100644 index 000000000000..88024028bb70 --- /dev/null +++ b/arch/arm/kernel/bugs.c @@ -0,0 +1,9 @@ +// SPDX-Identifier: GPL-2.0 +#include +#include +#include + +void __init check_bugs(void) +{ + check_writebuffer_bugs(); +} From patchwork Wed Oct 31 14:04:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149822 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6835942ljp; Wed, 31 Oct 2018 07:04:44 -0700 (PDT) X-Received: by 2002:a9f:364a:: with SMTP id s10mr1341904uad.78.1540994683954; Wed, 31 Oct 2018 07:04:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994683; cv=none; d=google.com; s=arc-20160816; b=U8QV3JQxZexkG8V57pxJShd0WyVsJS2MSW5kH92YD15mx7XsmnOWkI8hKyRYVPmQiZ cJICIQrA6ZAHStIbcRR7tsCvpibXnqrRjrbdR9N/Lt+ubw02v7vfUceofJyZ/4MjeCLG PISOUt6cGQZnKtWWwe4GLfeo8XQBi1HxzrmVCl+RXLp6tUuD4F7c3EH0A5fitQOl1xqa 1hNVYyZtjDGx71+iqwMrLOM5bnxpzc+ZHRvcmLzqyaCorYpiamQ1VpkteMbEqzVzhhph IoulJBxTuR4UzQSQroKRqaHHPAsDF9OD3rEy1/xtBS7lpoWZQjz+KZZQq4BPSs9fU880 zKEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XEVPM1Mo+ku5rrRHAc518WvkerVTKSxDAXP6BlmW8w8=; b=SSUCace4lWBSsDeUfsunrwlkQIOtwiooP3WkyuSEGrm+taEdbC+IY45LXk5/Jpb6ZC 0gcl1sm2srdfPT7wf4OW4qpHh3yJP6w15z6g996q931Bt66l1gPuzZezgyN5ORBeYWD7 98RbyY/BKNK19TgFVzyf5cWe4CHHWvSZiaWF/y1OK1F6hKQCHjus/8JH2AD+gUSf2emP mJkwinm86Ex3WHOP+X9v4k/N1d4coKi1RbG+5oKJoAe24czlJE/SWLmrVHVopO6cWf/5 smxncugWwvaztuXvtiR7WN5BrbapeqOqeNpN2TW/27637oGQSyBlAxnD/GVc014Ack5f bDig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bKK36Lco; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id c10sor16246799uak.27.2018.10.31.07.04.43 for (Google Transport Security); Wed, 31 Oct 2018 07:04:43 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bKK36Lco; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XEVPM1Mo+ku5rrRHAc518WvkerVTKSxDAXP6BlmW8w8=; b=bKK36Lco5Q19SzXvf1gDx04qFNWpUu1kbJOt3VOmE4rV5sW9mBr+LIFAY7wme4pRlw Hc9FAW+bGq54ERZXEMcu7Cu2HdewCGv0u65EsztqywB6yN5FM8G/GLxfB4WKeq+R92im ej98np2bX/486/PjpIK9djiM09XhRGEFBrWjs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XEVPM1Mo+ku5rrRHAc518WvkerVTKSxDAXP6BlmW8w8=; b=Cm/s4k+esxA89edPyJAy35gMKzWYRsXSwsvvj8A80S+2eRa2jjjgPfl51LDtzauBl+ +E8dLlbL7XnRJ6ZcQ8gkyktklo48trHIB5b5L7v5Luh9pIrEcthnrbHrrQy60lycI3qt HXQaZ8dTix799RB7mSIj8tHLXmn8+xISyAZoRWtTz/ItRoWeFbs9AV1SHruQfJUgIxv9 UljumIZHcY8NXzaCh24wubyTHr1t5B1DrOP7i5kYH49EirFj3TPflRluoPrhYMSd8llp qyWCMW0ToChecr93t1pvWlsh33L6VplC2puM9apbTP8qqQxl5Ft4vTTXyDnC0SrCVpTj Ak6g== X-Gm-Message-State: AGRZ1gIVcndGsycmB9dlphJE5AkCma6NT8hww3bMoBUX0xGZOwWXDokJ kLjMg5V+5hoF92J4QKTQT4suJyPo X-Google-Smtp-Source: AJdET5e1MVU+Funpa0lxM6CwE66GfLhmlH3K+wqFyOm+3/gjLqT1kKGIySuL26WvVw6w/OYz3v6sxg== X-Received: by 2002:ab0:162e:: with SMTP id k43mr1322245uae.77.1540994683105; Wed, 31 Oct 2018 07:04:43 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:42 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 03/18] ARM: bugs: hook processor bug checking into SMP and suspend paths Date: Wed, 31 Oct 2018 10:04:21 -0400 Message-Id: <20181031140436.2964-4-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit 26602161b5ba795928a5a719fe1d5d9f2ab5c3ef upstream. Check for CPU bugs when secondary processors are being brought online, and also when CPUs are resuming from a low power mode. This gives an opportunity to check that processor specific bug workarounds are correctly enabled for all paths that a CPU re-enters the kernel. Signed-off-by: Russell King Reviewed-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long --- arch/arm/include/asm/bugs.h | 2 ++ arch/arm/kernel/bugs.c | 5 +++++ arch/arm/kernel/smp.c | 4 ++++ arch/arm/kernel/suspend.c | 2 ++ 4 files changed, 13 insertions(+) -- 2.17.1 diff --git a/arch/arm/include/asm/bugs.h b/arch/arm/include/asm/bugs.h index ed122d294f3f..73a99c72a930 100644 --- a/arch/arm/include/asm/bugs.h +++ b/arch/arm/include/asm/bugs.h @@ -14,8 +14,10 @@ extern void check_writebuffer_bugs(void); #ifdef CONFIG_MMU extern void check_bugs(void); +extern void check_other_bugs(void); #else #define check_bugs() do { } while (0) +#define check_other_bugs() do { } while (0) #endif #endif diff --git a/arch/arm/kernel/bugs.c b/arch/arm/kernel/bugs.c index 88024028bb70..16e7ba2a9cc4 100644 --- a/arch/arm/kernel/bugs.c +++ b/arch/arm/kernel/bugs.c @@ -3,7 +3,12 @@ #include #include +void check_other_bugs(void) +{ +} + void __init check_bugs(void) { check_writebuffer_bugs(); + check_other_bugs(); } diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index b26361355dae..334c319f5766 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -396,6 +397,9 @@ asmlinkage void secondary_start_kernel(void) * before we continue - which happens after __cpu_up returns. */ set_cpu_online(cpu, true); + + check_other_bugs(); + complete(&cpu_running); local_irq_enable(); diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c index 9a2f882a0a2d..134f0d432610 100644 --- a/arch/arm/kernel/suspend.c +++ b/arch/arm/kernel/suspend.c @@ -1,6 +1,7 @@ #include #include +#include #include #include #include @@ -34,6 +35,7 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) cpu_switch_mm(mm->pgd, mm); local_flush_bp_all(); local_flush_tlb_all(); + check_other_bugs(); } return ret; From patchwork Wed Oct 31 14:04:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149823 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6835981ljp; Wed, 31 Oct 2018 07:04:45 -0700 (PDT) X-Received: by 2002:a67:8406:: with SMTP id g6mr1380318vsd.0.1540994685349; Wed, 31 Oct 2018 07:04:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994685; cv=none; d=google.com; s=arc-20160816; b=N3dt0Jzsmbd6+gAFWYDc9sRlNRUdadceOD2fb5fJ/OGq8SWq99Gi1x6L8bPNXX337A 1zjhK7VXDq9CNX7lFHbT2+VVSWvvxVcN2STV6fbaCoVIqx+cj8D68bsV9qLbuqk6wpJ6 WjBmnlLOxPdcamSuyPrV6ZQiFYYLm+X61wlu5fKoD6lHTUmarl4JE+W28tdEZWDSExaM FQvrEGIo8x+fOvbXv6Gk6Uiy8qI4Ngya9TEn8+rzwrMAe7o6EptIVsmZDbzuqvmrTkap DPfmz2kVBmKIMgCVEvIeDnaI1q7Ek0V1kx9fvpBFlQDHmCHoxRV/Pge6UWoVk6X91kvL /H+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ETbNdSeBPd5xM2dN4FrDzl5stbA+LzyzD4VmBVmdPGg=; b=enTQr4dSgRk0t3fMqoBvcqMNwxtdZUtLN4Qf8SgUn25NJzHYNbiIZssFXQwejBX6nM Hv54ltr2EhVBl8nzl5+DSggivm7GFKG74bR0ZFpKTa6qkTFVXtgEAKaAHYqhMGbxxLnp c/ba6EfCrA7Y6LkIv9RXhQFoYT6WI6BXxU+YvmWw90TLyqfTQIuCz+YzRmbhwxz2LV3b E7anmH6OmbKGSQYNW7LzlRytWx8lfQ6mYCcayNsi8wr6QkLsBM3lk4xg3ixZHdW6/4R3 Elzx9UggpORVCrADgZRsO6QC16XXaIzd4hrKaVZD9g2SMILCsAn1VnEM3ZZtDVi0ad2H iAAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L7bEqun5; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id b187sor16167813vsd.54.2018.10.31.07.04.45 for (Google Transport Security); Wed, 31 Oct 2018 07:04:45 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L7bEqun5; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ETbNdSeBPd5xM2dN4FrDzl5stbA+LzyzD4VmBVmdPGg=; b=L7bEqun521oaqk2WTcO/fR/5e2dbRx7+iqdR8fyRauKqYkK9KVp4UQ/n0t7+wPuOQI KPEqymre4PVMRR70myzdwyLdt8qVz9oe7OK/WEL1X1El1A6w9fCOo5RNTagJXl0Zg7S9 5GaH+Yak9qEEE743eaF6eXmpWDgoO6QCuUaAM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ETbNdSeBPd5xM2dN4FrDzl5stbA+LzyzD4VmBVmdPGg=; b=CSNPxFkeus7wD5/Ji9PEXg9wVB9aYCrnUhvDHVli+6HWvKH3UKL892YrvLKRgOjTmO QGAGpVV5sWMBSaVH9y+IblOLjEuXd0bhs/0gTvlE5DPlRZEYY/RT6HpOl0EKXyH9NYtW MMWtotZBTM9wJ2owj0vKUgwdOufIWDYnbCq23ghHos1owGTmHgCb23F4eAZWzhR4SfSP bBFCy0qzWxoOEDYUIkC6Ia3TtqMu8eBeZ8CEj8EeL5UOfzEHuLQNwPRl64VlooxvOe1M Dlmz1iIuSDkHZMvVbqRZiCCFh+S2+AMFi/Hs4DHf56Zc0a48S9WvMQL1rNelUf9YNUli VNxw== X-Gm-Message-State: AGRZ1gImsIe/91EmZ0RiM0+Rya8poueXbo2lC6lAC+dmgdz/lefkGDuj 7/uqFaXNYyqHeekH5VID5y0sfZRQ X-Google-Smtp-Source: AJdET5eMLo9Hx8lg/rPLUW9xGsgiBbnvll5/j4yD1Ndr7tpcbcJpi/dzKkdnHq0nyKSVs8tXOBdG7w== X-Received: by 2002:a67:4441:: with SMTP id r62mr1331511vsa.38.1540994684880; Wed, 31 Oct 2018 07:04:44 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:43 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 04/18] ARM: bugs: add support for per-processor bug checking Date: Wed, 31 Oct 2018 10:04:22 -0400 Message-Id: <20181031140436.2964-5-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit 9d3a04925deeabb97c8e26d940b501a2873e8af3 upstream. Add support for per-processor bug checking - each processor function descriptor gains a function pointer for this check, which must not be an __init function. If non-NULL, this will be called whenever a CPU enters the kernel via which ever path (boot CPU, secondary CPU startup, CPU resuming, etc.) This allows processor specific bug checks to validate that workaround bits are properly enabled by firmware via all entry paths to the kernel. Signed-off-by: Russell King Reviewed-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long --- arch/arm/include/asm/proc-fns.h | 4 ++++ arch/arm/kernel/bugs.c | 4 ++++ arch/arm/mm/proc-macros.S | 3 ++- 3 files changed, 10 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h index 8877ad5ffe10..f379f5f849a9 100644 --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h @@ -36,6 +36,10 @@ extern struct processor { * Set up any processor specifics */ void (*_proc_init)(void); + /* + * Check for processor bugs + */ + void (*check_bugs)(void); /* * Disable any processor specifics */ diff --git a/arch/arm/kernel/bugs.c b/arch/arm/kernel/bugs.c index 16e7ba2a9cc4..7be511310191 100644 --- a/arch/arm/kernel/bugs.c +++ b/arch/arm/kernel/bugs.c @@ -5,6 +5,10 @@ void check_other_bugs(void) { +#ifdef MULTI_CPU + if (processor.check_bugs) + processor.check_bugs(); +#endif } void __init check_bugs(void) diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index c671f345266a..212147c78f4b 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -258,13 +258,14 @@ mcr p15, 0, ip, c7, c10, 4 @ data write barrier .endm -.macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0 +.macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0, bugs=0 .type \name\()_processor_functions, #object .align 2 ENTRY(\name\()_processor_functions) .word \dabort .word \pabort .word cpu_\name\()_proc_init + .word \bugs .word cpu_\name\()_proc_fin .word cpu_\name\()_reset .word cpu_\name\()_do_idle From patchwork Wed Oct 31 14:04:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149824 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836032ljp; Wed, 31 Oct 2018 07:04:47 -0700 (PDT) X-Received: by 2002:a67:ebc3:: with SMTP id y3mr524456vso.75.1540994687282; Wed, 31 Oct 2018 07:04:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994687; cv=none; d=google.com; s=arc-20160816; b=zLWjmq4fjPw0l3KkGl+afduuKjs/w9s5PlH7QO5gHIoqmdgQGr9Zr6+IBG3p5OAnkK aSzSMAfmPFoA3nucouj57pDA54FL+38A947+6yPADVx0z4cHiNktS5tzCawQguEphz70 rd1ZtdCu9+CJ6Xj3kEh/+VOCauY+5sETOF0+jXdLoqCsysATPM4KORijw6Q6qqwGewCj OiiG2HhKRiPZn9h+OGHWpEzzkwFb2LkKR0SsIsb1O3dLtH1O79uqdskiDKk6CaTy4e6Q zl4ocA332MbOZ3HgPXmKD33mt/QD8Hip6WQjrw6S92jDS8uq3sPJVwY4nlxgg0Y/9PVM y+ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iY0C5tZptmS259+EdQcS5tjulW6ZksJIMP4AJC8oZq4=; b=th1/Q08QRSGsjR9OOW5UmHPU0RPxou4D7XqWMjRZwan58zOaCVrbUG4H/knogSQts3 maRKM6r+XjP9PwoBb6Lx0Ait5PXwjBhk79e8fo3oa7FvXijhjhsryDhBEggG6cFQ7Tcz 2VT6xB1mVbWzCAtSCja3ul7D822OvOetxYfjWekfRzMJppNVGkToCrVEUm8weYAP6rNF 9X4AGwRlfqR1PocPwDCuC1hIc0EINTaVpZSUWMzC2YLfRfmA/rz1gIgz2bPk5VhI5Hze 8X395zsP1zr95P9dv380Kx9SPmIFQIZt70WS/G1C+93zEHmw3NRiLRS0A9GBcEisflJO u3cg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Yuk1W/Tm"; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id p100sor4363583uap.6.2018.10.31.07.04.47 for (Google Transport Security); Wed, 31 Oct 2018 07:04:47 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Yuk1W/Tm"; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iY0C5tZptmS259+EdQcS5tjulW6ZksJIMP4AJC8oZq4=; b=Yuk1W/Tm5cGYw9I9u4+xHd6Z1YjrfhZu8L0zK4d0X8r9vgf5B//V9drnIudoj0/HFT 4//ivx4/sUN9b4EbXaTyaH1d+S1TPvkPbZVBc3wR8OwmCo0qhRfsbQP6t8VGo9M/6m+s FzB101y5GF1d8id6xqwMF4V0KLwyEXVwa/U8w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iY0C5tZptmS259+EdQcS5tjulW6ZksJIMP4AJC8oZq4=; b=O32MufPzRvTUKWvJ9034UEzRPisqdgbUKdBDZiEsbAXFQuK+e0Gp2onQuBvZO68+lB 4hR8Oktmv1h5sSP0AyxYegE6Nlj/FbbEeZsv7znmoAhJrxw2xSokt1LbcWx9co35HKoh cQSmSs4gm5r2yYKntySYnzoErkOpPY1B057dyHgqF1MVcw600oJ4nS3pvnO8fmqkG7bt P64S683Q81TEByEVOv0jRIj0IImz863MCGZVXadjENA3h+PIj6O2QznUzIkytpeNO4t8 f1iPzMXnP9Y4NjCRNnONE44VymWu9Um48Ak03CP7Aps+f3u713l2qPbUlCLpr8/VS5ao j6Ug== X-Gm-Message-State: AGRZ1gKkJVTQ0atMrtNkobLjnLmGXsvgBoxewYQbprULWd2jqaUAmS0C RM2zy0FhJjj8hVWjWE8eBJSTKpJH X-Google-Smtp-Source: AJdET5caf0ijU/68utFvGbs2ArxHaaEp8QGrT3tJ4rV/5sHLWYHlUYRxSjolQGrnmU6/9JgGI4HLow== X-Received: by 2002:a9f:2b06:: with SMTP id p6mr1445950uaj.103.1540994686587; Wed, 31 Oct 2018 07:04:46 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:46 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 05/18] ARM: spectre: add Kconfig symbol for CPUs vulnerable to Spectre Date: Wed, 31 Oct 2018 10:04:23 -0400 Message-Id: <20181031140436.2964-6-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit c58d237d0852a57fde9bc2c310972e8f4e3d155d upstream. Add a Kconfig symbol for CPUs which are vulnerable to the Spectre attacks. Signed-off-by: Russell King Reviewed-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long --- arch/arm/mm/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 41218867a9a6..7ef92e6692ab 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -396,6 +396,7 @@ config CPU_V7 select CPU_CP15_MPU if !MMU select CPU_HAS_ASID if MMU select CPU_PABRT_V7 + select CPU_SPECTRE if MMU select CPU_TLB_V7 if MMU # ARMv7M @@ -793,6 +794,9 @@ config CPU_BPREDICT_DISABLE help Say Y here to disable branch prediction. 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Required manual merge of arch/arm/mm/proc-v7.S. Harden the branch predictor against Spectre v2 attacks on context switches for ARMv7 and later CPUs. We do this by: Cortex A9, A12, A17, A73, A75: invalidating the BTB. Cortex A15, Brahma B15: invalidating the instruction cache. Cortex A57 and Cortex A72 are not addressed in this patch. Cortex R7 and Cortex R8 are also not addressed as we do not enforce memory protection on these cores. Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long --- arch/arm/mm/Kconfig | 19 ++++++ arch/arm/mm/proc-v7-2level.S | 6 -- arch/arm/mm/proc-v7.S | 125 +++++++++++++++++++++++++++-------- 3 files changed, 115 insertions(+), 35 deletions(-) -- 2.17.1 diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 7ef92e6692ab..71115afb71a0 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -797,6 +797,25 @@ config CPU_BPREDICT_DISABLE config CPU_SPECTRE bool +config HARDEN_BRANCH_PREDICTOR + bool "Harden the branch predictor against aliasing attacks" if EXPERT + depends on CPU_SPECTRE + default y + help + Speculation attacks against some high-performance processors rely + on being able to manipulate the branch predictor for a victim + context by executing aliasing branches in the attacker context. + Such attacks can be partially mitigated against by clearing + internal branch predictor state and limiting the prediction + logic in some situations. + + This config option will take CPU-specific actions to harden + the branch predictor against aliasing attacks and may rely on + specific instruction sequences or control bits being set by + the system firmware. + + If unsure, say Y. + config TLS_REG_EMUL bool select NEED_KUSER_HELPERS diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index c6141a5435c3..f8d45ad2a515 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -41,11 +41,6 @@ * even on Cortex-A8 revisions not affected by 430973. * If IBE is not set, the flush BTAC/BTB won't do anything. */ -ENTRY(cpu_ca8_switch_mm) -#ifdef CONFIG_MMU - mov r2, #0 - mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB -#endif ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU mmid r1, r1 @ get mm->context.id @@ -66,7 +61,6 @@ ENTRY(cpu_v7_switch_mm) #endif bx lr ENDPROC(cpu_v7_switch_mm) -ENDPROC(cpu_ca8_switch_mm) /* * cpu_v7_set_pte_ext(ptep, pte) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 8e1ea433c3f1..c2950317c7c2 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -87,6 +87,17 @@ ENTRY(cpu_v7_dcache_clean_area) ret lr ENDPROC(cpu_v7_dcache_clean_area) +ENTRY(cpu_v7_iciallu_switch_mm) + mov r3, #0 + mcr p15, 0, r3, c7, c5, 0 @ ICIALLU + b cpu_v7_switch_mm +ENDPROC(cpu_v7_iciallu_switch_mm) +ENTRY(cpu_v7_bpiall_switch_mm) + mov r3, #0 + mcr p15, 0, r3, c7, c5, 6 @ flush BTAC/BTB + b cpu_v7_switch_mm +ENDPROC(cpu_v7_bpiall_switch_mm) + string cpu_v7_name, "ARMv7 Processor" .align @@ -152,31 +163,6 @@ ENTRY(cpu_v7_do_resume) ENDPROC(cpu_v7_do_resume) #endif -/* - * Cortex-A8 - */ - globl_equ cpu_ca8_proc_init, cpu_v7_proc_init - globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin - globl_equ cpu_ca8_reset, cpu_v7_reset - globl_equ cpu_ca8_do_idle, cpu_v7_do_idle - globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area - globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext - globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size -#ifdef CONFIG_ARM_CPU_SUSPEND - globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend - globl_equ cpu_ca8_do_resume, cpu_v7_do_resume -#endif - -/* - * Cortex-A9 processor functions - */ - globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init - globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin - globl_equ cpu_ca9mp_reset, cpu_v7_reset - globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle - globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area - globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm - globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext .globl cpu_ca9mp_suspend_size .equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2 #ifdef CONFIG_ARM_CPU_SUSPEND @@ -490,10 +476,75 @@ __v7_setup_stack: @ define struct processor (see and proc-macros.S) define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + @ generic v7 bpiall on context switch + globl_equ cpu_v7_bpiall_proc_init, cpu_v7_proc_init + globl_equ cpu_v7_bpiall_proc_fin, cpu_v7_proc_fin + globl_equ cpu_v7_bpiall_reset, cpu_v7_reset + globl_equ cpu_v7_bpiall_do_idle, cpu_v7_do_idle + globl_equ cpu_v7_bpiall_dcache_clean_area, cpu_v7_dcache_clean_area + globl_equ cpu_v7_bpiall_set_pte_ext, cpu_v7_set_pte_ext + globl_equ cpu_v7_bpiall_suspend_size, cpu_v7_suspend_size +#ifdef CONFIG_ARM_CPU_SUSPEND + globl_equ cpu_v7_bpiall_do_suspend, cpu_v7_do_suspend + globl_equ cpu_v7_bpiall_do_resume, cpu_v7_do_resume +#endif + define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + +#define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_bpiall_processor_functions +#else +#define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_processor_functions +#endif + #ifndef CONFIG_ARM_LPAE + @ Cortex-A8 - always needs bpiall switch_mm implementation + globl_equ cpu_ca8_proc_init, cpu_v7_proc_init + globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin + globl_equ cpu_ca8_reset, cpu_v7_reset + globl_equ cpu_ca8_do_idle, cpu_v7_do_idle + globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area + globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext + globl_equ cpu_ca8_switch_mm, cpu_v7_bpiall_switch_mm + globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size +#ifdef CONFIG_ARM_CPU_SUSPEND + globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend + globl_equ cpu_ca8_do_resume, cpu_v7_do_resume +#endif define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + + @ Cortex-A9 - needs more registers preserved across suspend/resume + @ and bpiall switch_mm for hardening + globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init + globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin + globl_equ cpu_ca9mp_reset, cpu_v7_reset + globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle + globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + globl_equ cpu_ca9mp_switch_mm, cpu_v7_bpiall_switch_mm +#else + globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm +#endif + globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 #endif + + @ Cortex-A15 - needs iciallu switch_mm for hardening + globl_equ cpu_ca15_proc_init, cpu_v7_proc_init + globl_equ cpu_ca15_proc_fin, cpu_v7_proc_fin + globl_equ cpu_ca15_reset, cpu_v7_reset + globl_equ cpu_ca15_do_idle, cpu_v7_do_idle + globl_equ cpu_ca15_dcache_clean_area, cpu_v7_dcache_clean_area +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + globl_equ cpu_ca15_switch_mm, cpu_v7_iciallu_switch_mm +#else + globl_equ cpu_ca15_switch_mm, cpu_v7_switch_mm +#endif + globl_equ cpu_ca15_set_pte_ext, cpu_v7_set_pte_ext + globl_equ cpu_ca15_suspend_size, cpu_v7_suspend_size + globl_equ cpu_ca15_do_suspend, cpu_v7_do_suspend + globl_equ cpu_ca15_do_resume, cpu_v7_do_resume + define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 #ifdef CONFIG_CPU_PJ4B define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 #endif @@ -600,7 +651,7 @@ __v7_ca7mp_proc_info: __v7_ca12mp_proc_info: .long 0x410fc0d0 .long 0xff0ffff0 - __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup + __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info /* @@ -610,7 +661,7 @@ __v7_ca12mp_proc_info: __v7_ca15mp_proc_info: .long 0x410fc0f0 .long 0xff0ffff0 - __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup + __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup, proc_fns = ca15_processor_functions .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info /* @@ -620,7 +671,7 @@ __v7_ca15mp_proc_info: __v7_b15mp_proc_info: .long 0x420f00f0 .long 0xff0ffff0 - __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup + __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup, proc_fns = ca15_processor_functions .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info /* @@ -630,9 +681,25 @@ __v7_b15mp_proc_info: __v7_ca17mp_proc_info: .long 0x410fc0e0 .long 0xff0ffff0 - __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup + __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info + /* ARM Ltd. Cortex A73 processor */ + .type __v7_ca73_proc_info, #object +__v7_ca73_proc_info: + .long 0x410fd090 + .long 0xff0ffff0 + __v7_proc __v7_ca73_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS + .size __v7_ca73_proc_info, . - __v7_ca73_proc_info + + /* ARM Ltd. Cortex A75 processor */ + .type __v7_ca75_proc_info, #object +__v7_ca75_proc_info: + .long 0x410fd0a0 + .long 0xff0ffff0 + __v7_proc __v7_ca75_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS + .size __v7_ca75_proc_info, . - __v7_ca75_proc_info + /* * Qualcomm Inc. Krait processors. */ From patchwork Wed Oct 31 14:04:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149826 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836100ljp; Wed, 31 Oct 2018 07:04:50 -0700 (PDT) X-Received: by 2002:a67:87cf:: with SMTP id j198mr632866vsd.104.1540994690316; Wed, 31 Oct 2018 07:04:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994690; cv=none; d=google.com; s=arc-20160816; b=b41oflOTl6bbdBz36SgXTSqXsRt0hFiKICXniyIPyMCQfkzP9luEyNpxa4E8dZSH4P ClDBahKrlQz//Ios8bzfc/dbFD+acflY0KLWbJIOt1QbV5UKJ3jrXphwWJJScX/FNxd5 m+bsCLCPChDUHwqSrtR7HfQ8XnqcYLZghAuZMjykUQ7FVJYATLEe2H92jZuyy/AIP95H CnhthCcRgLOneLcVCMG0sXevBB/5WkAHj6WRq4moP/6m5WjhyqsQ51JLOM4VMPQKA5bn sXnZow/3mnEReQkXk6ZVivu21wB12Ef5806v6Dp443pU15N13fgwDw0aScf10bctR5TS Srbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HEne2njS0TPSGIgg0dgG4R5OFKIAKRCc8fMLUGG3Bbk=; b=LByArq2p1H87yf6nZmMVru66da2ZkCDT89sJjrStFkeGdoDz6l727Gr+pFIypg04A4 OL/wgsK/gLuQmS5Q/2Erzh2WPcCCCDWNuV9EoHsgPhSJCPChOjgGILmzzy02uYHORvj/ Ezv7fCisrpPdAO6fdyAY11fsbu5UgY+SJMxxJC0ozwcx8rynKwZtIYd2mxw/B9rFT0bW uQ4MSWyZoF750ayZsPJaZ29jHCfALB2TptpqhJ5Zu8xbE9OTGfaKH5+xTO2Egs7tqvhk i2GVq5FiKNCqJOXauwt2hEdgqDNWNvpLRtSAm6KWtufi04A5Axd+wh02tUvGfv3vpP1Y DRFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bThnRVgQ; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id w18sor16273332uaj.58.2018.10.31.07.04.50 for (Google Transport Security); Wed, 31 Oct 2018 07:04:50 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bThnRVgQ; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HEne2njS0TPSGIgg0dgG4R5OFKIAKRCc8fMLUGG3Bbk=; b=bThnRVgQET4Lz6iWI+LjvuQho1FoWcdO/PWwJOCYNYxp2DXcxauevFjbD4Da8cQB1y 82m8w8uhRwbtG5FalmeRpTC0KvT97fHNofEE19cu5yjrL5Q8B/KffLpiwzyjRe6C+tR6 2d+cpsL/MGrM6dVasH7rk86LFfGUV3P6WWUkc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HEne2njS0TPSGIgg0dgG4R5OFKIAKRCc8fMLUGG3Bbk=; b=l3+78ZyPnCDxakP15nh7L7uRlFLcN76LvHvL9wShZpexM8boqVHBRc8S4JOIPFaj0n rrGPri4z+RUx6huX1+Oix640pODO50/KNICaG/SI7wXgvjUk+825MVThaxAgsUJihj7o 0Ds4DZivgpD+/LEYtP7e2BZ3svtcPB4D7sO9qBQtNr3p7zQEe+J3rlLIzxhtR5ZQ3VtV Kw8sgfNc84bdt+yR1TkoS6mTySqgjTMPywiTsSSEB2nO+AilPMx1GM1JlGXgREfY7t3M cay+zN6Lr7QueMLvN7NnIq/m4btfucruy6bbhh9fxY+QpB7rFgxIlr9IOe47P4LMcmPE Zn6g== X-Gm-Message-State: AGRZ1gJysIUJD4kJII28pRkQxAFuAQ4OO3U84WggPGBy9xUAC1mI0ZM9 6UaoxksNoUmVcNvBD0RNWJlxxoS+ X-Google-Smtp-Source: AJdET5etLHVe+uwkU+SLxGCT+pqendR62nkPcQOe5J5qGxeM+/D2/XOJ9+v+fUXCtqoVDEj4mnoOxQ== X-Received: by 2002:ab0:b82:: with SMTP id c2mr1428137uak.121.1540994689690; Wed, 31 Oct 2018 07:04:49 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:48 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 07/18] ARM: spectre-v2: add Cortex A8 and A15 validation of the IBE bit Date: Wed, 31 Oct 2018 10:04:25 -0400 Message-Id: <20181031140436.2964-8-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit e388b80288aade31135aca23d32eee93dd106795 upstream. When the branch predictor hardening is enabled, firmware must have set the IBE bit in the auxiliary control register. If this bit has not been set, the Spectre workarounds will not be functional. Add validation that this bit is set, and print a warning at alert level if this is not the case. Signed-off-by: Russell King Reviewed-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/mm/Makefile | 2 +- arch/arm/mm/proc-v7-bugs.c | 36 ++++++++++++++++++++++++++++++++++++ arch/arm/mm/proc-v7.S | 4 ++-- 3 files changed, 39 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mm/proc-v7-bugs.c -- 2.17.1 diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 7f76d96ce546..35307176e46c 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -92,7 +92,7 @@ obj-$(CONFIG_CPU_MOHAWK) += proc-mohawk.o obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o obj-$(CONFIG_CPU_V6) += proc-v6.o obj-$(CONFIG_CPU_V6K) += proc-v6.o -obj-$(CONFIG_CPU_V7) += proc-v7.o +obj-$(CONFIG_CPU_V7) += proc-v7.o proc-v7-bugs.o obj-$(CONFIG_CPU_V7M) += proc-v7m.o AFLAGS_proc-v6.o :=-Wa,-march=armv6 diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c new file mode 100644 index 000000000000..e46557db6446 --- /dev/null +++ b/arch/arm/mm/proc-v7-bugs.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +static __maybe_unused void cpu_v7_check_auxcr_set(bool *warned, + u32 mask, const char *msg) +{ + u32 aux_cr; + + asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (aux_cr)); + + if ((aux_cr & mask) != mask) { + if (!*warned) + pr_err("CPU%u: %s", smp_processor_id(), msg); + *warned = true; + } +} + +static DEFINE_PER_CPU(bool, spectre_warned); + +static void check_spectre_auxcr(bool *warned, u32 bit) +{ + if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR) && + cpu_v7_check_auxcr_set(warned, bit, + "Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable\n"); +} + +void cpu_v7_ca8_ibe(void) +{ + check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6)); +} + +void cpu_v7_ca15_ibe(void) +{ + check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0)); +} diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c2950317c7c2..1436ad424f2a 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -511,7 +511,7 @@ __v7_setup_stack: globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend globl_equ cpu_ca8_do_resume, cpu_v7_do_resume #endif - define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca8_ibe @ Cortex-A9 - needs more registers preserved across suspend/resume @ and bpiall switch_mm for hardening @@ -544,7 +544,7 @@ __v7_setup_stack: globl_equ cpu_ca15_suspend_size, cpu_v7_suspend_size globl_equ cpu_ca15_do_suspend, cpu_v7_do_suspend globl_equ cpu_ca15_do_resume, cpu_v7_do_resume - define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca15_ibe #ifdef CONFIG_CPU_PJ4B define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 #endif From patchwork Wed Oct 31 14:04:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149827 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836147ljp; Wed, 31 Oct 2018 07:04:52 -0700 (PDT) X-Received: by 2002:a1f:850a:: with SMTP id h10-v6mr1345895vkd.4.1540994692179; Wed, 31 Oct 2018 07:04:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994692; cv=none; d=google.com; s=arc-20160816; b=RXDU9dxdKYOpheRZLtY8nWtd9v6Hr4SBN/QzYFsmk+QeCz2yiMYSGcvQm1bRlGe7rY b2hv31nGEB3l9NX8u/CMSI2/1ItC+z/IQ7jsUA+zNC+65TTjBxi1iR6fPKfzU73Tik7w uQNAszMHmsnV/4srw8UwjRk4yLBVRaSeUQmLasx6idWSMtMlQlWoV3EXeSuVVkuABI6T CaEeOoyi0RrzFtAvYBacTStP09tIqwOJunNPVuuT7J9Ngs6maVoUgMGhcIapeFN8i2WZ Dq9uwf2mxQ0OtbN7xOAR5mkgilCKq7sCybOP4qfmgtus2wZ5hv47DpC1rX6JPBq7J2hT 2KqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9sK25ehlMYx5Oqprsh7r57AVHEV3azX4ngQ8wLdhyeU=; b=wxUuF9B1wg0XMJJcC4tuzHBZwfKVPuR/7mc04PqOPSizURgeVRjw0vpZ3KLUZdm74f n+i2PrJKrKBtBjn7g6op9N24AfwfbEah/taK3csow3V1HJ1cu8JbUdv6cV31BoNiT0iy TLC9FQDlAGku1D4NyGnZJBXHxZMoBegCsbtQiPXY7PCUk/hXh/GZabsah0cSTd0jrsYT zSitQY5XPR100qrXO1ZaCS2ty+I96ARP0UKgE+hR5wRN2JsO0ecQpqMyxBqu335y6Ky6 hcQuPnjYxy/ijIGQoMESfNKv8SelHq9d8qoDghfH7Emu8/M+AeWXp15SsSNcbfHrPS1J uMvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kwKr+ahY; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. 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This required some additional defines be brought back. In order to prevent aliasing attacks on the branch predictor, invalidate the BTB or instruction cache on CPUs that are known to be affected when taking an abort on a address that is outside of a user task limit: Cortex A8, A9, A12, A17, A73, A75: flush BTB. Cortex A15, Brahma B15: invalidate icache. If the IBE bit is not set, then there is little point to enabling the workaround. Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: Florian Fainelli Signed-off-by: David A. Long --- arch/arm/include/asm/cp15.h | 18 ++++++++ arch/arm/include/asm/system_misc.h | 15 ++++++ arch/arm/mm/fault.c | 3 ++ arch/arm/mm/proc-v7-bugs.c | 73 ++++++++++++++++++++++++++++-- arch/arm/mm/proc-v7.S | 8 ++-- 5 files changed, 109 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h index c3f11524f10c..b74b174ac9fc 100644 --- a/arch/arm/include/asm/cp15.h +++ b/arch/arm/include/asm/cp15.h @@ -49,6 +49,24 @@ #ifdef CONFIG_CPU_CP15 +#define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ + "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32 +#define __ACCESS_CP15_64(Op1, CRm) \ + "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64 + +#define __read_sysreg(r, w, c, t) ({ \ + t __val; \ + asm volatile(r " " c : "=r" (__val)); \ + __val; \ +}) +#define read_sysreg(...) __read_sysreg(__VA_ARGS__) + +#define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v))) +#define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__) + +#define BPIALL __ACCESS_CP15(c7, 0, c5, 6) +#define ICIALLU __ACCESS_CP15(c7, 0, c5, 0) + extern unsigned long cr_alignment; /* defined in entry-armv.S */ static inline unsigned long get_cr(void) diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h index a3d61ad984af..1fed41440af9 100644 --- a/arch/arm/include/asm/system_misc.h +++ b/arch/arm/include/asm/system_misc.h @@ -7,6 +7,7 @@ #include #include #include +#include extern void cpu_init(void); @@ -14,6 +15,20 @@ void soft_restart(unsigned long); extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); extern void (*arm_pm_idle)(void); +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +typedef void (*harden_branch_predictor_fn_t)(void); +DECLARE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); +static inline void harden_branch_predictor(void) +{ + harden_branch_predictor_fn_t fn = per_cpu(harden_branch_predictor_fn, + smp_processor_id()); + if (fn) + fn(); +} +#else +#define harden_branch_predictor() do { } while (0) +#endif + #define UDBG_UNDEFINED (1 << 0) #define UDBG_SYSCALL (1 << 1) #define UDBG_BADABORT (1 << 2) diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 0d20cd594017..afc8d7cf7625 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -163,6 +163,9 @@ __do_user_fault(struct task_struct *tsk, unsigned long addr, { struct siginfo si; + if (addr > TASK_SIZE) + harden_branch_predictor(); + #ifdef CONFIG_DEBUG_USER if (((user_debug & UDBG_SEGV) && (sig == SIGSEGV)) || ((user_debug & UDBG_BUS) && (sig == SIGBUS))) { diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c index e46557db6446..85a2e3d6263c 100644 --- a/arch/arm/mm/proc-v7-bugs.c +++ b/arch/arm/mm/proc-v7-bugs.c @@ -2,7 +2,61 @@ #include #include -static __maybe_unused void cpu_v7_check_auxcr_set(bool *warned, +#include +#include +#include + +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); + +static void harden_branch_predictor_bpiall(void) +{ + write_sysreg(0, BPIALL); +} + +static void harden_branch_predictor_iciallu(void) +{ + write_sysreg(0, ICIALLU); +} + +static void cpu_v7_spectre_init(void) +{ + const char *spectre_v2_method = NULL; + int cpu = smp_processor_id(); + + if (per_cpu(harden_branch_predictor_fn, cpu)) + return; + + switch (read_cpuid_part()) { + case ARM_CPU_PART_CORTEX_A8: + case ARM_CPU_PART_CORTEX_A9: + case ARM_CPU_PART_CORTEX_A12: + case ARM_CPU_PART_CORTEX_A17: + case ARM_CPU_PART_CORTEX_A73: + case ARM_CPU_PART_CORTEX_A75: + per_cpu(harden_branch_predictor_fn, cpu) = + harden_branch_predictor_bpiall; + spectre_v2_method = "BPIALL"; + break; + + case ARM_CPU_PART_CORTEX_A15: + case ARM_CPU_PART_BRAHMA_B15: + per_cpu(harden_branch_predictor_fn, cpu) = + harden_branch_predictor_iciallu; + spectre_v2_method = "ICIALLU"; + break; + } + if (spectre_v2_method) + pr_info("CPU%u: Spectre v2: using %s workaround\n", + smp_processor_id(), spectre_v2_method); +} +#else +static void cpu_v7_spectre_init(void) +{ +} +#endif + +static __maybe_unused bool cpu_v7_check_auxcr_set(bool *warned, u32 mask, const char *msg) { u32 aux_cr; @@ -13,24 +67,33 @@ static __maybe_unused void cpu_v7_check_auxcr_set(bool *warned, if (!*warned) pr_err("CPU%u: %s", smp_processor_id(), msg); *warned = true; + return false; } + return true; } static DEFINE_PER_CPU(bool, spectre_warned); -static void check_spectre_auxcr(bool *warned, u32 bit) +static bool check_spectre_auxcr(bool *warned, u32 bit) { - if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR) && + return IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR) && cpu_v7_check_auxcr_set(warned, bit, "Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable\n"); } void cpu_v7_ca8_ibe(void) { - check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6)); + if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6))) + cpu_v7_spectre_init(); } void cpu_v7_ca15_ibe(void) { - check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0)); + if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0))) + cpu_v7_spectre_init(); +} + +void cpu_v7_bugs_init(void) +{ + cpu_v7_spectre_init(); } diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 1436ad424f2a..f6a4589b4fd2 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -474,8 +474,10 @@ __v7_setup_stack: __INITDATA + .weak cpu_v7_bugs_init + @ define struct processor (see and proc-macros.S) - define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR @ generic v7 bpiall on context switch @@ -490,7 +492,7 @@ __v7_setup_stack: globl_equ cpu_v7_bpiall_do_suspend, cpu_v7_do_suspend globl_equ cpu_v7_bpiall_do_resume, cpu_v7_do_resume #endif - define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_bpiall_processor_functions #else @@ -526,7 +528,7 @@ __v7_setup_stack: globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm #endif globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext - define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init #endif @ Cortex-A15 - needs iciallu switch_mm for hardening From patchwork Wed Oct 31 14:04:27 2018 Content-Type: text/plain; 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[209.85.220.65]) by mx.google.com with SMTPS id d81-v6sor13358468vkd.2.2018.10.31.07.04.53 for (Google Transport Security); Wed, 31 Oct 2018 07:04:53 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hfqzVOtP; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=a96yTV8wn2l6+VBtY/7yxFV7aynWWpJdrxYm6O/2iOk=; b=hfqzVOtPZO9Kf2pDXqek2I53fQsJ0KTPVZ6G8kS1cVlVnw5dEqVUYkazQuFD0sVF60 KoRwjHphZbc8vXAeWcopucS3moDWU3OXduDkXOl5b2XGURq81cntYMzMa4IuqRq4dJOp JqWGn3SOfWwh7FIIy50VCQX25SN93ywlvL1yk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=a96yTV8wn2l6+VBtY/7yxFV7aynWWpJdrxYm6O/2iOk=; b=TOMN7Gug/dn08x7NLJIBmQQmswvDbn9FIAOzCq4UINRKDf0lV/pewWDwoiKxhJ3IDz /s81bb9a4dLYiC+2iz6fvCSlaKCy3RKniSgiwmdZMI+o8CeBWQBTF86qJ/wnCMNR8Daa 5CfMU3kqF+UZ/0HAew1Rj7dOqgI8OwgmKFqENJjMStWpuZfdn5TBbPFW7kYmnmi0F2/2 oBt1OMv9vNQslP6K8/6dc5PnQxor27Jdf3ZXgZ0Two3gIYcQlgH3zZoRnxAQjBZHaw+h Bir/IAhD8CSVoQHEm9ldk78g71fcSiEiAv6BSvi0G/OsSUuTV4c7nYXd1kQN5S1wCRba AMtg== X-Gm-Message-State: AGRZ1gIei1qqqM4y2LO8U5vprjGYg+3ydoe0XKpUF3TSv01Pvqj6Lvrv ao7G3gmN8qHxxAsbt98FKDthCJTC X-Google-Smtp-Source: AJdET5dStCsNbWPWxiqsmv4nlWR+GG/ZT8u20H62/A+Nd9Ep7hL8mQjrUD822zT7bso6/MgcZsmY8g== X-Received: by 2002:a1f:1e09:: with SMTP id e9mr1390408vke.18.1540994692862; Wed, 31 Oct 2018 07:04:52 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:52 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 09/18] ARM: spectre-v2: warn about incorrect context switching functions Date: Wed, 31 Oct 2018 10:04:27 -0400 Message-Id: <20181031140436.2964-10-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit c44f366ea7c85e1be27d08f2f0880f4120698125 upstream. Warn at error level if the context switching function is not what we are expecting. This can happen with big.Little systems, which we currently do not support. Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long --- arch/arm/mm/proc-v7-bugs.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.17.1 diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c index 85a2e3d6263c..027b29f852f6 100644 --- a/arch/arm/mm/proc-v7-bugs.c +++ b/arch/arm/mm/proc-v7-bugs.c @@ -4,11 +4,15 @@ #include #include +#include #include #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); +extern void cpu_v7_iciallu_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); +extern void cpu_v7_bpiall_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); + static void harden_branch_predictor_bpiall(void) { write_sysreg(0, BPIALL); @@ -34,6 +38,8 @@ static void cpu_v7_spectre_init(void) case ARM_CPU_PART_CORTEX_A17: case ARM_CPU_PART_CORTEX_A73: case ARM_CPU_PART_CORTEX_A75: + if (processor.switch_mm != cpu_v7_bpiall_switch_mm) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = harden_branch_predictor_bpiall; spectre_v2_method = "BPIALL"; @@ -41,6 +47,8 @@ static void cpu_v7_spectre_init(void) case ARM_CPU_PART_CORTEX_A15: case ARM_CPU_PART_BRAHMA_B15: + if (processor.switch_mm != cpu_v7_iciallu_switch_mm) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = harden_branch_predictor_iciallu; spectre_v2_method = "ICIALLU"; @@ -49,6 +57,11 @@ static void cpu_v7_spectre_init(void) if (spectre_v2_method) pr_info("CPU%u: Spectre v2: using %s workaround\n", smp_processor_id(), spectre_v2_method); + return; + +bl_error: + pr_err("CPU%u: Spectre v2: incorrect context switching function, system vulnerable\n", + cpu); } #else static void cpu_v7_spectre_init(void) From patchwork Wed Oct 31 14:04:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149829 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836215ljp; Wed, 31 Oct 2018 07:04:55 -0700 (PDT) X-Received: by 2002:a67:843:: with SMTP id 64mr1348502vsi.166.1540994694984; Wed, 31 Oct 2018 07:04:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994694; cv=none; d=google.com; s=arc-20160816; b=sVIN0Y7+nTVqvXAYPHlK2h+N8ewT5dncHVo/+osFvGDiDBLciheSXYkaAKygBzY0z6 Kwcx60CnY9WE80a319oxWtCNhtyGXKc3RYnLC0uCSvSaLxc7J8OIBW/WLrp5fDBBao02 mqWnhwj/PchrtAWHPmeKS2qCydshT+MDhuk3rgZgBnp6LcKOxyS8txOkGFDxlZ8PTrSC hEtCNRTj593gp0hu20BPH6HUfKpyv/A46S+b5/ZV3jZtBSZ7tTKHyJGHY0sgmyo5U6hz s6mU+OqjcurPMn3idbUZZHvSyFVJ/Es0oTbUMyckhZ6cUK0CtV7S3fOQW+a38u6SBS2v PNlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=u2E0Yv/m/5J4oG7CM84UYhk7NYJmPFxPsB+ynyFPbSs=; b=I+IEr7JzE0FLXVRFj3iNGuUrmbre2Fhx4ta8oqZzp61p3oofBYAEoq6c2d11IGJ46J U/JXl6RxYre2ZYcmYC8j51Skz9Z8WxS/iDlyVeVV1HxhZQlu/k+yz3L0PPVH2gG7KVBi eR29JZ7LIrtaMMjgTslnIj2rV+kFCmwSKTNYUhBIznhxp87W3165wqbGbylpnIMlnrxO CRYfr93QyhaP34jZCZObDeL/tMKPy6YIdguLr8+nkbMXYwbjM9gdje0lFgJVX+bHFrU/ uFcCByY/IFfSHN5Zb2uXRlp+1m10rG0uD5bOS2gXCfQvLyhu8VJR/QY13KeJpnnDyhis aBTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g6v5uzAF; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id r134sor1213171vsc.112.2018.10.31.07.04.54 for (Google Transport Security); Wed, 31 Oct 2018 07:04:54 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g6v5uzAF; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u2E0Yv/m/5J4oG7CM84UYhk7NYJmPFxPsB+ynyFPbSs=; b=g6v5uzAF3qUXVjklFMYFzqczf18m7XMmercqnWO/K3DNCTccdZ0Vq7juTTbWkkJEf3 +es1Zp4TxdRKQxvZOCeKbMwzvBVXuyES4ByCkYkA5qZKtW7E2S891WPVw/UTxG79pT/E OlAipQ0Np8easI7ivf5pWRT8MILp8yDyV6Abc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u2E0Yv/m/5J4oG7CM84UYhk7NYJmPFxPsB+ynyFPbSs=; b=OJmFLiMxm66blge733rgdJ2Qq6wGg4mii9zVh1D+fJA9jNn8K/6wvHnat7wAk/Y4+F NW3TUU/nUvZQZjdtQ1JvN0lD/0V+vWN03zTgdbUHhxo2rMANwtOqVfRuBlEGlDo6ewdg T+fVD2OU205y7lAIatmxeswNeCjaFdhyXa9P4kRdVEZaKWhboaeu3V2hvGnJ2Cckw2s+ 5NilTBso4zETC5LlxEwFshYohsFXZRmtVQ+rwWa2QCSojEh/PdQIOsU1+ozdmsVivL4l 5Q1ftSe3HlZX/u5U4c7WWay5ovVLD4Bq/PaXkbTmZpZaOup9Tfc6altaBXfMFDlaNi1S kLDA== X-Gm-Message-State: AGRZ1gK5eI3xQjuYQDF1ZnXsYshXFIluHf2xp1Bl+o6WCByIs/bXqR6m 0s+UDiKHrvZyqZCOn6r8p6HXN1HN X-Google-Smtp-Source: AJdET5enYe5EgvpyJHiIHraDNt6eodlHikioMWR8GLZdT9/37J7lwXfK5nfuaCGknmjtGTmDAe9JIA== X-Received: by 2002:a67:98c3:: with SMTP id g64mr1356311vsh.204.1540994694361; Wed, 31 Oct 2018 07:04:54 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:53 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 10/18] ARM: spectre-v1: add speculation barrier (csdb) macros Date: Wed, 31 Oct 2018 10:04:28 -0400 Message-Id: <20181031140436.2964-11-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit a78d156587931a2c3b354534aa772febf6c9e855 upstream. Add assembly and C macros for the new CSDB instruction. Signed-off-by: Russell King Acked-by: Mark Rutland Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/include/asm/assembler.h | 8 ++++++++ arch/arm/include/asm/barrier.h | 13 +++++++++++++ 2 files changed, 21 insertions(+) -- 2.17.1 diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 4a275fba6059..307901f88a1e 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -441,6 +441,14 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) .size \name , . - \name .endm + .macro csdb +#ifdef CONFIG_THUMB2_KERNEL + .inst.w 0xf3af8014 +#else + .inst 0xe320f014 +#endif + .endm + .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req #ifndef CONFIG_CPU_USE_DOMAINS adds \tmp, \addr, #\size - 1 diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index 3ff5642d9788..d705be47a1ad 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -16,6 +16,12 @@ #define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory") #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory") +#ifdef CONFIG_THUMB2_KERNEL +#define CSDB ".inst.w 0xf3af8014" +#else +#define CSDB ".inst 0xe320f014" +#endif +#define csdb() __asm__ __volatile__(CSDB : : : "memory") #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ : : "r" (0) : "memory") @@ -36,6 +42,13 @@ #define dmb(x) __asm__ __volatile__ ("" : : : "memory") #endif +#ifndef CSDB +#define CSDB +#endif +#ifndef csdb +#define csdb() +#endif + #ifdef CONFIG_ARM_HEAVY_MB extern void (*soc_mb)(void); extern void arm_heavy_mb(void); From patchwork Wed Oct 31 14:04:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149830 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836267ljp; Wed, 31 Oct 2018 07:04:56 -0700 (PDT) X-Received: by 2002:a1f:c3c5:: with SMTP id t188-v6mr1381717vkf.67.1540994696585; Wed, 31 Oct 2018 07:04:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994696; cv=none; d=google.com; s=arc-20160816; b=CxKE3jJrCCwdez0XF6QZMy7Qt+LMqmn6kXg/tB7srKCgIJ60JUUe454hOGHEe0YXPM a9yT0uDUZc4oA4E9f3ApGDOGs6st4ca8EmwQUBYeSD8iE9YDjMXaC9Mp5fmXugba3ej8 NYsnxgyiooNb1xmIJF4ziwoD0XZ6mx13dwd2wsuzy3YDzdx405dS/40IBrdoOjH13p+U TJEHYWkBk60he8lXdObNvghErwRAYRevZGf1rnfXcageuZE327SjBrbeAu8sIGBp8dLs /yVJMLswl9k+sCbFihWhFQBhxgL3Oq5QsOopeDGik0+xjrQ3a37V8P8pxN3cxXD28er7 Mqzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=w3vN2kbKb/kbQFzTan22brttmozPByYhPX1tSkHW2yg=; b=U6CcJmdYwEaGtDV48J4j07yGTtu5tENIL+cUGMbxUecvF5e4UO7jgj7B22Tva6ySo6 qbIndWRnMCsMxx8wCQBqwyAd864g0xHPbd40xoRImcnGPJLmZFGow9/Qz4IsEmWkOt38 RWGpi9iHjeVy2nKWhddq9Mp/ctjOPEw6PMuvvc8HQbL1jmynRiv+7cMgRjYOZ1sdOAOn Ebe7tpnus0Ve0JEnNFD868gapYAQV4xiV7ZnulPZz/s1l6gL2xG3ZV9raBm2e9UHu4UQ rqGYYtUrcA2MvtsgkbLJlkM/QLYsxgPq1e89SKyth47GjoA+AiqJd/NglksOvqGCHYKU bERA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=STUl5Yof; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id t4sor16126487vsa.43.2018.10.31.07.04.56 for (Google Transport Security); Wed, 31 Oct 2018 07:04:56 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=STUl5Yof; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w3vN2kbKb/kbQFzTan22brttmozPByYhPX1tSkHW2yg=; b=STUl5YofniCjcwN5T161W4MyVgqI+BR29z63vStJnovJLgPmpJL2pB+F47OIaWJep4 m/qKqPjB2kHjPJPosSpLKGc9GglwksIke68X9mIEAvaw+8mYS719+GqcOgddit+uQw8x gk63Y9qWBYQHqKxlWl4vKaEwozjEAi4+aDx0Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w3vN2kbKb/kbQFzTan22brttmozPByYhPX1tSkHW2yg=; b=p57NoTT40sDAIkNbtDTBGlpkQLnZQCEzo69kPuEKUC5DXn03VADUvcwcLNvdzGjOs+ mhInp5mrSw+11ZitAUZ2ltMH2xxUyFM4yQO9DaiZn3BvH5NcsTXnpKJ+x28xkdG5vBns rPnNJ4K5Bkl8rddmXVnzCn+xqoXWJOOcIqVFS67BBu0F3ZWkt6vXxyb5aeWMdHwR7bWt 1Z8PHbVdDb8dc8CQBnvNf4AwixZa83sDoBSOrH54h60sSn3cjRqrvIaap3DuFc/yPxkx pvlC+rLfKMaSIye5vuWaoD9a8wcIzwcBXM7prX6mEPwFrHs2PmHPPezdvGT+yI6zGDUT kkPA== X-Gm-Message-State: AGRZ1gKO+8s7ADPG7f3vrUZTwdCxaxpqMzofY+X/RRl2KBpmziQz5e67 5tdsN4mBXsFNf0KjVgk/xVQMoxdg X-Google-Smtp-Source: AJdET5f0g1dmpoF9Dkr/VU5nLPVQt/U4r2tC+J6LA8A0zvzIGgrJOkQNk1CSDDqhn9MXuRGc3XkpaQ== X-Received: by 2002:a67:bc1:: with SMTP id 184mr1309593vsl.153.1540994695876; Wed, 31 Oct 2018 07:04:55 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:55 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 11/18] ARM: spectre-v1: add array_index_mask_nospec() implementation Date: Wed, 31 Oct 2018 10:04:29 -0400 Message-Id: <20181031140436.2964-12-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit 1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613 upstream. Add an implementation of the array_index_mask_nospec() function for mitigating Spectre variant 1 throughout the kernel. Signed-off-by: Russell King Acked-by: Mark Rutland Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/include/asm/barrier.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.17.1 diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index d705be47a1ad..85eb7ef44a18 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -106,5 +106,24 @@ do { \ #define smp_mb__before_atomic() smp_mb() #define smp_mb__after_atomic() smp_mb() +#ifdef CONFIG_CPU_SPECTRE +static inline unsigned long array_index_mask_nospec(unsigned long idx, + unsigned long sz) +{ + unsigned long mask; + + asm volatile( + "cmp %1, %2\n" + " sbc %0, %1, %1\n" + CSDB + : "=r" (mask) + : "r" (idx), "Ir" (sz) + : "cc"); + + return mask; +} +#define array_index_mask_nospec array_index_mask_nospec +#endif + #endif /* !__ASSEMBLY__ */ #endif /* __ASM_BARRIER_H */ From patchwork Wed Oct 31 14:04:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149831 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836321ljp; Wed, 31 Oct 2018 07:04:58 -0700 (PDT) X-Received: by 2002:a67:38d8:: with SMTP id n85mr1341799vsi.30.1540994698370; Wed, 31 Oct 2018 07:04:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994698; cv=none; d=google.com; s=arc-20160816; b=jyxGDscmbdO/x7Okz70rBZCq7Z9+deQ4vH2jHol6DW434UvAnifjf51Jh1fE4YC2HA G500TJZYKOjjvTeRTNxb9A10XLTZa/zDDV8F5FPLP11EQAgCb+3bWDq0Sdv2mR0SX5Zt CdANSI1IxeRVVJ0yflCpRoxCAIwpM1oTHoUKycU7LgMJVulnPlfxj1VXXFQR/ZJoNn31 kjIql0kQyX8djlQ53rvHHEtizKr5xT2+aRPdF/VDRTfP0SHq+Q0F3fE9yJ0Jnt5t3l/U h/DMtKt5zFP5eP/R7iwUmreCpBTUqVv+gKVHwcKHFHcp2at7dUQPiRzPJo7efzX4lXBU Fy2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=867jEO/qR6LH2/a6FnPf5KwETFlGxEbyzbFnAsxeVQY=; b=G8Bx64ALGL1fr4HF8g6TAINVPHeM0H9jyocKH+2+Hi8caHpEwyyp+mLGXSZZK3T57o nn12Yo5YvwkEr2MtdMyTqs907xpm3ejji8/2VIrH4tss+8cqk0IQ7pBozzmONz8sEvHE dijyaI/TjZbwFb/wGF3TgRn/JCeaCmH0LHEeyRmFduIo/4MJr0r6K4mRm3E41wv02x70 WW8ibWDfIUVxXB4xancOZvGPSq35aLSTkwDP2Y5WKpDBzFm8OtYgOQHs4DxqKwSghNVt UyJEpSTXwJ57ygd5qJTyLV9yFdQQLAJwvdqAcZx2qmzh71cuflg8i3xOQyg5daOr+Fvz ChBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=adCmGBkC; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. 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Prevent speculation at the syscall table decoding by clamping the index used to zero on invalid system call numbers, and using the csdb speculative barrier. Signed-off-by: Russell King Acked-by: Mark Rutland Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/kernel/entry-common.S | 18 +++++++----------- arch/arm/kernel/entry-header.S | 25 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 30a7228eaceb..e969b18d9ff9 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -223,9 +223,7 @@ local_restart: tst r10, #_TIF_SYSCALL_WORK @ are we tracing syscalls? bne __sys_trace - cmp scno, #NR_syscalls @ check upper syscall limit - badr lr, ret_fast_syscall @ return address - ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine + invoke_syscall tbl, scno, r10, ret_fast_syscall add r1, sp, #S_OFF 2: cmp scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE) @@ -258,14 +256,8 @@ __sys_trace: mov r1, scno add r0, sp, #S_OFF bl syscall_trace_enter - - badr lr, __sys_trace_return @ return address - mov scno, r0 @ syscall number (possibly new) - add r1, sp, #S_R0 + S_OFF @ pointer to regs - cmp scno, #NR_syscalls @ check upper syscall limit - ldmccia r1, {r0 - r6} @ have to reload r0 - r6 - stmccia sp, {r4, r5} @ and update the stack args - ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine + mov scno, r0 + invoke_syscall tbl, scno, r10, __sys_trace_return, reload=1 cmp scno, #-1 @ skip the syscall? bne 2b add sp, sp, #S_OFF @ restore stack @@ -317,6 +309,10 @@ sys_syscall: bic scno, r0, #__NR_OABI_SYSCALL_BASE cmp scno, #__NR_syscall - __NR_SYSCALL_BASE cmpne scno, #NR_syscalls @ check range +#ifdef CONFIG_CPU_SPECTRE + movhs scno, #0 + csdb +#endif stmloia sp, {r5, r6} @ shuffle args movlo r0, r1 movlo r1, r2 diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 6d243e830516..86dfee487e24 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -373,6 +373,31 @@ #endif .endm + .macro invoke_syscall, table, nr, tmp, ret, reload=0 +#ifdef CONFIG_CPU_SPECTRE + mov \tmp, \nr + cmp \tmp, #NR_syscalls @ check upper syscall limit + movcs \tmp, #0 + csdb + badr lr, \ret @ return address + .if \reload + add r1, sp, #S_R0 + S_OFF @ pointer to regs + ldmccia r1, {r0 - r6} @ reload r0-r6 + stmccia sp, {r4, r5} @ update stack arguments + .endif + ldrcc pc, [\table, \tmp, lsl #2] @ call sys_* routine +#else + cmp \nr, #NR_syscalls @ check upper syscall limit + badr lr, \ret @ return address + .if \reload + add r1, sp, #S_R0 + S_OFF @ pointer to regs + ldmccia r1, {r0 - r6} @ reload r0-r6 + stmccia sp, {r4, r5} @ update stack arguments + .endif + ldrcc pc, [\table, \nr, lsl #2] @ call sys_* routine +#endif + .endm + /* * These are the registers used in the syscall handler, and allow us to * have in theory up to 7 arguments to a function - r0 to r6. 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[209.85.220.65]) by mx.google.com with SMTPS id b64sor1841426vsb.118.2018.10.31.07.05.00 for (Google Transport Security); Wed, 31 Oct 2018 07:05:00 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DtDDWveW; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qa5Mci7cMAGvawpk5a6Wtf5f3dHfZJJnbCtGATwkUMw=; b=DtDDWveWgpuBfa6qJmT18PDqLti6FdQuxLDwm1idV7usJS+yUPTpgBmPGDqWLfrBhF 0YmoJXIkcYwPhr9MnmqkFeCo9YjaFCUTDeOXr1LlXSUgB3ruaytzrhYxAR9Z4NH5Smi2 iL8mtQ/Da6M/AgEWcoAmuH6GdYT2PHu3kMAzE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qa5Mci7cMAGvawpk5a6Wtf5f3dHfZJJnbCtGATwkUMw=; b=eSgdlp/urLMC2yaFBY5DM21+LXeaH4B98xPSx8zgB/v4yTZTximH5wiO2L7Ywnd/q8 RR3W0XlwlfyHtnqG7fxsIFg/altyB5FWihRqYEvB5XJ+3NPTHbyqEhjMlY71IjirFaw7 hqJATZ+kT1x2stBLHircTrTmi+vtQWTtgLSf6Z7ZoQql/KM6y4MRqgR/XWvf72lKFmW5 rE4XbbzX7jRwM0rXouiyGtf/F1rZqgyYBhKLHjWpmd0JHxBu2ns0RXokPqq4aCaF4OqF ifyulXG82AOU3tbD0eX8i+d+5b90vop1kpf2ycO1X4p4hD6mYy2FmZUmpiUJ/2V8B3AH RKNg== X-Gm-Message-State: AGRZ1gJVXKbvyZ+5oU46N1SBTbCgUnlFENt8rMVriYKRUZrSGEQ7qzBl K23/Dsm1U7IlymiTc1jaXgrBZzbT X-Google-Smtp-Source: AJdET5ftirgmWeTPiJDmSGosSeIJ7lkQUnleDm8eOJf9SVT9wMBYEAsm8kFYb8U9TMheMqa70suLWw== X-Received: by 2002:a67:33d1:: with SMTP id z200mr1345315vsz.40.1540994699538; Wed, 31 Oct 2018 07:04:59 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:58 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 13/18] ARM: signal: copy registers using __copy_from_user() Date: Wed, 31 Oct 2018 10:04:31 -0400 Message-Id: <20181031140436.2964-14-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit c32cd419d6650e42b9cdebb83c672ec945e6bd7e upstream. __get_user_error() is used as a fast accessor to make copying structure members in the signal handling path as efficient as possible. However, with software PAN and the recent Spectre variant 1, the efficiency is reduced as these are no longer fast accessors. In the case of software PAN, it has to switch the domain register around each access, and with Spectre variant 1, it would have to repeat the access_ok() check for each access. It becomes much more efficient to use __copy_from_user() instead, so let's use this for the ARM integer registers. Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long --- arch/arm/kernel/signal.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 7b8f2141427b..a592bc0287f8 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -141,6 +141,7 @@ struct rt_sigframe { static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf) { + struct sigcontext context; struct aux_sigframe __user *aux; sigset_t set; int err; @@ -149,23 +150,26 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf) if (err == 0) set_current_blocked(&set); - __get_user_error(regs->ARM_r0, &sf->uc.uc_mcontext.arm_r0, err); - __get_user_error(regs->ARM_r1, &sf->uc.uc_mcontext.arm_r1, err); - __get_user_error(regs->ARM_r2, &sf->uc.uc_mcontext.arm_r2, err); - __get_user_error(regs->ARM_r3, &sf->uc.uc_mcontext.arm_r3, err); - __get_user_error(regs->ARM_r4, &sf->uc.uc_mcontext.arm_r4, err); - __get_user_error(regs->ARM_r5, &sf->uc.uc_mcontext.arm_r5, err); - __get_user_error(regs->ARM_r6, &sf->uc.uc_mcontext.arm_r6, err); - __get_user_error(regs->ARM_r7, &sf->uc.uc_mcontext.arm_r7, err); - __get_user_error(regs->ARM_r8, &sf->uc.uc_mcontext.arm_r8, err); - __get_user_error(regs->ARM_r9, &sf->uc.uc_mcontext.arm_r9, err); - __get_user_error(regs->ARM_r10, &sf->uc.uc_mcontext.arm_r10, err); - __get_user_error(regs->ARM_fp, &sf->uc.uc_mcontext.arm_fp, err); - __get_user_error(regs->ARM_ip, &sf->uc.uc_mcontext.arm_ip, err); - __get_user_error(regs->ARM_sp, &sf->uc.uc_mcontext.arm_sp, err); - __get_user_error(regs->ARM_lr, &sf->uc.uc_mcontext.arm_lr, err); - __get_user_error(regs->ARM_pc, &sf->uc.uc_mcontext.arm_pc, err); - __get_user_error(regs->ARM_cpsr, &sf->uc.uc_mcontext.arm_cpsr, err); + err |= __copy_from_user(&context, &sf->uc.uc_mcontext, sizeof(context)); + if (err == 0) { + regs->ARM_r0 = context.arm_r0; + regs->ARM_r1 = context.arm_r1; + regs->ARM_r2 = context.arm_r2; + regs->ARM_r3 = context.arm_r3; + regs->ARM_r4 = context.arm_r4; + regs->ARM_r5 = context.arm_r5; + regs->ARM_r6 = context.arm_r6; + regs->ARM_r7 = context.arm_r7; + regs->ARM_r8 = context.arm_r8; + regs->ARM_r9 = context.arm_r9; + regs->ARM_r10 = context.arm_r10; + regs->ARM_fp = context.arm_fp; + regs->ARM_ip = context.arm_ip; + regs->ARM_sp = context.arm_sp; + regs->ARM_lr = context.arm_lr; + regs->ARM_pc = context.arm_pc; + regs->ARM_cpsr = context.arm_cpsr; + } err |= !valid_user_regs(regs); From patchwork Wed Oct 31 14:04:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149834 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836450ljp; Wed, 31 Oct 2018 07:05:04 -0700 (PDT) X-Received: by 2002:a67:8a88:: with SMTP id m130mr1331330vsd.206.1540994702612; Wed, 31 Oct 2018 07:05:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994701; cv=none; d=google.com; s=arc-20160816; b=jWempYuMbOEF9hAws4I7aTVsghrMcQntFE6YdBErTrSSZZicr8rvR8ju/YA3gpewVU gWh69V82/95uf3gBNi+y5VT6S/MsxyvVB7HmcZcjz1ITiJWNaxf6akHCKu17sqM51N3A 8RDPaYbZ7nnXSeHOFVupQV8TuXdekSU3YOwEBkcOpoGUtfvR9ESTJGRzdwsu+AX83ejs +wAIAVUYdHz1uxlW6JKBkfS9QZNBiPj25qFfA4cUDjh3bxKcH5ktfMaqEu2y1cQFoAhw iUrZ+w8JFOtO/uVkxcTB3pIZSRzmQX0f5hCBmfjJFY2CeZm3dBec0FpJv1VWAyBHEkut 5EeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xy/UIMoNnpuW3No4gkHcbKZisJ/hrnSGJPSz10O8lGk=; b=fh7n/KN+HYa3nRpRKEbNrV+PQ/hqsHXvjKurTyJCRCfa4htWpY34iBK/yLd1FCoKm/ lb2GUDQJnHQvOyxa9EbO1uWGjudPJ4KegTYxcUC40tueskPcudg8xCb9DzTUv7a4mNWh gF1/eyjj3Mxj1MPbGiRfrM4JV9KCh02ersPHtNCuc5RXWMlJ00AgeqL5/ZMq3rpf1boN yu1SRgx+wehZU/lrUDsrAxJ3CeS+fZkAcQjQS6jKcs1kfNwHFw/2DIYcQYDXlUiKA6i+ nJbmuvF/s5X40RpIbVn/OFQ/6TgK8WB0HSL/llAlIVD95ZYWgAwyl5Bho7Zdbeat4BKz N5sQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MZwhwEoP; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id i188sor4728677vsi.84.2018.10.31.07.05.01 for (Google Transport Security); Wed, 31 Oct 2018 07:05:01 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MZwhwEoP; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xy/UIMoNnpuW3No4gkHcbKZisJ/hrnSGJPSz10O8lGk=; b=MZwhwEoPJCA+ODVwgJ4XgLeYnpdizOj7q0/rEpOfwY++TmLDzY1MZR/YEebCCEmtig 3yHLzekj2+d8jdOPAvv2i08cBcTxZyzn9S6OYKno7dMBknAN1z5Dfd+Cx3qJz5YBUhy0 2WluV9EpO1p+tc3/m9Wr0iob2f5CtNCLwI1aQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xy/UIMoNnpuW3No4gkHcbKZisJ/hrnSGJPSz10O8lGk=; b=EoMwO2VzJTWEHmEQl9e9Fg2OKjtE2cZPFzQlU+kPf6TMz700w0qakWS5lKEca5FRlw hRMsOhLcrN9gW4UcOExWT1Xaiodyw31cUTIq69DaPSPnNZLJcbfn5NvReBvzCPdwY6YX m0YRTuWbxIVjesigKOo3c/mn9hFN5W4yOitUqTFZfSVwXy7MnqwbMy67PtOguNPqYo9X F+iJ3XOklq2SjQ985/PhgdHdl15tfMGK9INsoevBWCJBQOsdW/ppX4YSodx6AzqLShU3 8bFRx3Ii28E3QqPrNMs3/LbeNNbJ1L2veFIML/Pu28HfXUvEihE9fztzO+/gfJganfPm qL7g== X-Gm-Message-State: AGRZ1gKKDX9TJ5H07grFfcyDgSq9Y/lSOKMgr3FytmQg21ZibJg2+s9J bZkS3Pnf7dY5jx1gywlbmMB8cWDk X-Google-Smtp-Source: AJdET5ffmNYm9V16tfW6pqMJPFfr/I/HzcRWDs5/DUoXL5ue22XZrKmddQSR4EMhaqe+MGRPGYtEyg== X-Received: by 2002:a67:2802:: with SMTP id o2mr1345033vso.220.1540994701155; Wed, 31 Oct 2018 07:05:01 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:05:00 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 14/18] ARM: vfp: use __copy_from_user() when restoring VFP state Date: Wed, 31 Oct 2018 10:04:32 -0400 Message-Id: <20181031140436.2964-15-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit 42019fc50dfadb219f9e6ddf4c354f3837057d80 upstream. __get_user_error() is used as a fast accessor to make copying structure members in the signal handling path as efficient as possible. However, with software PAN and the recent Spectre variant 1, the efficiency is reduced as these are no longer fast accessors. In the case of software PAN, it has to switch the domain register around each access, and with Spectre variant 1, it would have to repeat the access_ok() check for each access. Use __copy_from_user() rather than __get_user_err() for individual members when restoring VFP state. Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long --- arch/arm/include/asm/thread_info.h | 4 ++-- arch/arm/kernel/signal.c | 18 ++++++++---------- arch/arm/vfp/vfpmodule.c | 17 +++++++---------- 3 files changed, 17 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 776757d1604a..57d2ad9c75ca 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -126,8 +126,8 @@ struct user_vfp_exc; extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *, struct user_vfp_exc __user *); -extern int vfp_restore_user_hwstate(struct user_vfp __user *, - struct user_vfp_exc __user *); +extern int vfp_restore_user_hwstate(struct user_vfp *, + struct user_vfp_exc *); #endif /* diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index a592bc0287f8..76f85c38f2b8 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -107,21 +107,19 @@ static int preserve_vfp_context(struct vfp_sigframe __user *frame) return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc); } -static int restore_vfp_context(struct vfp_sigframe __user *frame) +static int restore_vfp_context(struct vfp_sigframe __user *auxp) { - unsigned long magic; - unsigned long size; - int err = 0; - - __get_user_error(magic, &frame->magic, err); - __get_user_error(size, &frame->size, err); + struct vfp_sigframe frame; + int err; + err = __copy_from_user(&frame, (char __user *) auxp, sizeof(frame)); if (err) - return -EFAULT; - if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE) + return err; + + if (frame.magic != VFP_MAGIC || frame.size != VFP_STORAGE_SIZE) return -EINVAL; - return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc); + return vfp_restore_user_hwstate(&frame.ufp, &frame.ufp_exc); } #endif diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 2a61e4b04600..7aa6366b2a8d 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -601,13 +601,11 @@ int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp, } /* Sanitise and restore the current VFP state from the provided structures. */ -int vfp_restore_user_hwstate(struct user_vfp __user *ufp, - struct user_vfp_exc __user *ufp_exc) +int vfp_restore_user_hwstate(struct user_vfp *ufp, struct user_vfp_exc *ufp_exc) { struct thread_info *thread = current_thread_info(); struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; unsigned long fpexc; - int err = 0; /* Disable VFP to avoid corrupting the new thread state. */ vfp_flush_hwstate(thread); @@ -616,17 +614,16 @@ int vfp_restore_user_hwstate(struct user_vfp __user *ufp, * Copy the floating point registers. There can be unused * registers see asm/hwcap.h for details. */ - err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs, - sizeof(hwstate->fpregs)); + memcpy(&hwstate->fpregs, &ufp->fpregs, sizeof(hwstate->fpregs)); /* * Copy the status and control register. */ - __get_user_error(hwstate->fpscr, &ufp->fpscr, err); + hwstate->fpscr = ufp->fpscr; /* * Sanitise and restore the exception registers. */ - __get_user_error(fpexc, &ufp_exc->fpexc, err); + fpexc = ufp_exc->fpexc; /* Ensure the VFP is enabled. */ fpexc |= FPEXC_EN; @@ -635,10 +632,10 @@ int vfp_restore_user_hwstate(struct user_vfp __user *ufp, fpexc &= ~(FPEXC_EX | FPEXC_FP2V); hwstate->fpexc = fpexc; - __get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err); - __get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err); + hwstate->fpinst = ufp_exc->fpinst; + hwstate->fpinst2 = ufp_exc->fpinst2; - return err ? -EFAULT : 0; + return 0; } /* From patchwork Wed Oct 31 14:04:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149833 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836441ljp; Wed, 31 Oct 2018 07:05:03 -0700 (PDT) X-Received: by 2002:ab0:6448:: with SMTP id j8mr1474040uap.48.1540994703550; Wed, 31 Oct 2018 07:05:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994703; cv=none; d=google.com; s=arc-20160816; b=olapSa5y0maqvn56LYIiXXwSsq3WxUU0g8nLhV6Jeo4NjESJNE1sgvODHEMxk3q+pQ HN8d4FZ+JDULrnGGYkp+3FbMmhDrSTw+Zz/vUplVTs8S8KFm8Www4eoIxCuvm2XAiR+6 iFb8cbEQxoHWJpbCD9I6gZ4usGk9nSYY1M0kc5lPXqjaQmOA3XceDh0a/Hq7gLaqRy91 It6VSMifV02tnwj6xqGAuuClxMEYG5ki9gMiuygQB6O4dJlhGNsN9t6gLJTsLYmVMatA YEOzomD9MYXYkYDQghzeZqRn0EFXEtPY5rwoiGrarE64nruXnBh5a8/3D3RzPaQcSfiA QwLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IaoQxTRrxrYBzQWir0u9ErhYqEdp4e5JRmU48kGigvg=; b=FyHa8gailwflcMFAj/9vUyzobPr9y7ZKKbvcH07lBLJZSLByf4SoXoTM3qrUqSAoYr ot/J4MOX5lhtI/zWyVlD9aswp0U6dnQNnXpB0PFkqr8s9K1pwZw2s4J3TKrrcnMfLIUP 3ay/OA3TM8sEQLuGzgrheNmSa0mEDZdImwXiNpIS/blm3yt/bDJJfn0P62zW2GoQE2Kq kRSrjjdY7HBU/hids3FVWKRl0SMTITMa/Cv+4IeGjype5NnyE4ayNUV/lhMzoND12imM Ee+BtJhwTje0a1EW4wjawv2zp6dFBLZTXOq5XMLgrwJf8Fjspen19HYGQ/g8aCfAd6Jb z7ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lm3yNeU7; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id 2sor1772964vse.1.2018.10.31.07.05.03 for (Google Transport Security); Wed, 31 Oct 2018 07:05:03 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lm3yNeU7; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IaoQxTRrxrYBzQWir0u9ErhYqEdp4e5JRmU48kGigvg=; b=Lm3yNeU7dp3fVMR9ihnBDfuEp12hLVC0S2qU8SfRGF0kNy9zLJghafvcu7tgMaodyM 6+zC0pbr2Dw8va3wdODAASQeB85OFZlLVVAf1zOn9Q6AaJTs500Helom6WmRNB8xGMTf fJPV0y37RuwWglISJQTySfw/V1VQEnJbbC+6M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IaoQxTRrxrYBzQWir0u9ErhYqEdp4e5JRmU48kGigvg=; b=EDogqwHR81ZpE8/3VZt/dmMWx9YpL7+TuSoVVAEPBUxcE/fKHq2Ns0mZLa7GGSDHYZ qblnipDAsJ+URgUrrQrz8Ir0lFKco9NPQV4mxeqcv7wiRcuTmq4Rxw7YIPY4l+mHPt4w mkgvVJjNLjYBi9s9vPIeC2L2b62WgRyslk0qH401ihctoyqrGaPsp592ApUaNu6SIxWF R3X5/fkae+zOxysukVzvhiQAi+PZJahHQwKHwzEBcaDSh/5yGH52Xx5rN0Uu55M5YaBC SvPLcFXVyBdnzzavROkUNzenwZh6KBYliQtK6RsEWnv+p1jOcFv890C0lA94CrlSULWw OyAA== X-Gm-Message-State: AGRZ1gIMb6PtKqSNC/bY9m/3305Y7N4icASfZIRWrNU+y4nVdh2yAQc+ d7On1TH/98hqyG8CIzH0gTDMigBL X-Google-Smtp-Source: AJdET5e4SBUncKduPx1etMO6a239DXlBZq5CjYL3QSkrykrAb/NDVQi5KDuo5pzTAKFHjHn1FQlO2Q== X-Received: by 2002:a67:f441:: with SMTP id r1mr1340661vsn.164.1540994702737; Wed, 31 Oct 2018 07:05:02 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.05.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:05:01 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 15/18] ARM: oabi-compat: copy semops using __copy_from_user() Date: Wed, 31 Oct 2018 10:04:33 -0400 Message-Id: <20181031140436.2964-16-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit 8c8484a1c18e3231648f5ba7cc5ffb7fd70b3ca4 upstream. __get_user_error() is used as a fast accessor to make copying structure members as efficient as possible. However, with software PAN and the recent Spectre variant 1, the efficiency is reduced as these are no longer fast accessors. In the case of software PAN, it has to switch the domain register around each access, and with Spectre variant 1, it would have to repeat the access_ok() check for each access. Rather than using __get_user_error() to copy each semops element member, copy each semops element in full using __copy_from_user(). Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long --- arch/arm/kernel/sys_oabi-compat.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c index 5f221acd21ae..640748e27035 100644 --- a/arch/arm/kernel/sys_oabi-compat.c +++ b/arch/arm/kernel/sys_oabi-compat.c @@ -328,9 +328,11 @@ asmlinkage long sys_oabi_semtimedop(int semid, return -ENOMEM; err = 0; for (i = 0; i < nsops; i++) { - __get_user_error(sops[i].sem_num, &tsops->sem_num, err); - __get_user_error(sops[i].sem_op, &tsops->sem_op, err); - __get_user_error(sops[i].sem_flg, &tsops->sem_flg, err); + struct oabi_sembuf osb; + err |= __copy_from_user(&osb, tsops, sizeof(osb)); + sops[i].sem_num = osb.sem_num; + sops[i].sem_op = osb.sem_op; + sops[i].sem_flg = osb.sem_flg; tsops++; } if (timeout) { From patchwork Wed Oct 31 14:04:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149835 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836467ljp; Wed, 31 Oct 2018 07:05:05 -0700 (PDT) X-Received: by 2002:a67:d309:: with SMTP id a9mr1322857vsj.229.1540994705198; Wed, 31 Oct 2018 07:05:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994705; cv=none; d=google.com; s=arc-20160816; b=jJle+wGKJCe4Htm6h1IB6PYDJM6BLn4wouzmegGm+1Gfj+BXjT8s3sczMhd20cLSLw 7dtr1Fcu9ZQEkJ1hh+Rcyh9mmGAOjDkrYCD/5gNMhT/Z+nj7uJVURjpjsZttl5KVsvdn Dx7fS9sAE/NwBQ9qgean/0nhxt5W4A83hjAdY3s4ty9unlROoc4C6RY+njqw/W7s8Scn ac2WAvZVjkgIQYFlkUNRyHBkmYH9jbyJAMgFc0ZLjfnGpzRKgjvEFSI0sF9SUc5QCRvD n3yPr3GnLl4BzNHWD4lMYpfPy6wafuW/aYUIoI5F2UGt8f3Vsp7Hgd0Yi4oaF3Cvko4+ R0jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qFPA/Nuv5CvVFze52wqR0w87HvJAXZ36fXdUmDk6ygE=; b=q0nuZCWgh4D7LGy/Swxcjy2vvRj1a0Dv1lQwUJHsAYoTuoIIAwnQfCYsqfNappRTij 1mg0HTOAfbSXgSMmwSP9XrvxtWTkeNp2wMv3Dnj8JcQ15iubpOG3Sl4UCNi1PtcidJv6 Df73SIhFSlikypB2AdNP8szS1hn2tCCug70LdyUpJXeoIyqEFLWa+PlhMyQXT/EXIz1o 1kojCY/NPcLGhwo7XlOElf2WHutKm1MDt8YVcMOmcy1YNPSNfp3RPp1BSDjFmkxJ/sjn ONfESh5KKeUXG0X7+A3ZqiSK2M9ZEpcxkRFSUh5Y5ctK/bGyZuMTQLrNHEwOFNTChhku a8Xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JLMvTkIs; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. 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Borrow the x86 implementation of __inttype() to use in get_user() to select an integer type suitable to temporarily hold the result value. This is necessary to avoid propagating the volatile nature of the result argument, which can cause the following warning: lib/iov_iter.c:413:5: warning: optimization may eliminate reads and/or writes to register variables [-Wvolatile-register-var] Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long --- arch/arm/include/asm/uaccess.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index cd8b589111ba..968b50063431 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -122,6 +122,13 @@ static inline void set_fs(mm_segment_t fs) : "cc"); \ flag; }) +/* + * This is a type: either unsigned long, if the argument fits into + * that type, or otherwise unsigned long long. + */ +#define __inttype(x) \ + __typeof__(__builtin_choose_expr(sizeof(x) > sizeof(0UL), 0ULL, 0UL)) + /* * Single-value transfer routines. They automatically use the right * size if we just have the right pointer type. Note that the functions @@ -191,7 +198,7 @@ extern int __get_user_64t_4(void *); ({ \ unsigned long __limit = current_thread_info()->addr_limit - 1; \ register const typeof(*(p)) __user *__p asm("r0") = (p);\ - register typeof(x) __r2 asm("r2"); \ + register __inttype(x) __r2 asm("r2"); \ register unsigned long __l asm("r1") = __limit; \ register int __e asm("r0"); \ unsigned int __ua_flags = uaccess_save_and_enable(); \ From patchwork Wed Oct 31 14:04:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149836 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836538ljp; Wed, 31 Oct 2018 07:05:07 -0700 (PDT) X-Received: by 2002:a67:44dc:: with SMTP id y89mr1322273vsf.4.1540994707805; Wed, 31 Oct 2018 07:05:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994707; cv=none; d=google.com; s=arc-20160816; b=BSodtkg608Gy4gXv0f2CXPfDrjubSJuqqOjmGJGPLlF2HtLJQgpAEUdiu7Gi4NbnTy 5fjED+ibOUCXh3JL0dtepMGoL9nZGr69FUSwTLcOm0lYeaH9oZq44C6xNayUapFniMQD upxnR05V6++xGg0gxBkcc+Gi9oRIsyR2kakTp+zu+rZSStaYYsrzscojqQhIR04+wVfB VEMyFvLEBC+oeg90l2ixBjkOZGjUyYzcNQFEBng6kBc12etuHhzxAsVig/tXuTwEwLP3 sv+CrgIowcYEYApgDuEmXrmRas0/eQolxDX04Aa2QUoqRfCcjSRafSGt5eQeEl/8RQIB c4dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dKp7WarRb5ZEErL7wz6fxfKxyloFGIJqsAGrNR1dgaM=; b=tHd/N6QGVF/G/2xCXpmU2Bf6M50uR9fo0BrdJgDHq45V6j8Rcqynj08B4xxc2MaFM0 f3v+07iB21LCcZLw8bkFvMebg3sf5GQI9h4doPUCQV1wdK4RmXMsaizocGtDDLXISeMn aGzUlDUi6Rel9Wh9KHPnngFReoXJLU8WizbJOhKfG+PtcuOrh3apA4DPz7dBazuF0UUl 0KBTdyKxcFpQPHRDTpZ1wwG9Mqw9RlSO5l3z+OdN6pmpbKucRmmgVVcQkNtc/ofzKZ2c qzyaHvJoFWDBtiqfykwkI4Gy6TY9bSXugLPtXFphQCf47y6UAg5YJeeK5oaZ/lG4p4iO WVxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZP2kkHNK; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id 62sor9184433vku.41.2018.10.31.07.05.07 for (Google Transport Security); Wed, 31 Oct 2018 07:05:07 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZP2kkHNK; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dKp7WarRb5ZEErL7wz6fxfKxyloFGIJqsAGrNR1dgaM=; b=ZP2kkHNKUMA391jKIVFWRizRA60UjjCfYKn4LSUQvEzhPvyK+n03rQCVVF1bU5oOEE UCFEk5eg8T4kU/2mEluXSwcIfXF2J0aWPQCMWJjF43P2S/9jkBGQz7LernZ7GuFDdcmx 3XH8iVvde2h83GZPGI9LdJfyfoN6kFMkFjzSk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dKp7WarRb5ZEErL7wz6fxfKxyloFGIJqsAGrNR1dgaM=; b=e8kYwrM1Sl8oJtemeq0KWDkRg+5rydrn7Xpa5MLNPrQ520qyIbDaTunPXHoNkl9JPo QRH7hncOP6B/RWVFR5MDHdDsQ4vdSqCIdkjQqiUgbNiFw+mHbv8AT87AfuNcil62Ok0S +xkbS4cbP2o/3fd+SkSHFhMj+ut9QrkdJ1vCBN/CH76e09AZb9H5tKHFpHCMVSxmpuwB BKH/1Zixe6VqTCzrOEHctJDUo7c8q4UOkaX9flU2YyduvBic4nxKEEqAMNQKa+ucOWya q+gjodurp6d70kNrUNtc9HL+g17UGDv5NJVh+zoyDGqmZRr6+2QxNDl+8WEHKvJEJTqo aARQ== X-Gm-Message-State: AGRZ1gI/tYVy1a03vvz6VJJ1JGN2xe483Vkfs3Scac+vbv/2CkP29k5O DfJGbOMo9xipxtossSKNkRae3/L8 X-Google-Smtp-Source: AJdET5c4oC2f7HqU6BzdjhYvVS39zq8XDR05LPbXVbCX40Z3Owupe5r8HBWAA3pSgn7Pc9g84PHnKg== X-Received: by 2002:a1f:a60f:: with SMTP id p15mr1321853vke.76.1540994707024; Wed, 31 Oct 2018 07:05:07 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.05.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:05:05 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 17/18] ARM: spectre-v1: use get_user() for __get_user() Date: Wed, 31 Oct 2018 10:04:35 -0400 Message-Id: <20181031140436.2964-18-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit b1cd0a14806321721aae45f5446ed83a3647c914 upstream. Fixing __get_user() for spectre variant 1 is not sane: we would have to add address space bounds checking in order to validate that the location should be accessed, and then zero the address if found to be invalid. Since __get_user() is supposed to avoid the bounds check, and this is exactly what get_user() does, there's no point having two different implementations that are doing the same thing. So, when the Spectre workarounds are required, make __get_user() an alias of get_user(). Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long --- arch/arm/include/asm/uaccess.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 968b50063431..ecd159b45f12 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -314,6 +314,15 @@ static inline void set_fs(mm_segment_t fs) #define user_addr_max() \ (segment_eq(get_fs(), KERNEL_DS) ? ~0UL : get_fs()) +#ifdef CONFIG_CPU_SPECTRE +/* + * When mitigating Spectre variant 1, it is not worth fixing the non- + * verifying accessors, because we need to add verification of the + * address space there. Force these to use the standard get_user() + * version instead. + */ +#define __get_user(x, ptr) get_user(x, ptr) +#else /* * The "__xxx" versions of the user access functions do not verify the * address space - it must have been done previously with a separate @@ -330,12 +339,6 @@ static inline void set_fs(mm_segment_t fs) __gu_err; \ }) -#define __get_user_error(x, ptr, err) \ -({ \ - __get_user_err((x), (ptr), err); \ - (void) 0; \ -}) - #define __get_user_err(x, ptr, err) \ do { \ unsigned long __gu_addr = (unsigned long)(ptr); \ @@ -395,6 +398,7 @@ do { \ #define __get_user_asm_word(x, addr, err) \ __get_user_asm(x, addr, err, ldr) +#endif #define __put_user(x, ptr) \ ({ \ From patchwork Wed Oct 31 14:04:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149837 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836597ljp; Wed, 31 Oct 2018 07:05:09 -0700 (PDT) X-Received: by 2002:a9f:3829:: with SMTP id p38mr1453350uad.25.1540994709788; Wed, 31 Oct 2018 07:05:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994709; cv=none; d=google.com; s=arc-20160816; b=CNmohGHXc+pF1ocaNMpzqtWJH/NfN6+VoBkNetoPXq0fti3nTLV7b7WWvD45IilGSI +7Ymb0Eg18joq5ePX2uN4TaauC1k1N+DCffGvqdHxxX7aL1aBYcCFfhSQ81Nck4RDVfL LsXDjudZjtRMHZec4ZO3dzm16Hfjvj4eSgiFyIfYBsWwf8QWYExm+nHaUKT+46jkclmy 3ihOnU0X6+ogU1j13PfFFS5orb944+o9/EhOIA840wBdwC8g07ifRF0mE0dUA/TkLYs8 G0afL75f0vjWi6TWjc3ZV7qHWmS4Syws/Llcs6B1KE8LLYyUT5Q3SJYgYg+9GECABJNA 85vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DU5sjZ6mkqAN5cgzmGt1AH+VCJ6Ym643zDXIwVYAfpI=; b=rvYN7IePP0okrHYZ3V7PaBRXDJEEMA8iJ9RYmVmU0sejp1JUu6uoZDl1EmdGAtidD0 rbKM3QGKoMWX8cVSuVWZK9hSD8wNMV/FR1sJeP0O0iHYWrY4ds8vngmQQFRAaS/NE4FV SHdeRnsufkfbvXsFSFWk98jNo2E3tpW4yLFgRdDN2ntTsE+lnEwaW6XDUvkMXfaG/ynh L8/msEq0fvwTy0i6r7mWOmV2iN6ch0EKsUobJtq2Ds8QXoupT9eBNs/5zI8mfOxGhB41 JZJhRLIEsSnv9M57AMssGV9hfAB1SpuKBI7KmfxT2jzPvuXX62f1lM115OEs1tuGgX76 XEhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SIFFliQu; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id w82-v6sor13357899vkd.25.2018.10.31.07.05.09 for (Google Transport Security); Wed, 31 Oct 2018 07:05:09 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SIFFliQu; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DU5sjZ6mkqAN5cgzmGt1AH+VCJ6Ym643zDXIwVYAfpI=; b=SIFFliQuWZC4t/9fmYOVzYBmeOh5ByuRpk9PK7xEPVWstapuL6+EBUz5qcUCC1rOgS rlonve91wAEn5ekgK63rWFZ+YER7OTxla97TsrBWW2ZWxL7R9mtP/JnRkwy8ySQlBJM1 Wi0wAadnAIYJJ/fHBi2Dj5z5n4TcyYvyNKCMM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DU5sjZ6mkqAN5cgzmGt1AH+VCJ6Ym643zDXIwVYAfpI=; b=CjERy7gumKfwWF9jtvYZ2bZo+e8v37GwE/6vAStxep7TxV1Qapn6qjxhoJGFEQo3ps 4Tq7RqQeybL+vYc5jCpy08tb/XCaWCmx+T0i+HSmTDVy86SVWi/C3uKhwGaDZrXGCQvW kCxPLf3nQMVL3CDBZG0+NRIlV3Jp7ZO+dv1YbqjKUFyVAn0ouAFRP0ik6l4+4AePNarm 88TAL6tEjQch8GzSHqUWXVLYECiK7V5EaRjLbVU1WPZ6o4YFZPKJ/AzU6gcaP1nWhvzy RfB5+CYEWy7kDtiynIXYi1u7G+fanSrSYnVOcA/Dv1NranCJRBit6GP7gshceIlObmpk 6czQ== X-Gm-Message-State: AGRZ1gJWqQle/PnO+dwY7fCYcd/F5bjqpzZ9PM6h+t9RA0DQ0Ld5OPt9 TCbtS3zcE0U2RdCiZ1SffH1AGadi X-Google-Smtp-Source: AJdET5cfROhGGmoQJE1F/fN5XUzKf7RUDlhOjdPqDPqV4yJftsN8fYAvBTZmbiMFvE0vXlgcgTnzaQ== X-Received: by 2002:a1f:490:: with SMTP id 138mr158365vke.48.1540994709099; Wed, 31 Oct 2018 07:05:09 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.05.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:05:07 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 18/18] ARM: spectre-v1: mitigate user accesses Date: Wed, 31 Oct 2018 10:04:36 -0400 Message-Id: <20181031140436.2964-19-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit a3c0f84765bb429ba0fd23de1c57b5e1591c9389 upstream. Spectre variant 1 attacks are about this sequence of pseudo-code: index = load(user-manipulated pointer); access(base + index * stride); In order for the cache side-channel to work, the access() must me made to memory which userspace can detect whether cache lines have been loaded. On 32-bit ARM, this must be either user accessible memory, or a kernel mapping of that same user accessible memory. The problem occurs when the load() speculatively loads privileged data, and the subsequent access() is made to user accessible memory. Any load() which makes use of a user-maniplated pointer is a potential problem if the data it has loaded is used in a subsequent access. This also applies for the access() if the data loaded by that access is used by a subsequent access. Harden the get_user() accessors against Spectre attacks by forcing out of bounds addresses to a NULL pointer. This prevents get_user() being used as the load() step above. As a side effect, put_user() will also be affected even though it isn't implicated. Also harden copy_from_user() by redoing the bounds check within the arm_copy_from_user() code, and NULLing the pointer if out of bounds. Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long --- arch/arm/include/asm/assembler.h | 4 ++++ arch/arm/lib/copy_from_user.S | 9 +++++++++ 2 files changed, 13 insertions(+) -- 2.17.1 diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 307901f88a1e..483481c6937e 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -454,6 +454,10 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) adds \tmp, \addr, #\size - 1 sbcccs \tmp, \tmp, \limit bcs \bad +#ifdef CONFIG_CPU_SPECTRE + movcs \addr, #0 + csdb +#endif #endif .endm diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S index 1512bebfbf1b..d36329cefedc 100644 --- a/arch/arm/lib/copy_from_user.S +++ b/arch/arm/lib/copy_from_user.S @@ -90,6 +90,15 @@ .text ENTRY(arm_copy_from_user) +#ifdef CONFIG_CPU_SPECTRE + get_thread_info r3 + ldr r3, [r3, #TI_ADDR_LIMIT] + adds ip, r1, r2 @ ip=addr+size + sub r3, r3, #1 @ addr_limit - 1 + cmpcc ip, r3 @ if (addr+size > addr_limit - 1) + movcs r1, #0 @ addr = NULL + csdb +#endif #include "copy_template.S"