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[202.81.18.30]) by smtp.gmail.com with ESMTPSA id c23sm16290636pfh.131.2017.05.25.20.32.31 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 25 May 2017 20:32:36 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 26 May 2017 13:32:27 +1000 From: Joel Stanley To: Philipp Zabel , Rob Herring , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Andrew Jeffery Subject: [PATCH 1/2] dt-bindings: reset: Add bindings for basic reset controller Date: Fri, 26 May 2017 13:32:13 +1000 Message-Id: <20170526033214.8081-2-joel@jms.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170526033214.8081-1-joel@jms.id.au> References: <20170526033214.8081-1-joel@jms.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the bindings documentation for a basic single-register reset controller. The bindings describe a single 32-bit register that contains up to 32 reset lines, each deasserted by clearing the appropriate bit in the register. Signed-off-by: Joel Stanley --- .../devicetree/bindings/reset/reset-basic.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/reset-basic.txt -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/reset/reset-basic.txt b/Documentation/devicetree/bindings/reset/reset-basic.txt new file mode 100644 index 000000000000..7341e04e7904 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/reset-basic.txt @@ -0,0 +1,31 @@ +Basic single-register reset controller +====================================== + +This describes a generic reset controller where the reset lines are controlled +by single bits within a 32-bit memory location. The memory location is assumed +to be part of a syscon regmap. + +Reset controller required properties: + - compatible: should be "reset-basic" + - #reset-cells: must be set to 1 + - reg: reset register location within regmap + +Device node required properties: + - resets phandle + - bit number, counting from zero, for the desired reset line. Max is 31. + +Example: + +syscon { + compatible = "syscon"; + + uart_rest: rest@0c { + compatible = "reset-basic"; + #reset-cells = <1>; + reg = <0x0c>; + }; +} + +&uart { + resets = <&uart_rest 0x04>; +} From patchwork Fri May 26 03:32:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 100545 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp66247qge; Thu, 25 May 2017 20:33:30 -0700 (PDT) X-Received: by 10.98.69.193 with SMTP id n62mr49530910pfi.216.1495769610258; Thu, 25 May 2017 20:33:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495769610; cv=none; d=google.com; s=arc-20160816; b=0ay8auAjfuzLxae/47kUEvy0fjFWvwnyRVgcTrx33ePIpHycjjNQ/C1Dzxh/LPafo7 y0jcIV0qUcgJ8YAP7cD8fZd78yPTtuTUW0cRtR7h6YrZNQr8j7IexJxqQ11XiOvOoXiM Xc2smbvGH1pNuTp3R2v87h5fdt5+6ihEBBbzi/uuYbeTvIs2NG1S60v8crbqmTNQA1VJ Q5v5JWP03HsNX/1ylTOwglPhOsatRzOr/wW+t1SJgY2SV6gCPXEi340AXQ72qXymEIwe t3o+jeLzpFvX9ZwAM44hsoKLlfslh51am+pdriHqVRchW+Mc7qaeOJBCGykvNE290Bb5 wC8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=GdR8ek4B563s4kZubpLcOqf9Fc5753TXS65iY++0bhg=; b=NiP+nJOL4fdmktX3MW8v0K9xQ6kvw3X1buQr09C5d24Jylc0hjB01bRwetRj6FnWrq m3jH5+whw2BfTAPKVpsT2DnZdLN2JdM9eVOtkCwReJ8kLxQdrzD4+/Onfv6lw3kRyyaW quFGlLSkM8+YRa/cCEndkFX2ScDdX++gHxCIbzdMeGWDcnYNVbkWP0eA+v2rbiJ/K27d NLdFlv42B8kHpPT9AJuQ/Us/xv0qVqwShM93/ZNZolvMyqnjyBMYSiV6ECkWluiAoxCs T+1wFRDwy/StiFrnaNA9v7/rUlpa0Y0b7DCNZGZ93TP53ueZldUeFWqon11YcVQl/OtD 0Xhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[202.81.18.30]) by smtp.gmail.com with ESMTPSA id t17sm14202592pfj.61.2017.05.25.20.32.42 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 25 May 2017 20:32:47 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 26 May 2017 13:32:37 +1000 From: Joel Stanley To: Philipp Zabel , Rob Herring , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Andrew Jeffery Subject: [PATCH 2/2] reset: Add basic single-register reset driver Date: Fri, 26 May 2017 13:32:14 +1000 Message-Id: <20170526033214.8081-3-joel@jms.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170526033214.8081-1-joel@jms.id.au> References: <20170526033214.8081-1-joel@jms.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This driver is a basic single-register reset controller driver that supports clearing a single bit in a register. Signed-off-by: Joel Stanley --- drivers/reset/Kconfig | 6 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-basic.c | 109 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 116 insertions(+) create mode 100644 drivers/reset/reset-basic.c -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d21c07ccc94e..980cda887dfe 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -28,6 +28,12 @@ config RESET_ATH79 This enables the ATH79 reset controller driver that supports the AR71xx SoC reset controller. +config RESET_BASIC + bool "Basic Reset Driver" + help + This enables a basic single-register reset controller driver that + supports clearing a single bit in a register. + config RESET_BERLIN bool "Berlin Reset Driver" if COMPILE_TEST default ARCH_BERLIN diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 02a74db94339..e8e8869e098d 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o obj-$(CONFIG_RESET_ATH79) += reset-ath79.o +obj-$(CONFIG_RESET_BASIC) += reset-basic.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o diff --git a/drivers/reset/reset-basic.c b/drivers/reset/reset-basic.c new file mode 100644 index 000000000000..62a676de9f62 --- /dev/null +++ b/drivers/reset/reset-basic.c @@ -0,0 +1,109 @@ +/* + * Copyright 2017 IBM Corperation + * + * Joel Stanley + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define to_basic_reset_priv(p) \ + container_of((p), struct basic_reset_priv, rcdev) + +struct basic_reset_priv { + struct regmap *regmap; + struct reset_controller_dev rcdev; + u32 reg; +}; + +static int basic_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct basic_reset_priv *priv = to_basic_reset_priv(rcdev); + u32 mask = BIT(id); + + regmap_update_bits(priv->regmap, priv->reg, mask, mask); + + return 0; +} + +static int basic_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct basic_reset_priv *priv = to_basic_reset_priv(rcdev); + u32 mask = BIT(id); + + regmap_update_bits(priv->regmap, priv->reg, mask, 0); + + return 0; +} + +static int basic_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct basic_reset_priv *priv = to_basic_reset_priv(rcdev); + u32 mask = BIT(id); + u32 val; + + regmap_read(priv->regmap, priv->reg, &val); + + return !!(val & mask); +} + +static const struct reset_control_ops basic_reset_ops = { + .assert = basic_reset_assert, + .deassert = basic_reset_deassert, + .status = basic_reset_status, +}; + +static int basic_reset_probe(struct platform_device *pdev) +{ + struct device_node *parent_np = of_get_parent(pdev->dev.of_node); + struct basic_reset_priv *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap = syscon_node_to_regmap(parent_np); + of_node_put(parent_np); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + ret = of_property_read_u32(pdev->dev.of_node, "reg", &priv->reg); + if (ret) + return ret; + + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.ops = &basic_reset_ops; + priv->rcdev.of_node = pdev->dev.of_node; + priv->rcdev.nr_resets = 32; + + return reset_controller_register(&priv->rcdev); +} + +static const struct of_device_id basic_reset_dt_match[] = { + { .compatible = "reset-basic" }, + { }, +}; + +static struct platform_driver basic_reset_driver = { + .probe = basic_reset_probe, + .driver = { + .name = "basic-reset", + .of_match_table = basic_reset_dt_match, + }, +}; +builtin_platform_driver(basic_reset_driver);