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The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 13 +++++++++++++ target/alpha/cpu.h | 6 ------ target/arm/cpu.h | 7 ------- target/avr/cpu.h | 2 -- target/cris/cpu.h | 8 -------- target/hexagon/cpu.h | 3 --- target/hppa/cpu.h | 3 --- target/i386/cpu.h | 7 ------- target/m68k/cpu.h | 8 -------- target/microblaze/cpu.h | 7 ------- target/mips/cpu.h | 3 --- target/mips/internal.h | 2 -- target/nios2/cpu.h | 2 -- target/openrisc/cpu.h | 2 -- target/ppc/cpu.h | 7 ------- target/riscv/cpu.h | 2 -- target/rx/cpu.h | 4 ---- target/s390x/cpu.h | 7 ------- target/sh4/cpu.h | 3 --- target/sparc/cpu.h | 2 -- target/tricore/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- 22 files changed, 13 insertions(+), 89 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5d1b6d80fb..9d5987ba04 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -662,6 +662,19 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, } return addr; } + +/** + * cpu_signal_handler + * @signum: host signal number + * @pinfo: host siginfo_t + * @puc: host ucontext_t + * + * To be called from the SIGBUS and SIGSEGV signal handler to inform the + * virtual cpu of exceptions. Returns true if the signal was handled by + * the virtual CPU. + */ +int cpu_signal_handler(int signum, void *pinfo, void *puc); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 4e993bd15b..ce9ec32199 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -287,7 +287,6 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, int mmu_idx, uintptr_t retaddr); #define cpu_list alpha_cpu_list -#define cpu_signal_handler cpu_alpha_signal_handler typedef CPUAlphaState CPUArchState; typedef AlphaCPU ArchCPU; @@ -440,11 +439,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU void alpha_cpu_list(void); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_alpha_signal_handler(int host_signum, void *pinfo, - void *puc); bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 09d9027734..751141915d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1121,12 +1121,6 @@ static inline bool is_a64(CPUARMState *env) return env->aarch64; } -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_arm_signal_handler(int host_signum, void *pinfo, - void *puc); - /** * pmu_op_start/finish * @env: CPUARMState @@ -3015,7 +3009,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU -#define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list /* ARM has the following "translation regimes" (as the ARM ARM calls them): diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 93e3faa0a9..dceacf3cd7 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -175,7 +175,6 @@ static inline void set_avr_feature(CPUAVRState *env, int feature) } #define cpu_list avr_cpu_list -#define cpu_signal_handler cpu_avr_signal_handler #define cpu_mmu_index avr_cpu_mmu_index static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) @@ -187,7 +186,6 @@ void avr_cpu_tcg_init(void); void avr_cpu_list(void); int cpu_avr_exec(CPUState *cpu); -int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc); int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, int len, bool is_write); diff --git a/target/cris/cpu.h b/target/cris/cpu.h index be021899ae..6603565f83 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -199,12 +199,6 @@ int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_cris_signal_handler(int host_signum, void *pinfo, - void *puc); - void cris_initialize_tcg(void); void cris_initialize_crisv10_tcg(void); @@ -250,8 +244,6 @@ enum { #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU -#define cpu_signal_handler cpu_cris_signal_handler - /* MMU modes definitions */ #define MMU_USER_IDX 1 static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 2855dd3881..f7d043865b 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -129,9 +129,6 @@ typedef struct HexagonCPU { #include "cpu_bits.h" -#define cpu_signal_handler cpu_hexagon_signal_handler -int cpu_hexagon_signal_handler(int host_signum, void *pinfo, void *puc); - static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7854675b90..d3cb7a279f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -319,9 +319,6 @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } void cpu_hppa_change_prot_id(CPUHPPAState *env); #endif -#define cpu_signal_handler cpu_hppa_signal_handler - -int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7dd664791a..c2954c71ea 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1947,12 +1947,6 @@ void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_x86_signal_handler(int host_signum, void *pinfo, - void *puc); - /* cpu.c */ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, uint32_t vendor2, uint32_t vendor3); @@ -2020,7 +2014,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") #endif -#define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list /* MMU modes definitions */ diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 550eb028b6..a3423729ef 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -177,13 +177,6 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void m68k_tcg_init(void); void m68k_cpu_init_gdb(M68kCPU *cpu); -/* - * you can call this signal handler from your SIGBUS and SIGSEGV - * signal handlers to inform the virtual CPU of exceptions. non zero - * is returned if the signal was handled by the virtual CPU. - */ -int cpu_m68k_signal_handler(int host_signum, void *pinfo, - void *puc); uint32_t cpu_m68k_get_ccr(CPUM68KState *env); void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); @@ -563,7 +556,6 @@ enum { #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU -#define cpu_signal_handler cpu_m68k_signal_handler #define cpu_list m68k_cpu_list /* MMU modes definitions */ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 40401c33b7..13ed3cd4dd 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -385,16 +385,9 @@ static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val) } void mb_tcg_init(void); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_mb_signal_handler(int host_signum, void *pinfo, - void *puc); #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU -#define cpu_signal_handler cpu_mb_signal_handler - /* MMU modes definitions */ #define MMU_NOMMU_IDX 0 #define MMU_KERNEL_IDX 1 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1dfe69c6c0..56b1cbd091 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1193,7 +1193,6 @@ struct MIPSCPU { void mips_cpu_list(void); -#define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); @@ -1277,8 +1276,6 @@ enum { */ #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 -int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); - #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU diff --git a/target/mips/internal.h b/target/mips/internal.h index eecdd10116..daddb05fd4 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -156,8 +156,6 @@ extern const VMStateDescription vmstate_mips_cpu; #endif /* !CONFIG_USER_ONLY */ -#define cpu_signal_handler cpu_mips_signal_handler - static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2ab82fdc71..88a511209c 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -193,7 +193,6 @@ struct Nios2CPU { void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); -int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); @@ -206,7 +205,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU #define cpu_gen_code cpu_nios2_gen_code -#define cpu_signal_handler cpu_nios2_signal_handler #define CPU_SAVE_VERSION 1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index be6df81a81..187a4a114e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -320,11 +320,9 @@ void openrisc_translate_init(void); bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); int print_insn_or1k(bfd_vma addr, disassemble_info *info); #define cpu_list cpu_openrisc_list -#define cpu_signal_handler cpu_openrisc_signal_handler #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_openrisc_cpu; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 362e7c4c5c..01d3773bc7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1278,12 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu; /*****************************************************************************/ void ppc_translate_init(void); -/* - * you can call this signal handler from your SIGBUS and SIGSEGV - * signal handlers to inform the virtual CPU of exceptions. non zero - * is returned if the signal was handled by the virtual CPU. - */ -int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc); bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -1371,7 +1365,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU -#define cpu_signal_handler cpu_ppc_signal_handler #define cpu_list ppc_cpu_list /* MMU modes definitions */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e735e53e26..465142616a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -356,7 +356,6 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); -#define cpu_signal_handler riscv_cpu_signal_handler #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index @@ -372,7 +371,6 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); void riscv_translate_init(void); -int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index faa3606f52..4ac71aec37 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -134,13 +134,9 @@ int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void rx_translate_init(void); -int cpu_rx_signal_handler(int host_signum, void *pinfo, - void *puc); - void rx_cpu_list(void); void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); -#define cpu_signal_handler cpu_rx_signal_handler #define cpu_list rx_cpu_list #include "exec/cpu-all.h" diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index b26ae8fff2..3153d053e9 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -809,13 +809,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_S390_CPU -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); -#define cpu_signal_handler cpu_s390x_signal_handler - - /* interrupt.c */ #define RA_IGNORED 0 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 017a770214..56f7c32df9 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -213,8 +213,6 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, int mmu_idx, uintptr_t retaddr); void sh4_translate_init(void); -int cpu_sh4_signal_handler(int host_signum, void *pinfo, - void *puc); bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -250,7 +248,6 @@ void cpu_load_tlb(CPUSH4State * env); #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU -#define cpu_signal_handler cpu_sh4_signal_handler #define cpu_list sh4_cpu_list /* MMU modes definitions */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 1f40d768d8..5a7f1ed5d6 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -648,13 +648,11 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, int mmu_idx); #endif #endif -int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU -#define cpu_signal_handler cpu_sparc_signal_handler #define cpu_list sparc_cpu_list /* MMU modes definitions */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 4b61a2c03f..c461387e71 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -362,7 +362,6 @@ void fpu_set_state(CPUTriCoreState *env); void tricore_cpu_list(void); -#define cpu_signal_handler cpu_tricore_signal_handler #define cpu_list tricore_cpu_list static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) @@ -377,7 +376,6 @@ typedef TriCoreCPU ArchCPU; void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); -int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index cbb720e7cc..646965f379 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -584,7 +584,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -#define cpu_signal_handler cpu_xtensa_signal_handler #define cpu_list xtensa_cpu_list #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU @@ -613,7 +612,6 @@ void check_interrupts(CPUXtensaState *s); void xtensa_irq_init(CPUXtensaState *env); qemu_irq *xtensa_get_extints(CPUXtensaState *env); qemu_irq xtensa_get_runstall(CPUXtensaState *env); -int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); void xtensa_cpu_list(void); void xtensa_sync_window_from_phys(CPUXtensaState *env); void xtensa_sync_phys_from_window(CPUXtensaState *env); From patchwork Tue Sep 21 02:25:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514381 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp2638657jao; Mon, 20 Sep 2021 19:27:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw6fCSx7NZzV+uBtVOGhOVnPEGfuT4iDuMLkD//cmh63rUu1J2n3W+qLCXGvJQEw4d/Ub/J X-Received: by 2002:a05:6638:2493:: with SMTP id x19mr22004480jat.57.1632191226971; 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If we don't ensure we go back * to sleep in the halted state we won't cleanly * start-up when the vCPU is enabled. * * cpu->halted should ensure we sleep in wait_io_event */ g_assert(cpu->halted); break; qemu_wait_io_event() is sysemu-specific, so we can restrict the cpu_handle_halt() call in cpu_exec() to system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-2-f4bug@amsat.org> Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 75dbc1e4e3..5fd1ed3422 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -588,8 +588,9 @@ static inline void tb_add_jump(TranslationBlock *tb, int n, static inline bool cpu_handle_halt(CPUState *cpu) { +#ifndef CONFIG_USER_ONLY if (cpu->halted) { -#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) +#if defined(TARGET_I386) if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { X86CPU *x86_cpu = X86_CPU(cpu); qemu_mutex_lock_iothread(); @@ -597,13 +598,14 @@ static inline bool cpu_handle_halt(CPUState *cpu) cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); qemu_mutex_unlock_iothread(); } -#endif +#endif /* TARGET_I386 */ if (!cpu_has_work(cpu)) { return true; } cpu->halted = 0; } +#endif /* !CONFIG_USER_ONLY */ return false; } From patchwork Tue Sep 21 02:25:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514383 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp2638664jao; Mon, 20 Sep 2021 19:27:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzfKzNUAkT9YbyMxcLlQ9MGgUkYze2/0SLpNq2H6cCJXFyFf1fvFjZlU54l2FYTB2dq8HcV X-Received: by 2002:a02:11c1:: with SMTP id 184mr21982641jaf.70.1632191228078; Mon, 20 Sep 2021 19:27:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632191228; cv=none; d=google.com; s=arc-20160816; b=Df93JxkEeqGjhWqIzzsJHQIZoW61arMoHvGgktUGRi9rPqMrf6cd8aW0vobXokk7Zb xC8yt/agTD9WrLBtUG8TJ15dROXGxAdB48rIIL5GZiUqH/aH+z+s0ER9PL+Lljp5Wk5b T+HMXUjyEuTd7tSQLa3CBhtMNTNjLsFKS+iFION+xgymNHlyMmViOv8AQiLOTj3CZMof D3qyWUepakSYiw6E8Unc7J9LEq5ZGUzQCdaJnEnvAseessyyzDzStSEpTrBIq7RgHauA SCX1ZaLJRZQJ695YutNYA+9UFOx72i3aeIa/YFAFroQpiT7ljK7SbCTRExOy/CNNBRJY jxhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5xOsJ/q61bGEcfr8bVryci8I2a76P5P5Z/hHe2uiGQU=; b=iXUd/dz4W7VpBJ4++p4RX8iID/tpOGVzxhl7EeTyxyWv9JiIn6fCYRi6bJITn0hOol xwDeFMdMLVZ9qaMxP9zpWC3aeQaMpGDLKmqAAIpHmZQhXSyNsgjTZ8eSA3dslt2ncWBS eSEaMf/FA4zwIb4qozIaV74wh627uLDQpD8nv9znc47Ke9XTSlmyn0C6792Hg1d44OZV ILnmwpijIBuQY7RsV2jc9qahPFeMlfC73DW/t70KPnNKpTm6E4KB+7yKBzFoW/zTtPfb A+ntfLV5Jce6zE2iCSJgZrIIXwnTxSvdVMZndozlFpdlq8uFialOPf0izbcMg/TBS/xT azNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="p/AG+c7e"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f22si15860451jam.69.2021.09.20.19.27.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 20 Sep 2021 19:27:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="p/AG+c7e"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSVUw-0005ZH-II for patch@linaro.org; Mon, 20 Sep 2021 22:27:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSVTa-0005X4-9Q for qemu-devel@nongnu.org; Mon, 20 Sep 2021 22:25:42 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:55860) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSVTY-0006FF-5s for qemu-devel@nongnu.org; Mon, 20 Sep 2021 22:25:42 -0400 Received: by mail-pj1-x102f.google.com with SMTP id t20so13341406pju.5 for ; Mon, 20 Sep 2021 19:25:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5xOsJ/q61bGEcfr8bVryci8I2a76P5P5Z/hHe2uiGQU=; b=p/AG+c7eXuezBYP8hx8i5eozEiymVa34qCIcfSRcV/m59Vg1PIYej37Sshdeu0Wdy/ JflZMbe7a56KlPEymTxLY4OJDttZCUKOzafkQcRSwLE/MRGFLfmEEJ3gS94j8zJmg/tQ O3hLLnmvFq23YR0pbcvpanx9fhKfSUrXjBg2N90NZvUSylcmsF5Ay8N/5ZSVfEtkbYce PDuyP9+QjSjcANHL2cEHVnfmVumk/69tZjb/qO626oFFn56ai6p+LjgoNo31N7VKZa68 o3kyrQYq8iauEZzXVULWbCdW4r/rwNGwn/9ENdPQUQa75Do7P4QSFp6MCFDEne2epoMZ 0spw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5xOsJ/q61bGEcfr8bVryci8I2a76P5P5Z/hHe2uiGQU=; b=NQoQjzXpxmnEPDHi6F0Jiy+R5V8WFWMWzBGU9F3CvQUG9kEIpkIsHH1BftT58fwDtb wjJvus6rnuDfGY+fKdr5uChatKSSr8M8KSAZXGWWnUdoqa7lrqOkv+SwdeXKrTwz/jC4 SOieppsCnPiKZ9LoF+A2BKQ2WBXd3twadN20DDTC2p/6e56Z3KlQP5E3mippHhpG7Qa/ 5SPx7r2IR/WhR7cvW9As93O537UFVtphg+ITJkqUxW/+01GzX8oBejsxDiG/VYVN5gGa FdtbRpcPUkhl7+khixtJrJ6Cu4uoD4GS9hbCPeF3Ns7x/vO58iE5DkLw3Eo+/QzwciCS So3w== X-Gm-Message-State: AOAM533CyEFaSJ2FUZCIq76EJydkrwCM4bJTk4FRc9bmR7GkI69L45uT yflUL9Umcf33xk4AN9V0RKcZk9FfFGNASA== X-Received: by 2002:a17:90a:1904:: with SMTP id 4mr2372037pjg.191.1632191138528; Mon, 20 Sep 2021 19:25:38 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id n9sm15297621pff.37.2021.09.20.19.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 19:25:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/10] tcg/mips: Drop inline markers Date: Mon, 20 Sep 2021 19:25:27 -0700 Message-Id: <20210921022534.365291-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org> References: <20210921022534.365291-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Let the compiler decide about inlining. Remove tcg_out_ext8s and tcg_out_ext16s as unused. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 76 ++++++++++++++------------------------- 1 file changed, 27 insertions(+), 49 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index bf0eb84e2d..320795a637 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -187,7 +187,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, #endif -static inline bool is_p2m1(tcg_target_long val) +static bool is_p2m1(tcg_target_long val) { return val && ((val + 1) & val) == 0; } @@ -361,8 +361,8 @@ typedef enum { /* * Type reg */ -static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, - TCGReg rd, TCGReg rs, TCGReg rt) +static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, + TCGReg rd, TCGReg rs, TCGReg rt) { int32_t inst; @@ -376,8 +376,8 @@ static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, /* * Type immediate */ -static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, - TCGReg rt, TCGReg rs, TCGArg imm) +static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, + TCGReg rt, TCGReg rs, TCGArg imm) { int32_t inst; @@ -391,8 +391,8 @@ static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, /* * Type bitfield */ -static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, - TCGReg rs, int msb, int lsb) +static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, + TCGReg rs, int msb, int lsb) { int32_t inst; @@ -404,8 +404,8 @@ static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, tcg_out32(s, inst); } -static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, - MIPSInsn oph, TCGReg rt, TCGReg rs, +static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, + MIPSInsn oph, TCGReg rt, TCGReg rs, int msb, int lsb) { if (lsb >= 32) { @@ -422,8 +422,7 @@ static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, /* * Type branch */ -static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, - TCGReg rt, TCGReg rs) +static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) { tcg_out_opc_imm(s, opc, rt, rs, 0); } @@ -431,8 +430,8 @@ static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, /* * Type sa */ -static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, - TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, + TCGReg rd, TCGReg rt, TCGArg sa) { int32_t inst; @@ -479,28 +478,27 @@ static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) return true; } -static inline void tcg_out_nop(TCGContext *s) +static void tcg_out_nop(TCGContext *s) { tcg_out32(s, 0); } -static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); } -static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); } -static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); } -static inline bool tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (ret != arg) { @@ -612,27 +610,7 @@ static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) } } -static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); - } else { - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); - } -} - -static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); - } else { - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); - } -} - -static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); @@ -656,8 +634,8 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, tcg_out_opc_imm(s, opc, data, addr, lo); } -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { MIPSInsn opc = OPC_LD; if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { @@ -666,8 +644,8 @@ static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, tcg_out_ldst(s, opc, arg, arg1, arg2); } -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { MIPSInsn opc = OPC_SD; if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { @@ -676,8 +654,8 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, tcg_out_ldst(s, opc, arg, arg1, arg2); } -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) { if (val == 0) { tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); @@ -1637,9 +1615,9 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, } } -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { MIPSInsn i1, i2; TCGArg a0, a1, a2; From patchwork Tue Sep 21 02:25:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514385 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp2639732jao; Mon, 20 Sep 2021 19:29:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy0OiMxhlT8R1T8gN9yTVLW9FR/hztNZLak+xwatQH+4zlLVvnxzBmOHbuo7ecLqBpmxxk+ X-Received: by 2002:a25:868f:: with SMTP id z15mr35426195ybk.338.1632191354773; Mon, 20 Sep 2021 19:29:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632191354; 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[209.51.188.17]) by mx.google.com with ESMTPS id s145si17775148ybc.531.2021.09.20.19.29.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 20 Sep 2021 19:29:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w8O98B47; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSVX0-0002e5-82 for patch@linaro.org; Mon, 20 Sep 2021 22:29:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSVTa-0005X2-7I for qemu-devel@nongnu.org; Mon, 20 Sep 2021 22:25:42 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:42905) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSVTY-0006Fq-Dj for qemu-devel@nongnu.org; Mon, 20 Sep 2021 22:25:41 -0400 Received: by mail-pj1-x1030.google.com with SMTP id p12-20020a17090adf8c00b0019c959bc795so1422505pjv.1 for ; Mon, 20 Sep 2021 19:25:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M5odl7lhVWYI7jQ2rZz9eXg1u6cFbGrkar9AkgXAJoU=; b=w8O98B47eQENsPbH5ljBc2gmCujldqAOdOuocESNcQXqOXu3Pu65laxfHkfTgkglGs pcqLuRmzHNxq8Y/Gp3STekFod37bSPTivEc5KXphCFZbuEAGr/+G896pDoEKpr6nW7wK oAiJw9gYtIR9TUo4+zGR+GUUZL/qeHKNx6v8OsiaVkDmfaR39z8fKqs9u+4q9k9dFVEh AYgWI6MbVh4pRDPUx2L94kTbfabc2OR7Y9cBk07DftjD+yD043GB5JRpIXVBoit0brUG 7WPOmVv8cMfjOFSvP/w1EFs/yTRGhc2R6baDnunxbqGNorFX99pZEX67aR8uVQdaDZx+ Qh0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M5odl7lhVWYI7jQ2rZz9eXg1u6cFbGrkar9AkgXAJoU=; b=tAiTuzg12MsgQ84tqtZciHsuv/idKg0ICBFz8xBIMklz6MttpB4Qx16OfYJWpYV96X kOHJbzAXnEuhMD5BrRrK9Z+Uz4nd56c9G7OHGWJW6HEOJVnYi5kMvADZBzk/a6zxu3Gv LmeVIbJA+SUcUaozFguyya8y4UlunJrZnBjOMSt7gdim4KcSNiIokBH9kmpWXbVDGE/T kOuRMk7OhhmGxc4+3lY7KhpmjQjVdStOrnp12IYMYrKkWef0Nx35m3nWk0LmWy3/k0kK I5/1ybRIYFzbK+z180I81m6vtKCS3MQXc8ROTsqZLJCyKtiYL7fyUNBB3DuTGEJQSRWE Ptig== X-Gm-Message-State: AOAM532BvErUJ2lSiNQ0nJYJPYCFLZ71YMveO+tx0DjoXeddS/TIEcjU BG3lxnkEepof7IyQ8n2uHGq4LrubUXPxAQ== X-Received: by 2002:a17:90a:311:: with SMTP id 17mr2431398pje.121.1632191139162; Mon, 20 Sep 2021 19:25:39 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id n9sm15297621pff.37.2021.09.20.19.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 19:25:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/10] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr Date: Mon, 20 Sep 2021 19:25:28 -0700 Message-Id: <20210921022534.365291-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org> References: <20210921022534.365291-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Weaning off of unique alignment requirements, so allow JAL to not reach the target. TCG_TMP1 is always available for use as a scratch because it is clobbered by the subroutine being called. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 320795a637..3a40af8799 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -573,8 +573,10 @@ static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) { - bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); - tcg_debug_assert(ok); + if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); + tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); + } } static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) From patchwork Tue Sep 21 02:25:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514389 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp2641417jao; Mon, 20 Sep 2021 19:32:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxfTrb/Q+aAgnSeQdyKXMZUZc7Ria0A50GLvzOiK0+Y2gNC8nVr3itijP6FoidZtxDJhR2r X-Received: by 2002:a05:6e02:2148:: with SMTP id d8mr19485038ilv.305.1632191525315; Mon, 20 Sep 2021 19:32:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632191525; cv=none; d=google.com; s=arc-20160816; b=Zh/MgVeuOqVzVT2A7jjLP3WSRdUj3MbdjeAWqhfgRze4so/UrQwe7EXgrPuLY06fyG 4x88wQV9ARHvzBd/xdfLUB53vZ8bZCbjheTeDwfYdoF89R6EjWr08yaofLTnVPL9eT2S O3mMyoFDPTamQh/8BT/GGFG+f3SUnoQuunuxEWJmw2KAXTVvFTEwL7Anw85iUPiIGyJc WUl3L2hCakRRDLfFX/vyz6HUvMK8FFcZRbsjAJ/jV2ad0WTCdJxcsAtlbnWfE5ikZlPQ x4EIYEwIaDMrM+M32/IJzL2EN+swyuxk26+g3EQQHhD6KdRwduxQUYBIsSbANzvAk9wY gOrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sx9OxIFdY4NzqELX94oh/fd9umRX24uKGyg1w/4NOWY=; b=Zud13x92dPS3trfuNAG+2nRhgg44FcoxIDO0ofbS53Top3bk0WiBhHDUmxohZyv/Rw PHdzS0AKp+GEyC0HFDu1zfWn83DgUwEL2RQ8hmGcG6ci7NU5FKNEkXOWr+nZcU9Ajzue Y+9rPe3kOdTOg3yNx2zb+JDfT3zG1prU/FOij864nguc5iI8tQoihBfsmnzWcyVOz/9p 0H3uYYUowkQueRYN8VJ6EdTfYMlh7wiLdsd/2HgiTsoB6YkhIJfdqvIWCHB5kl0O1s06 ThGeU+w8X0tAgguJxTO/OGXYQJpr9d4JB2RDCdiCM1eCImW5ZGV2kgZ68MEKz16FD2ci 8c2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="W4ia7N9/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v189si14541113iof.75.2021.09.20.19.32.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 20 Sep 2021 19:32:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="W4ia7N9/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSVZk-0000O0-PJ for patch@linaro.org; Mon, 20 Sep 2021 22:32:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43314) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSVTe-0005cZ-1r for qemu-devel@nongnu.org; Mon, 20 Sep 2021 22:25:46 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:46713) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSVTZ-0006G2-7i for qemu-devel@nongnu.org; Mon, 20 Sep 2021 22:25:44 -0400 Received: by mail-pl1-x62d.google.com with SMTP id w11so2822851plz.13 for ; Mon, 20 Sep 2021 19:25:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sx9OxIFdY4NzqELX94oh/fd9umRX24uKGyg1w/4NOWY=; b=W4ia7N9/nMd8n4QGsBSHGjXueGIRm0W5pnzrPSfMO/yHUj0POKixXtJXZbR4cbjcWQ /+9loy7Zyvy5Gj5lsNHNbyM8OiAaiYa3Tu5ji1TGKZ0UcaWXhRsbycJUsTLjK4YmUjZW 9UngvPYih68cEBVxwZQi7uOwmVGvIkLe8qhz3utew7HjJAt+mmSlffzhOVBUu/bb/sid IxYfdg2ucXwDfMzUetgOx+swEZ7NsiSZFpOxqEYy5EryPKV1CB+6axXSvBHxvkeH4Gnn /LrXRGfY1jGTYFbEKxz85jqxGYSo+otQOYO99jWZfektYj2b1SupCGTzmHhfjSHGezLa eZ4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sx9OxIFdY4NzqELX94oh/fd9umRX24uKGyg1w/4NOWY=; b=6UgaqSr8Lh19NLC+WlCdHJc1nlgO9iaUTkQkDLjxMGHjfwf7gEmXY5VaSJbPG3kQcT cWKQ2rvAoqBeMAlrOFVo31c2jvVnysJSyw8IO0xXoIFfjGF+Ha52pblnJ6DvPwRCGryt KqN68IVM+QSU6uwtYNFntzRZJ7l49U+xNA0/x3wERbI63aQoVPRVsuOasNHdcXsVQCQz F/aeVoEWRYEmH6Paek59r5PAnSChoAPgmuIvV+fsikjxKlMs2gtk5GNJzUipQ6+GJMNb X0OO4N00DfNAejNbn6V8wMPhp3faT11g5KDR4tmNPnw8CP8VGDE/9eCMgFKFFzDg7bGJ IKcQ== X-Gm-Message-State: AOAM530nWkBZ3atMzkYeuuZKx7DyYOquemoMdx6OOatHlD0AgQCc9sb9 BDYY+rXDz7I8IAYc06GI/4bHyRI9U0CuCA== X-Received: by 2002:a17:90a:e547:: with SMTP id ei7mr2500575pjb.177.1632191139951; Mon, 20 Sep 2021 19:25:39 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id n9sm15297621pff.37.2021.09.20.19.25.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 19:25:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/10] tcg/mips: Unset TCG_TARGET_HAS_direct_jump Date: Mon, 20 Sep 2021 19:25:29 -0700 Message-Id: <20210921022534.365291-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org> References: <20210921022534.365291-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Only use indirect jumps. Finish weaning away from the unique alignment requirements for code_gen_buffer. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 12 +++++------- tcg/mips/tcg-target.c.inc | 23 +++++------------------ 2 files changed, 10 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 3a62055f04..c366fdf74b 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -39,11 +39,7 @@ #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define TCG_TARGET_NB_REGS 32 -/* - * We have a 256MB branch region, but leave room to make sure the - * main executable is also within that region. - */ -#define MAX_CODE_GEN_BUFFER_SIZE (128 * MiB) +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) typedef enum { TCG_REG_ZERO = 0, @@ -136,7 +132,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump 0 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_add2_i32 0 @@ -207,7 +203,9 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t) + QEMU_ERROR("code path is reachable"); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 3a40af8799..41ffa28394 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1654,17 +1654,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* direct jump method */ - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); - /* Avoid clobbering the address during retranslation. */ - tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); - } else { - /* indirect jump method */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, - (uintptr_t)(s->tb_jmp_target_addr + a0)); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); - } + /* indirect jump method */ + tcg_debug_assert(s->tb_jmp_insn_offset == 0); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, + (uintptr_t)(s->tb_jmp_target_addr + a0)); + tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); tcg_out_nop(s); set_jmp_reset_offset(s, a0); break; @@ -2538,13 +2532,6 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ } -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, - uintptr_t jmp_rw, uintptr_t addr) -{ - qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); - flush_idcache_range(jmp_rx, jmp_rw, 4); -} - typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4]; From patchwork Tue Sep 21 02:25:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514384 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp2638670jao; Mon, 20 Sep 2021 19:27:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzvytCRiJwAggf1mKSb0OF5XyMZGYQX1UZmm/C4aqpqTthiEUIhgLoUxoxiwUeo89rVGokR X-Received: by 2002:a05:6e02:1a8d:: with SMTP id k13mr18488107ilv.70.1632191228935; Mon, 20 Sep 2021 19:27:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632191228; cv=none; d=google.com; s=arc-20160816; b=jdTrHqCrcLpazr7I0x1qRsSBJh0hNakEerSzeQgNcYiL2faXIgA+uvcWF0ccC0v3ac ePQzHLd1FEK8ACD9Q0OClchs+NJmfXNhjGWTumpP1OGNqhDdET4KUW+P4JKXSzvBn3ck 1RI2kIIonrws4X985qBYOQog3HAGTVpI9hQbxYgTDlP27srMkkpYSEII9KueIOEBCyhU Aql2v+dH3ECd4sZLnBPI0F8bvzwnsoZOjJRsl+0VxERR9ClUPZjolnUl949gPGSdiLrm Ll8Mw4xHm4EaB4x+O7PKvLMrkdcloeZzVj65AEBn5RhiUmCYkM1pSHM5dEPPhRXI+K/i 1rdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zxXZyIG+Pw01TAIshh/v24ac5SJa+rYMBmTa7I6pYe8=; b=P99I4/zkpm0ZPFBiECWZSzBPXK5Oqw74NoXsrL/MQIKRzmInKK9xvFDZbKst0lujGs HDBgOPSJxbGdPKWIc4QyzT5M6dHHyPtgLje7JZ4vla+2tUYMMZjxu+nNj2RhRNZFYPRd I04gRcEp/GSUfRIUR/tgzrt0jwLVm/xFmp5+4D1lC/eFkC1+/smqe4lJV4+DDi8boD2F 7e0fajnqRUhYuFYatBKjaxs8MF9On4PL+Is9cb6U1CR2xqLtIc9FdePCUat+W1xIdsZn wACPn99ecVNfVkuhQl3ZyRrSJzDqpFUz1wUdPeSSkphovmGQRUVBDVy+7/X/0wtvmToA sH7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tMsuVb0c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) -#ifdef __mips__ -/* - * In order to use J and JAL within the code_gen_buffer, we require - * that the buffer not cross a 256MB boundary. - */ -static inline bool cross_256mb(void *addr, size_t size) -{ - return ((uintptr_t)addr ^ ((uintptr_t)addr + size)) & ~0x0ffffffful; -} - -/* - * We weren't able to allocate a buffer without crossing that boundary, - * so make do with the larger portion of the buffer that doesn't cross. - * Returns the new base and size of the buffer in *obuf and *osize. - */ -static inline void split_cross_256mb(void **obuf, size_t *osize, - void *buf1, size_t size1) -{ - void *buf2 = (void *)(((uintptr_t)buf1 + size1) & ~0x0ffffffful); - size_t size2 = buf1 + size1 - buf2; - - size1 = buf2 - buf1; - if (size1 < size2) { - size1 = size2; - buf1 = buf2; - } - - *obuf = buf1; - *osize = size1; -} -#endif - #ifdef USE_STATIC_CODE_GEN_BUFFER static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); @@ -526,12 +494,6 @@ static int alloc_code_gen_buffer(size_t tb_size, int splitwx, Error **errp) size = QEMU_ALIGN_DOWN(tb_size, qemu_real_host_page_size); } -#ifdef __mips__ - if (cross_256mb(buf, size)) { - split_cross_256mb(&buf, &size, buf, size); - } -#endif - region.start_aligned = buf; region.total_size = size; @@ -573,39 +535,6 @@ static int alloc_code_gen_buffer_anon(size_t size, int prot, return -1; } -#ifdef __mips__ - if (cross_256mb(buf, size)) { - /* - * Try again, with the original still mapped, to avoid re-acquiring - * the same 256mb crossing. - */ - size_t size2; - void *buf2 = mmap(NULL, size, prot, flags, -1, 0); - switch ((int)(buf2 != MAP_FAILED)) { - case 1: - if (!cross_256mb(buf2, size)) { - /* Success! Use the new buffer. */ - munmap(buf, size); - break; - } - /* Failure. Work with what we had. */ - munmap(buf2, size); - /* fallthru */ - default: - /* Split the original buffer. Free the smaller half. */ - split_cross_256mb(&buf2, &size2, buf, size); - if (buf == buf2) { - munmap(buf + size2, size - size2); - } else { - munmap(buf, size - size2); - } - size = size2; - break; - } - buf = buf2; - } -#endif - region.start_aligned = buf; region.total_size = size; return prot; @@ -620,35 +549,15 @@ static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) void *buf_rw = NULL, *buf_rx = MAP_FAILED; int fd = -1; -#ifdef __mips__ - /* Find space for the RX mapping, vs the 256MiB regions. */ - if (alloc_code_gen_buffer_anon(size, PROT_NONE, - MAP_PRIVATE | MAP_ANONYMOUS | - MAP_NORESERVE, errp) < 0) { - return false; - } - /* The size of the mapping may have been adjusted. */ - buf_rx = region.start_aligned; - size = region.total_size; -#endif - buf_rw = qemu_memfd_alloc("tcg-jit", size, 0, &fd, errp); if (buf_rw == NULL) { goto fail; } -#ifdef __mips__ - void *tmp = mmap(buf_rx, size, PROT_READ | PROT_EXEC, - MAP_SHARED | MAP_FIXED, fd, 0); - if (tmp != buf_rx) { - goto fail_rx; - } -#else buf_rx = mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0); if (buf_rx == MAP_FAILED) { goto fail_rx; } -#endif close(fd); region.start_aligned = buf_rw; From patchwork Tue Sep 21 02:25:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514390 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp2641456jao; Mon, 20 Sep 2021 19:32:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx20ikWztPHl9Iu3LbiAzXix8LHLpzvZy9rz20+0e3ce2ykaLZPkPI5PeqjO1HUVsSwps9O X-Received: by 2002:a05:6e02:1786:: with SMTP id y6mr13187017ilu.147.1632191529127; Mon, 20 Sep 2021 19:32:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632191529; cv=none; d=google.com; s=arc-20160816; b=btPysKFR8itSxrT/JbfrKze+WqEFp9SDzfza3tT7ARtW4p8abPN4ZM8OArKe5UiVt0 GACAmkhIXIIfzTBvjHte3wBlXkeUfvMnaZH8KDYdHpEsrd/e9CI9juO4rQvlkXa3mjLN QrF3RQwGTB3vIYwo9nW8gKrvKAlVPoFvHJppwfbvPOlkM/kLCSKaRdinVTRB7sQBt9Do HaCw4L6bOAKPuxQ+3thX4hzvV3UiG9N49fIvqtAjvdvPhYaEGL1PXYzlh28WFZG7IdM+ 8Aoke4RNgCrlzU08nrHFQ7Xlm3tJdcMzWkXuZcgQHOLhx/2VhedFXLoMLQ7wKq3C58Ra 1zrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ls0KyBh45JfBQfAk7i0S5ef1RFy/+/wZAVM/jQsZv0w=; b=iXfFKyLFeyKakJ3a5C/X36saTX80nClWhMIfr1uGZMwbDCZY7fU2DCKCNZzuK1bxqT Qd2Z5DPBlH8MV7cuHIC3f99btZ8XTfw6UUZCnWItav5M5nhrvjqZr75fvZQKEtluPzam rIV4mrPo0DA3++snNq4kYBYuPAzbAc2lZ3xJw6EIXMKpD4CyqMZFgC4yzXw9lWR9ckmL ATtwUMILTSrn0dAuWipWTsDLtKenQ9eZInHOPT3rkt9vwFdeVDGnR6HjsoarlFKRxk6M 68HaRXYUXqcs7sgG5u58N4ZulPhpINBJNKKVaEC+ZsRcKX79qgf/nu3F22cyqBzjG299 aR9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BzKTvXxr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 45 +++++++++++++++++++------------------- 1 file changed, 22 insertions(+), 23 deletions(-) -- 2.25.1 diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 688827968b..1763253edd 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -294,12 +294,12 @@ static const int tcg_target_call_oarg_regs[] = { bool use_vis3_instructions; #endif -static inline int check_fit_i64(int64_t val, unsigned int bits) +static bool check_fit_i64(int64_t val, unsigned int bits) { return val == sextract64(val, 0, bits); } -static inline int check_fit_i32(int32_t val, unsigned int bits) +static bool check_fit_i32(int32_t val, unsigned int bits) { return val == sextract32(val, 0, bits); } @@ -362,14 +362,14 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) } } -static inline void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, - TCGReg rs2, int op) +static void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, + TCGReg rs2, int op) { tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); } -static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, - int32_t offset, int op) +static void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, + int32_t offset, int op) { tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); } @@ -381,8 +381,7 @@ static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); } -static inline bool tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { if (ret != arg) { tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); @@ -390,12 +389,12 @@ static inline bool tcg_out_mov(TCGContext *s, TCGType type, return true; } -static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) +static void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) { tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); } -static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg) +static void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg) { tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); } @@ -470,14 +469,14 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } } -static inline void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) { tcg_out_movi_int(s, type, ret, arg, false); } -static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, - TCGReg a2, int op) +static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, + TCGReg a2, int op) { tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); } @@ -494,20 +493,20 @@ static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr, } } -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg arg1, intptr_t arg2) { tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); } -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); } -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) { if (val == 0) { tcg_out_st(s, type, TCG_REG_G0, base, ofs); @@ -527,12 +526,12 @@ static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, const void *arg) tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, (uintptr_t)arg & 0x3ff); } -static inline void tcg_out_sety(TCGContext *s, TCGReg rs) +static void tcg_out_sety(TCGContext *s, TCGReg rs) { tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); } -static inline void tcg_out_rdy(TCGContext *s, TCGReg rd) +static void tcg_out_rdy(TCGContext *s, TCGReg rd) { tcg_out32(s, RDY | INSN_RD(rd)); } @@ -552,7 +551,7 @@ static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, uns ? ARITH_UDIV : ARITH_SDIV); } -static inline void tcg_out_nop(TCGContext *s) +static void tcg_out_nop(TCGContext *s) { tcg_out32(s, NOP); } From patchwork Tue Sep 21 02:25:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514386 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp2639756jao; Mon, 20 Sep 2021 19:29:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyq14GUCA3a7e4fbvlntMEWpiZMQ+JrCV79ABnE3bO74B3ewFeDyH3eDWtzJbYMtXUGSo/6 X-Received: by 2002:a5d:9708:: with SMTP id h8mr20862618iol.170.1632191358034; Mon, 20 Sep 2021 19:29:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632191358; cv=none; d=google.com; s=arc-20160816; b=vBQDZTlBvyDNW/Z0dJQ0s5yfVdKPdqonzJ9BVccPI+Xb20vGy07z18UYj+Sh1Yn5OB PLfU+zJacb7LS183v5N80b74N23pp9rLJmAKfjJxFgdGj8X7DN6ErlB0BbJigNvoPqic cfg3OTVJF4bQlxWotQoPqEuFrJe40kjA3kbzybfYhegnp3i67XxknVY/6aZIfxOwmJqM Lf2fJ2Dkw7KGJwqHhtNAoHUIJTMj8xMvlHiR38MW0FWLSL1Fpot8huWOiNaZzmWa1qVm b5BDxQZEdUAi/TVW4hR4g0ohQwYLD1Q7MWC4rxc7dLKSg/WmR+7XpZ1CkhVDUmNByil3 Whig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PdcS/QGFTvc6ZKaUfNXcEO6hRsowcjhW++K3hiiKcz0=; b=1KCl53KQAibQHYV6PswmSaDG9BcJtU8jZZfupGVI+AhuZEvBVgMGdPwIx1CgIphYtz Mpo0npeYChXQEsI9sjaUcADkadDwJYfYpsG+APPF0MxrVNnFD5amQ/zGjUgOYlAYQBio 2YMWoy3DdTDunPOfWzYU+4jpBdOhHJwdlP1K9Q9K5t9FJgWPgqtlcDArk8jXj8X97LjV hb2di6xrlwrjvPriIkJT9O1yrHcfLylInsOa0gp1NqDXc+M3xrgwhMRTNBQfSoGhMJp3 BMK5z1wWmgA9NLKJReoy4pQKh3kOnwoWW9yKGZhWBT8JQfLgGUlPleMYwddbRRGQKDQg urrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qYCIdRpZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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The only current use, for INDEX_op_goto_ptr, will always require the move but properly documents the delay slot. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 1763253edd..9720d76abd 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -362,6 +362,11 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) } } +static void tcg_out_nop(TCGContext *s) +{ + tcg_out32(s, NOP); +} + static void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, TCGReg rs2, int op) { @@ -389,6 +394,15 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) return true; } +static void tcg_out_mov_delay(TCGContext *s, TCGReg ret, TCGReg arg) +{ + if (ret != arg) { + tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); + } else { + tcg_out_nop(s); + } +} + static void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) { tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); @@ -551,11 +565,6 @@ static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, uns ? ARITH_UDIV : ARITH_SDIV); } -static void tcg_out_nop(TCGContext *s) -{ - tcg_out32(s, NOP); -} - static const uint8_t tcg_cond_to_bcond[] = { [TCG_COND_EQ] = COND_E, [TCG_COND_NE] = COND_NE, @@ -1349,7 +1358,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_ptr: tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); if (USE_REG_TB) { - tcg_out_arith(s, TCG_REG_TB, a0, TCG_REG_G0, ARITH_OR); + tcg_out_mov_delay(s, TCG_REG_TB, a0); } else { tcg_out_nop(s); } From patchwork Tue Sep 21 02:25:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514391 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp2642091jao; Mon, 20 Sep 2021 19:33:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz1iRTKcV3tu/2PvmEfio7noz8o46cv5Ur7Rgnr4o37LR/2QL/0XIDKH1iM+fNNbvK57Hxs X-Received: by 2002:a05:6602:2182:: with SMTP id b2mr5669459iob.45.1632191593597; Mon, 20 Sep 2021 19:33:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632191593; cv=none; d=google.com; s=arc-20160816; b=Yns6oNibqb8XcjCM4RvqOsY36/fexU9B+HVzNViSIBoNxSRAzcAPfXlHqXViqW4r7O fLcLeYtg3JEYgsSjHIui66p6DsV9WnJ/L/Eq5dWwCQ83KLM5jGFZBXEQd8dKf0nMbCxi hTDIofJrO3UNorl7nd+dLwuGIkQDjc6InxB4fqP/VBHOLWPvF78crOzJQPxSdD0dB5FV sEkD70JHUgaQz2n5NocfDEsH8XxmZgV5LiPgvqfy7GGyQOaDaZD23WlrTJr8jte4F4d0 YpH5lRsY4ncftDzHM1WpWonQE2mEavvB4caziTFQHHmIL9/Jk/GhbAlCgevjI+v2wJJY 8bSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MpOMNzZjs3eYQt+AetmKowQQtI1fMdvXZt6ja8gx9sA=; b=ePG9E0ricgjhZm1CC1siWIO3wqKtiocEO+cGz4rlxWA+MOt5bA2B5i9CGUGeJDZgVD y/zXV+KSkFR3N5qNJrccn/AtFCEgsfhvAiU5CF674cjPbXeO23K0xS2/ljsLO+bp6rwj Jpyiso7jUGzCTxg15h8xMqgpcn7lpDA4Dd38IT/yPIXzDb5zTMsBtPT4hhMABfzmSuWA UaQqmez907nKb1WjaCnwrE3BgfDWkoFaQREQ3f4r5KNcw2FpJDE6xClWUulgjc1JTbNW Ij+mlKfFcaZW0oxN/gJz3NgIBbirPaX3wCyCwBldGQEuOWmrABFKauLIqLf+FwXEOAbM GDvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nCcReL1T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Alistair Francis Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 3 ++- target/alpha/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/microblaze/cpu.h | 2 +- target/mips/tcg/tcg-internal.h | 4 ++-- target/nios2/cpu.h | 4 ++-- target/ppc/internal.h | 4 ++-- target/riscv/cpu.h | 2 +- target/s390x/s390x-internal.h | 4 ++-- target/sh4/cpu.h | 4 ++-- target/xtensa/cpu.h | 4 ++-- target/hppa/cpu.c | 7 ++++--- 12 files changed, 23 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 55123cb4d2..6cbe17f2e6 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -78,10 +78,11 @@ struct TCGCPUOps { MemTxResult response, uintptr_t retaddr); /** * @do_unaligned_access: Callback for unaligned access handling + * The callback must exit via raising an exception. */ void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; /** * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index ce9ec32199..772828cc26 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -283,8 +283,8 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #define cpu_list alpha_cpu_list diff --git a/target/arm/internals.h b/target/arm/internals.h index cd2ea8a388..8a77929793 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -594,7 +594,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); /* Raise a data fault alignment exception for the specified virtual address */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; /* arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 13ed3cd4dd..b7a848bbae 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -361,7 +361,7 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); #endif /* !CONFIG_USER_ONLY */ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index c7a77ddccd..bad3deb611 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -22,8 +22,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; const char *mips_exception_name(int32_t exception); diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 88a511209c..a80587338a 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -197,8 +197,8 @@ void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; void do_nios2_semihosting(CPUNios2State *env); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index b71406fa46..55284369f5 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -213,8 +213,8 @@ void helper_compute_fprf_float128(CPUPPCState *env, float128 arg); /* Raise a data fault alignment exception for the specified virtual address */ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; /* translate.c */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 465142616a..5896aca346 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -344,7 +344,7 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr); + uintptr_t retaddr) QEMU_NORETURN; bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 7a6aa4dacc..27d4a03ca1 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -274,8 +274,8 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; /* fpu_helper.c */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 56f7c32df9..dc81406646 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -209,8 +209,8 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; void sh4_translate_init(void); bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 646965f379..f9a510ca46 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -581,8 +581,8 @@ void xtensa_count_regs(const XtensaConfig *config, int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #define cpu_list xtensa_cpu_list diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e8edd189bf..89cba9d7a2 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -72,9 +72,10 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) } #ifndef CONFIG_USER_ONLY -static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +static void QEMU_NORETURN +hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; From patchwork Tue Sep 21 02:25:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514388 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp2639778jao; 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Mon, 20 Sep 2021 19:25:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/10] tcg/riscv: Remove add with zero on user-only memory access Date: Mon, 20 Sep 2021 19:25:34 -0700 Message-Id: <20210921022534.365291-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org> References: <20210921022534.365291-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c16f96b401..dc8d8f1de2 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1130,10 +1130,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) tcg_out_ext32u(s, base, addr_regl); addr_regl = base; } - - if (guest_base == 0) { - tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); - } else { + if (guest_base != 0) { tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); } tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); @@ -1199,10 +1196,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) tcg_out_ext32u(s, base, addr_regl); addr_regl = base; } - - if (guest_base == 0) { - tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); - } else { + if (guest_base != 0) { tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); } tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);