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Signed-off-by: Etienne Carriere --- include/scmi_agent.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/include/scmi_agent.h b/include/scmi_agent.h index f1be9ff209..ed40c7360a 100644 --- a/include/scmi_agent.h +++ b/include/scmi_agent.h @@ -45,9 +45,9 @@ struct scmi_msg { } /** - * scmi_send_and_process_msg() - send and process a SCMI message + * devm_scmi_process_msg() - Send and process an SCMI message * - * Send a message to a SCMI server through a target SCMI agent device. + * Send a message to an SCMI server through a target SCMI agent device. * Caller sets scmi_msg::out_msg_sz to the output message buffer size. * On return, scmi_msg::out_msg_sz stores the response payload size. * From patchwork Thu Nov 4 14:23:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 516804 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp1993111iml; Thu, 4 Nov 2021 07:23:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzM8mQ8kQbKrBt2ASGtjvTZLkkXxJKkEdgmu9MvQNTXMTZJiisSDe8+g7IIQbsxNf9//Cgh X-Received: by 2002:aa7:c4d3:: with SMTP id p19mr27174018edr.333.1636035821815; Thu, 04 Nov 2021 07:23:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1636035821; cv=none; d=google.com; s=arc-20160816; b=hFmSK5fy3KG16xMYSj9bg2ufnVeX5+XkTNuoNigj6+xdBhvrHmbsymRHPtWTxREC2i KwZ3E/bUM2toqtqPrOKLsPjg6da5uxisjvMGH5oTYucVeUnoa9s4Pdzz7vbnGqguozfL aUU3dpLlfIVh9+sY39UQFs+6lms8FGi/Tnsuuij3Mpnorkx1jXfMylrfyv0J9VVTqTSI uAYAuBs21uNFkWu9n+ydHoZzwm22CxAdVTX4p7BNjACqRcBnbUGqoBeToejBEMUZbgWI ygXklkl1DTqwsBTMlxzQUwlc6nQKAhPrE3dFhyeSg6HWqAEzf3bOmeNTWHERfZtr/YLS sY7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=JggBeFHHolj55WSUBAPxLNQxZcRtOj7nr8UyKpjH6LY=; b=xLYxmJvnn+SJF6PK/nzh7nBLBsdiMaf98dQBJ9SI8CugqsGydghVHDRurAnzbCJnNr a1h2i7ltGmPKYSJtvwyu4n+VgU4JCBX8AsDlyJrqSkeuUORyc3BMogoKFMT0ee15IHqL WzUznJb8xrFWE2QKLYFwHYnQwyvN0LnhGuKk3EpTBmOKH1pb0TQDK9uoJe5V2jJFPuwb AYhfvPspDIoulJDmL7X6+TCPvSGcefxnhkQQJJX3vYrG1JnbahlskW+N57TvKc6Lpn8k 8fd5uDGc72BS3xRHUmZfVAWeha/nn4bcpr10eTORRjyEOiEicE/H7AG207qVtz/jokXB m7qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fCqJEDCY; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: Etienne Carriere --- drivers/firmware/scmi/mailbox_agent.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c index ea35e7e09e..eb841d692b 100644 --- a/drivers/firmware/scmi/mailbox_agent.c +++ b/drivers/firmware/scmi/mailbox_agent.c @@ -72,17 +72,13 @@ int scmi_mbox_probe(struct udevice *dev) ret = mbox_get_by_index(dev, 0, &chan->mbox); if (ret) { dev_err(dev, "Failed to find mailbox: %d\n", ret); - goto out; + return ret; } ret = scmi_dt_get_smt_buffer(dev, &chan->smt); if (ret) dev_err(dev, "Failed to get shm resources: %d\n", ret); -out: - if (ret) - devm_kfree(dev, chan); - return ret; } From patchwork Thu Nov 4 14:23:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 516807 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp1993726iml; Thu, 4 Nov 2021 07:24:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtgYrf7j6U9aX0YD/fRJURP+yYrlboCMRb4UnOoVoQplnw2qmmgrRBmZBJUdSYO+rg3vB6 X-Received: by 2002:a17:907:7b98:: with SMTP id ne24mr34167974ejc.14.1636035857527; Thu, 04 Nov 2021 07:24:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1636035857; cv=none; d=google.com; s=arc-20160816; b=shMIKmObt7myGEkQTYeRAAUj90EKy7EH/ChNPdrw6FPoOn0BdWTyufGjFlJ0HSfyaM uGcspSwZTTNYuP/L+7//1cJ1CAOsGFFXZ1sVQRI0z6HFZENDNwbR2ciAi7HtJlAy7Thl ZqDqADI3z4ZovFt1AjM1+Idy2h9W691MePH+nvU5SB0nx0jFmGO7fdqsL/dOH7vCXpAW RYC2YbpHumXlARB7RjeNE09Tck1Ptju3CluxCvdOfOR9mptZpkKJRVbLHSOrPUklAJdh iIaP/C+pSle+8CYxQ877Iex6Bx/ZLhUydUlsGD9LC5RD9uHdBFyJtXaA596yLbht6kjG 3h2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=d3VHB6izkJfAHSS8Z/yD5Qmdqq2UUmOo/K4yKfLWLO8=; b=PNj6KeshpzztcmgGRJcRa95JNTFVBCO2ZbBKlIDMsZQrbN/eX0wrfwQ/5+PaK3lNhX EamLwHNeHsaPtjI7Fw2/Z52LX/USkiROzKmi94PngS5ioVqncacu5R3TlCAajuvCUBNx 0DieYTS7F4eKg1jkggOo6rL4SoRkZDyD3lzEvIhDNurypxFJ1tZJOqq59HZvL4xXleVH 2VWaCfJWidba78D4X4ebUyODyYMHJqtczV3+j582UP+B4Ogh2HWHIlfanu4eNJEJPsgL Z6I/iNfqNI415VqZllb41oi+vzZGEMPd2MGT8DK3hmY5lL1D0iU1ZsH2dCIzkNilx7MT Jnww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sXculUh3; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Consequently the probe handler is replaced with a of_to_plat handler. Signed-off-by: Etienne Carriere --- drivers/firmware/scmi/mailbox_agent.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c index eb841d692b..8e4af0c8fa 100644 --- a/drivers/firmware/scmi/mailbox_agent.c +++ b/drivers/firmware/scmi/mailbox_agent.c @@ -33,7 +33,7 @@ struct scmi_mbox_channel { static int scmi_mbox_process_msg(struct udevice *dev, struct scmi_msg *msg) { - struct scmi_mbox_channel *chan = dev_get_priv(dev); + struct scmi_mbox_channel *chan = dev_get_plat(dev); int ret; ret = scmi_write_msg_to_smt(dev, &chan->smt, msg); @@ -62,9 +62,9 @@ out: return ret; } -int scmi_mbox_probe(struct udevice *dev) +int scmi_mbox_of_to_plat(struct udevice *dev) { - struct scmi_mbox_channel *chan = dev_get_priv(dev); + struct scmi_mbox_channel *chan = dev_get_plat(dev); int ret; chan->timeout_us = TIMEOUT_US_10MS; @@ -95,7 +95,7 @@ U_BOOT_DRIVER(scmi_mbox) = { .name = "scmi-over-mailbox", .id = UCLASS_SCMI_AGENT, .of_match = scmi_mbox_ids, - .priv_auto = sizeof(struct scmi_mbox_channel), - .probe = scmi_mbox_probe, + .plat_auto = sizeof(struct scmi_mbox_channel), + .of_to_plat = scmi_mbox_of_to_plat, .ops = &scmi_mbox_ops, }; From patchwork Thu Nov 4 14:23:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 516810 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp1994391iml; Thu, 4 Nov 2021 07:24:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtaIYg55EL3+mATfAxd22r5h5q2fINBpSD0NTJPjkwvpftqSGaE650RKJHvWRPagrPIDnZ X-Received: by 2002:a05:6402:350b:: with SMTP id b11mr12243378edd.184.1636035890669; Thu, 04 Nov 2021 07:24:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1636035890; cv=none; d=google.com; s=arc-20160816; b=QBGOZembzPFmHrjCllA4N2RQxg22IEi+PgrHrSYnok06508EYLq8fGUvnIv0we9R8e DAG8i2j/hDusYqYet3xEV5mrB2avzSSbQQJS2y/MtV13Q3/FOhxsqw3YD4ky3GQl6T8G XVD04QTP/yzz6BG/cSub5yblWDc1MDul4L2Bt6h0YUnDaX256JzVIw3508XAMyPgXvUo 8JvmT5F+JfvK7tsVSNgMWX+9GMvgSuqWYosBQuCJdFIo0LtemDHBQT7Xpx9kMW/8M/KN e15BaOwoNeAJPxfbB+yp0/CWcVV8irHBd45olIURX4mkytUaEH4Mwfg9pZPSRI0HR1oe pReg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=js8EbXkaLLnAB6JhLc4CliLfyFNg3BTLbv81LacT3VA=; b=r0xEoF6JcCDyQoS/JJ32q6N0ImX+TYNvgKkhsPYWjIVhJ0oEz7tQKSYqDOW+OgTTwU 1JzoscC+jCcoAwTknf0GJ7bQOJajr9iZBVfOnmcwExJfrysTJj950Rb1t+kSBolShQ3D jj7af7x0ZFDBoFPPr2Q7aHYtkNcAQ5PmO2AZKFk3hxhNQgLbY7KaEW8pnbtfmR7vEZ3B FHUW4HLCyAGS8fV1SnhKY3O0NlIvGxPFbVPyOq7ABf9n0ATtBPLsgw/3Onl9JOwNnYSy VjBei4z3SyFzEczDFvahUmRG92u+Bm49Fd6zGWcsG/0Y1685d37hJgS/erqDhZl1BC8N 7Zbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K3YJm7tN; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Consequently the probe handler is replaced with a of_to_plat handler. Signed-off-by: Etienne Carriere --- drivers/firmware/scmi/smccc_agent.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c index f185891e8f..f0477b91dc 100644 --- a/drivers/firmware/scmi/smccc_agent.c +++ b/drivers/firmware/scmi/smccc_agent.c @@ -32,7 +32,7 @@ struct scmi_smccc_channel { static int scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg) { - struct scmi_smccc_channel *chan = dev_get_priv(dev); + struct scmi_smccc_channel *chan = dev_get_plat(dev); struct arm_smccc_res res; int ret; @@ -51,9 +51,9 @@ static int scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg) return ret; } -static int scmi_smccc_probe(struct udevice *dev) +static int scmi_smccc_of_to_plat(struct udevice *dev) { - struct scmi_smccc_channel *chan = dev_get_priv(dev); + struct scmi_smccc_channel *chan = dev_get_plat(dev); u32 func_id; int ret; @@ -86,7 +86,7 @@ U_BOOT_DRIVER(scmi_smccc) = { .name = "scmi-over-smccc", .id = UCLASS_SCMI_AGENT, .of_match = scmi_smccc_ids, - .priv_auto = sizeof(struct scmi_smccc_channel), - .probe = scmi_smccc_probe, + .plat_auto = sizeof(struct scmi_smccc_channel), + .of_to_plat = scmi_smccc_of_to_plat, .ops = &scmi_smccc_ops, }; From patchwork Thu Nov 4 14:23:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 516808 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp1993944iml; Thu, 4 Nov 2021 07:24:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9niXNDE1BRCBC/WVqkRjvLv06becq9EjcOLi1E00J9p0U/MNZdDzaJXC7vqzIFtikjnPY X-Received: by 2002:a17:906:4fd6:: with SMTP id i22mr62002436ejw.92.1636035868337; Thu, 04 Nov 2021 07:24:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1636035868; cv=none; d=google.com; s=arc-20160816; b=BHHf15bWOIHCuKsawLDWfEDDPX8WDwHCeHHTR6w49oi/Kisu7anacTfGcpQPyscIi8 ETLjVrW9304Z/toqwQqiz6322KGf08FGWqO8DMNUNsh3TJK1fgnCTPdqyS0r7cdWi6WY UL5ppfQPVBnA8WNeFQPXUhDdRIRnmBjHxRuY8sh/AAuY8QsS1y/FiMBSoyD+GhHkuVcy +DwkVuTK5Wt36ygjI/kaPXD0tZRAEfkSbSa5UhM/IaXj3dXTkTeBPl12CV4jpoHF2edK pyO/OrF4HMfn3GIcuviR2d2rV6VqR/pWkl2yBdtTfCuyiut132b1lRhTywSAi9rhz/D9 dawQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=mMHZHxfXqKS/z4MJ0PbbuCxqzHJG8u1CMK7TayAQZPc=; b=c5xTqYDebAExpU7ymqytNxjfHUM3cQf+2Mwa7G9wnLfCRLqikWuhm9R3haVAhtAkKP 2i8Sh04RlULFdrhdhs1frqCaE3EsI5uXmVuHHYSvzaqzmRU/PaVei6wp8kg+c69c6N1b wUNSPsew30pHnQguz06wt9exO9R2iGrZnJWhXIZL2YcY27ViqaFZO20pGpYpGz7NbTjq GSSfJbAtwQwup0BD7czFNXHa3ngx4UDvHENw2frphSQc8xdyd9fvYeSDo75jY5aQgEWc UISKF1V7tSvrqf7g5pS4JOvqW/e43PmylmFfSrgUO9UMM0VFk8tb+a1zdnpKyg36C/Uv 6pfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HWo7hMUS; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: Etienne Carriere --- drivers/firmware/scmi/smccc_agent.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c index f0477b91dc..5e166ca93e 100644 --- a/drivers/firmware/scmi/smccc_agent.c +++ b/drivers/firmware/scmi/smccc_agent.c @@ -65,12 +65,10 @@ static int scmi_smccc_of_to_plat(struct udevice *dev) chan->func_id = func_id; ret = scmi_dt_get_smt_buffer(dev, &chan->smt); - if (ret) { + if (ret) dev_err(dev, "Failed to get smt resources: %d\n", ret); - return ret; - } - return 0; + return ret; } static const struct udevice_id scmi_smccc_ids[] = { From patchwork Thu Nov 4 14:23:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 516806 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp1993525iml; Thu, 4 Nov 2021 07:24:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyVO6rHnVHWuwfmB5xu6taXz0gHZFsoomfMLkF3PI+0J1/Bc8NGrN2wPJdz9oSYCPOfGRJ2 X-Received: by 2002:a17:906:3784:: with SMTP id n4mr63199204ejc.129.1636035846926; Thu, 04 Nov 2021 07:24:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1636035846; cv=none; d=google.com; s=arc-20160816; b=CKbnwlIb0ah59H3APBo2kC/Ur5tvKBYmv2mbw5Ejat8+dfdO1pEEUG8fVcsng9gxmK OCo0iJDqtLoA0aAU4tj5X0TAxHv8HEonPn9x4an3OTPUV/4I4bb2Iq+Q2ptD/UP7Y+SE YC24cjptbvx8qT4TgBgVPjazGpqfCI2JPQUG1Yq9Wtgu0C6EEftwgSDvgj7fx1uxSM3o C0Yq4l/js4pSeCQDP60hPvsAkfq8XhwqX/598bDRqTqfWB48JWc7OJJrxT8QTha3DzsA 5eFgORU5tu7HeupZtrqihX6r8L1DwV/J00Egjjap23rOWfzRR1VHv1IKD1HjTiFWawj3 cRSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=fKNIOeNoajOJQN2ZuKQ3738jTNcEEeFKsoCWSZwTNtw=; b=c4E9ujLIhf1RVPjuH4p1LtNFmaOEvcVbRBIelTeETfpoXWZAdkEqAUyMYk1fMsR+MM mJwwYnfQ/HDo3Qgye58O+l0YD+xUyOySsbqQ1pT+Awbdo8k99FsU8Uj+Lwar5jtJAomz RKBzWVJRgj4I/jlhkIrItwEKqxxDAECaTUe49XUa5Obvpa7s7W+dy+QMK6KC/2WfTnva j6GPl0SffV7KRkRgoQHmuLkijctVqndN2nlvrvEScR+i2ibEELH28duRgfb/nWFdLDdJ SobmKX6H5h3y8jSBiWFXOToCj1m0WfGKzwaUvkhRPHIv0EmTILt/yOzDULgOO034PLs9 ZbDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pFiHFEIv; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Change-Id: I23837c8c879ce5a080b23cb3ac5033d5ba73fb0d Signed-off-by: Etienne Carriere --- configs/stm32mp15_trusted_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index b4ed090e3f..48efdec657 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y CONFIG_TFABOOT=y -CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_OFFSET=0x280000 From patchwork Thu Nov 4 14:23:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 516809 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp1994181iml; Thu, 4 Nov 2021 07:24:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyykgpbRUu73xIPsNXbUCdrJ1freWK0oHCdXprjOZ04/GLDosRSlAPK5fGEAO/nF9A0jEUC X-Received: by 2002:a05:6402:35d2:: with SMTP id z18mr3489008edc.9.1636035880187; Thu, 04 Nov 2021 07:24:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1636035880; cv=none; d=google.com; s=arc-20160816; b=DujB5oeQE/FirTBYZaYK+A132dKquakbDANk2V1SSq13ixH+rTO+djTqh14LUjSd/y Vt4nkDaNNA6ob1/tiGbQ2jRaQfpS9LxgFjBkDEt+2hVRMbfZoZA/gu0XjRtSA0Ia3Qg2 qv5cnTupC/j5lHlYmhE6lzUnQ7DiJU46FgxePQDB7vtOUmQh/z1tm3xAbksFzF0stXrG nJ65NHoYqImuYw/aE79v+Mw40OizAkXjbo1UkaiLu2xQ4suFvoTDw5LSnGuApWrw0ETW tG7jIe6ayxX63XUtfjfE4LyZ3uLjRtaaHso2ZS2Jxuo34jpCjd82P8+Zt6WviZ6Aye/J lsEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=kvI7kN0AmNtN+2oC3gNmhtRnvzlckTEMAfghnXTltcw=; b=G0kG3uWQ6V4tWZEB+rAqDlagZ4t1Tp822I6cNcZwCuSx4Z2qv3vX20bqo2mv3PJ2SD kCDP2OMhqtKvt2fPyFOyfCBO/uzFrmSIJCjmqyyhTsV1yfOIYoi0Sfp1NcmQ8nUWzoi8 14lyvzeJ2CRAJhjDmmJj58dCOPLIHMKp990lgWVNQZ737AADbE27PONXeCjlrdkuVGHe zSB6mNNUyaVcDDkaS/xbkB/HCWs3+6GGi/dInIIdUO2PsK6bPMx5pmr0hf0BR+jp0MDF UJfM2JgEyPa9SIG1yqiuFlLNF94bvWVaD2vLK2gRPbwvs3I9neB+dCbd4yphiSPQNtoV PIHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AqN2rXBD; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: Etienne Carriere --- configs/stm32mp15_trusted_defconfig | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 48efdec657..dc1f48c518 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -116,6 +116,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_STM32_VREFBUF=y CONFIG_DM_REGULATOR_STPMIC1=y +CONFIG_DM_REGULATOR_SCMI=y CONFIG_REMOTEPROC_STM32_COPRO=y CONFIG_RESET_SCMI=y CONFIG_DM_RNG=y From patchwork Thu Nov 4 14:23:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 516811 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp1994595iml; Thu, 4 Nov 2021 07:25:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxteJv4Ec9pUojhidiZV1eGfPBWHI61foxyoXThkCD6y+DVfzOgqdcniDQoa0G0Fg5raMvF X-Received: by 2002:a17:906:4452:: with SMTP id i18mr61442529ejp.374.1636035901212; Thu, 04 Nov 2021 07:25:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1636035901; cv=none; d=google.com; s=arc-20160816; b=X7iCTzWi+/zRXExq1C+LHAqzHTqHqN3auBbf1jP1ua5vNohm957Cw8zrIiV6zHVY6b RypbC1f7sVnj6dGZelpTgLuHvw8TtAteUprPVS6lgKmYK6kdGflqYz4GWDxoQUzmRWpM eJJ1MlOI+eIIqvm8NiPIgepojn6HXzjjQiiAU5alz+xe+JLg7am7rjVQ1zJZrv2gqlsd qhzmhs3JUlMPEjY/ct8ILHgE8ILiFXCovx7gOSxiq/Mh3Zt/XrA9qDtMcTW4WsD7U/ki Xa6/cKDoVFxtrdHU8TeuMQbam1n1w2Kl1AeirlT6KGpMTpH1HH/aOZ4rkymPkotFX34C rPMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=7pS8BZZj0IVqtblSBcuUzvBKqm7MVfdqLOHe5lGKmck=; b=r9B3W0hQOuhm/GRZzWngxvzKDusaQYP6/QnP8Xio8Dd++Xflb2WDwsHUGfC3MQ5E/S OlLwzCBcN9Stc3g/3t5T7eE2LxJ9+dsrVi2A73NtuuWFVksnNSk1YnRevQgg0pKiqnwS lFCZ/tPiYfCWR7db7n5yP1QAU8ZKEJrSpz+u0UV9eMnFq/ouweWf0JU3G5Jfx5ukFAU2 R4Y30MqyKhfzipnQujxEMzlnAiyc3usiSSxXtoKZcJSMGMWh9DnEEbU1Kyfdi0oqgaRi +PjYF5NO/MU5VLPTsuty6u6Gmj6g21bd5BQhTQHaipVthBYdLULJnrURXeXGY7WfgrI5 ahog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FkBy8a1d; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: Etienne Carriere --- .../regulator/st,stm32mp15-regulator.h | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 include/dt-bindings/regulator/st,stm32mp15-regulator.h -- 2.17.1 diff --git a/include/dt-bindings/regulator/st,stm32mp15-regulator.h b/include/dt-bindings/regulator/st,stm32mp15-regulator.h new file mode 100644 index 0000000000..96eb578c00 --- /dev/null +++ b/include/dt-bindings/regulator/st,stm32mp15-regulator.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (C) 2020, STMicroelectronics - All Rights Reserved + */ + +#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H +#define __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H + +/* SCMI voltage domain identifiers */ + +#define VOLTD_SCMI0_REG11 0 +#define VOLTD_SCMI0_REG18 1 +#define VOLTD_SCMI0_USB33 2 +#define VOLTD_SCMI0_STPMIC1_BUCK1 3 +#define VOLTD_SCMI0_STPMIC1_BUCK2 4 +#define VOLTD_SCMI0_STPMIC1_BUCK3 5 +#define VOLTD_SCMI0_STPMIC1_BUCK4 6 +#define VOLTD_SCMI0_STPMIC1_LDO1 7 +#define VOLTD_SCMI0_STPMIC1_LDO2 8 +#define VOLTD_SCMI0_STPMIC1_LDO3 9 +#define VOLTD_SCMI0_STPMIC1_LDO4 10 +#define VOLTD_SCMI0_STPMIC1_LDO5 11 +#define VOLTD_SCMI0_STPMIC1_LDO6 12 +#define VOLTD_SCMI0_STPMIC1_VREFDDR 13 +#define VOLTD_SCMI0_STPMIC1_BOOST 14 +#define VOLTD_SCMI0_STPMIC1_PWR_SW1 15 +#define VOLTD_SCMI0_STPMIC1_PWR_SW2 16 + +#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H */ From patchwork Thu Nov 4 14:23:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 516814 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp1995207iml; Thu, 4 Nov 2021 07:25:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy8de4BVP6GQjOgLnOHqne6YssZmd76SOUXTU8Om6TkOmhRSGQ7Pqg0mUciQqyKeQ22VPp8 X-Received: by 2002:a17:906:489a:: with SMTP id v26mr12552412ejq.305.1636035932873; Thu, 04 Nov 2021 07:25:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1636035932; cv=none; d=google.com; s=arc-20160816; b=06vl8J0T+NG8nBdRCtUWVMsAzV9n3NPaNlUynC+YyevC57epDQJjMbq/4umdPCCsge dV5BhNmYjBGDUmlSfVNLyc9CTaxltJSIc4dm+zMQ9BkAJ5gqm3vTOzDsEPMPkQVZ8X89 CiR6r9IrtwlhxoroMaoO7EyIVLFfd+hHCt8j6snZG79F5P91JvMajovBopdXUrL3xuaP rb5yFe6eQ/4QuWECAQAoa8UAMoL4Aw9fFzAQ4Wa5QmLEY99XpD71UeCCEKP5iYovf2qA /IthHJpYcj0422mhqB5rHmCdW3sHK2xa4fvVTM2mOEUMUNyuO5GTNwAT6zyBXGJSrLXp EJww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=YMqpLb6vrbu+l2zg06bYUebH13GaVRtzHnVVoxQBbUk=; b=xEH4O237MugxAtPQh1zH8jEonQx5HytV/+zTB9kBldFEr8SBQlV6O/+47EAm9M8IS0 XkySSmhCR2WP8WEK7tCNFzxPPFb1kMMe30u1JJ9uGqj93hVwAllsPW7qVbI0aC/3le6Y DygcATdzDJsDXpAnxAywa4/3UDx9iSZhS4saNwSrgW/6T0y1GeNsM0V0O08E4x4IwBpJ HOGNkwBSV9AQOpMqqgKWgjH84rNzz/js/Aoap5KUjXx6jOtiGUGBd26N2hWb95I0ZUIM OXmoXzXA/WGbnWM6qeA84NyfsM+s0HcMotGS0Rton39Bu5rD8xGGKx4X6tRG712iKV4p M4LQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z8a4KiQd; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: Etienne Carriere --- arch/arm/dts/stm32mp15-u-boot.dtsi | 81 +++++------ arch/arm/dts/stm32mp151.dtsi | 145 ++++++++++++-------- arch/arm/dts/stm32mp153.dtsi | 6 +- arch/arm/dts/stm32mp157.dtsi | 2 +- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 114 +-------------- arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi | 40 ++++++ arch/arm/dts/stm32mp157c-dk2.dts | 9 ++ arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 99 +------------ arch/arm/dts/stm32mp157c-ed1.dts | 5 + arch/arm/dts/stm32mp157c-odyssey.dts | 14 ++ arch/arm/dts/stm32mp15xc.dtsi | 4 +- include/dt-bindings/clock/stm32mp1-clks.h | 27 ++++ include/dt-bindings/reset/stm32mp1-resets.h | 14 ++ 13 files changed, 248 insertions(+), 312 deletions(-) -- 2.17.1 diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index 43a7909978..6fd204c635 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -21,23 +21,11 @@ pinctrl1 = &pinctrl_z; }; - clocks { - u-boot,dm-pre-reloc; - }; - /* need PSCI for sysreset during board_f */ psci { u-boot,dm-pre-proper; }; - reboot { - u-boot,dm-pre-reloc; - compatible = "syscon-reboot"; - regmap = <&rcc>; - offset = <0x404>; - mask = <0x1>; - }; - soc { u-boot,dm-pre-reloc; @@ -72,36 +60,6 @@ u-boot,dm-pre-reloc; }; -&clk_csi { - u-boot,dm-pre-reloc; -}; - -&clk_hsi { - u-boot,dm-pre-reloc; -}; - -&clk_hse { - u-boot,dm-pre-reloc; -}; - -&clk_lsi { - u-boot,dm-pre-reloc; -}; - -&clk_lse { - u-boot,dm-pre-reloc; -}; - -&cpu0_opp_table { - u-boot,dm-spl; - opp-650000000 { - u-boot,dm-spl; - }; - opp-800000000 { - u-boot,dm-spl; - }; -}; - &gpioa { u-boot,dm-pre-reloc; }; @@ -161,8 +119,8 @@ /* temp = waiting kernel update */ &m4_rproc { - resets = <&rcc MCU_R>, - <&rcc MCU_HOLD_BOOT_R>; + resets = <&scmi0_reset RST_SCMI0_MCU>, + <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>; reset-names = "mcu_rst", "hold_boot"; }; @@ -174,6 +132,7 @@ u-boot,dm-pre-reloc; }; +// TODO: remove once PWR under SCMI &pwr_regulators { u-boot,dm-pre-reloc; }; @@ -184,6 +143,38 @@ #size-cells = <0>; }; +&scmi0 { + u-boot,dm-pre-reloc; +}; + +&scmi0_clk { + u-boot,dm-pre-reloc; +}; + +&scmi0_reset { + u-boot,dm-pre-reloc; +}; + +&scmi0_shm { + u-boot,dm-pre-reloc; +}; + +&scmi1 { + u-boot,dm-pre-reloc; +}; + +&scmi1_clk { + u-boot,dm-pre-reloc; +}; + +&scmi1_shm { + u-boot,dm-pre-reloc; +}; + +&scmi_sram { + u-boot,dm-pre-reloc; +}; + &sdmmc1 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; }; @@ -197,7 +188,7 @@ }; &usart1 { - resets = <&rcc USART1_R>; + resets = <&scmi0_reset RST_SCMI0_USART1>; }; &usart2 { diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 8e0a0bc1dd..db48077375 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -48,6 +48,69 @@ interrupt-parent = <&intc>; }; + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi0_shm: scmi_shm@0 { + reg = <0 0x80>; + }; + + scmi1_shm: scmi_shm@200 { + reg = <0x200 0x80>; + }; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + + scmi0: scmi0 { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + /* Supply properties for arm,scmi-smc compatible */ + arm,smc-id = <0x82002000>; + shmem = <&scmi0_shm>; + /* Enable only if stm32mp15x RCC[TZEN]=1 */ + status = "disabled"; + + scmi0_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi0_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi1: scmi1 { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <1>; + /* Supply properties for arm,scmi-smc compatible */ + arm,smc-id = <0x82002001>; + shmem = <&scmi1_shm>; + /* Enable only if stm32mp15x RCC[MCKPROT]=1 */ + status = "disabled"; + + scmi1_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -70,38 +133,6 @@ interrupt-parent = <&intc>; }; - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_csi: clk-csi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <4000000>; - }; - }; - thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <0>; @@ -571,7 +602,7 @@ compatible = "st,stm32-cec"; reg = <0x40016000 0x400>; interrupts = ; - clocks = <&rcc CEC_K>, <&clk_lse>; + clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>; clock-names = "cec", "hdmi-cec"; status = "disabled"; }; @@ -1143,16 +1174,19 @@ }; rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; + compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, - <&clk_lse>, <&clk_lsi>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, + <&scmi0_clk CK_SCMI0_HSI>, + <&scmi0_clk CK_SCMI0_CSI>, + <&scmi0_clk CK_SCMI0_LSE>, + <&scmi0_clk CK_SCMI0_LSI>; }; + // TODO: remove once under SCMI pwr_regulators: pwr@50001000 { compatible = "st,stm32mp1,pwr-reg"; reg = <0x50001000 0x10>; @@ -1333,8 +1367,8 @@ compatible = "st,stm32f756-hash"; reg = <0x54002000 0x400>; interrupts = ; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; + clocks = <&scmi0_clk CK_SCMI0_HASH1>; + resets = <&scmi0_reset RST_SCMI0_HASH1>; dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; dma-names = "in"; dma-maxburst = <2>; @@ -1344,8 +1378,8 @@ rng1: rng@54003000 { compatible = "st,stm32-rng"; reg = <0x54003000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; + clocks = <&scmi0_clk CK_SCMI0_RNG1>; + resets = <&scmi0_reset RST_SCMI0_RNG1>; status = "disabled"; }; @@ -1354,7 +1388,7 @@ reg = <0x58000000 0x1000>; interrupts = ; clocks = <&rcc MDMA>; - resets = <&rcc MDMA_R>; + resets = <&scmi0_reset RST_SCMI0_MDMA>; #dma-cells = <5>; dma-channels = <32>; dma-requests = <48>; @@ -1517,7 +1551,7 @@ iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; - clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clocks = <&rcc IWDG2>, <&scmi0_clk CK_SCMI0_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; }; @@ -1549,7 +1583,7 @@ compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; + clocks = <&scmi0_clk CK_SCMI0_USART1>; wakeup-source; status = "disabled"; }; @@ -1560,8 +1594,8 @@ compatible = "st,stm32h7-spi"; reg = <0x5c001000 0x400>; interrupts = ; - clocks = <&rcc SPI6_K>; - resets = <&rcc SPI6_R>; + clocks = <&scmi0_clk CK_SCMI0_SPI6>; + resets = <&scmi0_reset RST_SCMI0_SPI6>; dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, <&mdma1 35 0x0 0x40002 0x0 0x0>; dma-names = "rx", "tx"; @@ -1574,8 +1608,8 @@ interrupt-names = "event", "error"; interrupts = , ; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; + clocks = <&scmi0_clk CK_SCMI0_I2C4>; + resets = <&scmi0_reset RST_SCMI0_I2C4>; #address-cells = <1>; #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x8>; @@ -1587,7 +1621,8 @@ rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; - clocks = <&rcc RTCAPB>, <&rcc RTC>; + clocks = <&scmi0_clk CK_SCMI0_RTCAPB>, + <&scmi0_clk CK_SCMI0_RTC>; clock-names = "pclk", "rtc_ck"; interrupts = ; status = "disabled"; @@ -1615,8 +1650,8 @@ interrupt-names = "event", "error"; interrupts = , ; - clocks = <&rcc I2C6_K>; - resets = <&rcc I2C6_R>; + clocks = <&scmi0_clk CK_SCMI0_I2C6>; + resets = <&scmi0_reset RST_SCMI0_I2C6>; #address-cells = <1>; #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x20>; @@ -1782,7 +1817,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0 0x400>; - clocks = <&rcc GPIOZ>; + clocks = <&scmi0_clk CK_SCMI0_GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; status = "disabled"; @@ -1804,9 +1839,9 @@ reg = <0x10000000 0x40000>, <0x30000000 0x40000>, <0x38000000 0x10000>; - resets = <&rcc MCU_R>; - st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; + resets = <&scmi0_reset RST_SCMI0_MCU>, + <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi index 1c1889b194..e9ba6a9f30 100644 --- a/arch/arm/dts/stm32mp153.dtsi +++ b/arch/arm/dts/stm32mp153.dtsi @@ -13,6 +13,8 @@ clock-frequency = <650000000>; device_type = "cpu"; reg = <1>; + clocks = <&scmi0_clk CK_SCMI0_MPU>; + clock-names = "cpu"; }; }; @@ -30,7 +32,7 @@ interrupts = , ; interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; status = "disabled"; @@ -43,7 +45,7 @@ interrupts = , ; interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi index 54e73ccea4..7b06c08e3a 100644 --- a/arch/arm/dts/stm32mp157.dtsi +++ b/arch/arm/dts/stm32mp157.dtsi @@ -20,7 +20,7 @@ dsi: dsi@5a000000 { compatible = "st,stm32-dsi"; reg = <0x5a000000 0x800>; - clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clocks = <&rcc DSI_K>, <&scmi0_clk CK_SCMI0_HSE>, <&rcc DSI_PX>; clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index 15a04ae927..9e1c9c0329 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -31,6 +31,7 @@ /* only needed for boot with TF-A, witout FIP support */ firmware { optee { + u-boot,dm-pre-reloc; compatible = "linaro,optee-tz"; method = "smc"; }; @@ -38,8 +39,10 @@ reserved-memory { u-boot,dm-spl; + u-boot,dm-pre-reloc; optee@de000000 { + u-boot,dm-pre-reloc; reg = <0xde000000 0x02000000>; no-map; u-boot,dm-spl; @@ -61,117 +64,6 @@ status = "okay"; }; -&clk_hse { - st,digbypass; -}; - -&i2c4 { - u-boot,dm-pre-reloc; -}; - -&i2c4_pins_a { - u-boot,dm-pre-reloc; - pins { - u-boot,dm-pre-reloc; - }; -}; - -&pmic { - u-boot,dm-pre-reloc; -}; - -&rcc { - st,clksrc = < - CLK_MPU_PLL1P - CLK_AXI_PLL2P - CLK_MCU_PLL3P - CLK_PLL12_HSE - CLK_PLL3_HSE - CLK_PLL4_HSE - CLK_RTC_LSE - CLK_MCO1_DISABLED - CLK_MCO2_DISABLED - >; - - st,clkdiv = < - 1 /*MPU*/ - 0 /*AXI*/ - 0 /*MCU*/ - 1 /*APB1*/ - 1 /*APB2*/ - 1 /*APB3*/ - 1 /*APB4*/ - 2 /*APB5*/ - 23 /*RTC*/ - 0 /*MCO1*/ - 0 /*MCO2*/ - >; - - st,pkcs = < - CLK_CKPER_HSE - CLK_FMC_ACLK - CLK_QSPI_ACLK - CLK_ETH_DISABLED - CLK_SDMMC12_PLL4P - CLK_DSI_DSIPLL - CLK_STGEN_HSE - CLK_USBPHY_HSE - CLK_SPI2S1_PLL3Q - CLK_SPI2S23_PLL3Q - CLK_SPI45_HSI - CLK_SPI6_HSI - CLK_I2C46_HSI - CLK_SDMMC3_PLL4P - CLK_USBO_USBPHY - CLK_ADC_CKPER - CLK_CEC_LSE - CLK_I2C12_HSI - CLK_I2C35_HSI - CLK_UART1_HSI - CLK_UART24_HSI - CLK_UART35_HSI - CLK_UART6_HSI - CLK_UART78_HSI - CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4R - CLK_SAI1_PLL3Q - CLK_SAI2_PLL3Q - CLK_SAI3_PLL3Q - CLK_SAI4_PLL3Q - CLK_RNG1_LSI - CLK_RNG2_LSI - CLK_LPTIM1_PCLK1 - CLK_LPTIM23_PCLK3 - CLK_LPTIM45_LSE - >; - - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ - pll2: st,pll@1 { - compatible = "st,stm32mp1-pll"; - reg = <1>; - cfg = < 2 65 1 0 0 PQR(1,1,1) >; - frac = < 0x1400 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ - pll3: st,pll@2 { - compatible = "st,stm32mp1-pll"; - reg = <2>; - cfg = < 1 33 1 16 36 PQR(1,1,1) >; - frac = < 0x1a04 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ - pll4: st,pll@3 { - compatible = "st,stm32mp1-pll"; - reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; - u-boot,dm-pre-reloc; - }; -}; - &sdmmc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi index 06ef3a4095..9f9979dc5f 100644 --- a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi @@ -4,3 +4,43 @@ */ #include "stm32mp157a-dk1-u-boot.dtsi" + +&optee { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&scmi0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&scmi0_clk { + u-boot,dm-pre-reloc; +}; + +&scmi0_reset { + u-boot,dm-pre-reloc; +}; + +&scmi0_shm { + u-boot,dm-pre-reloc; +}; + +&scmi1 { + status = "disabled"; + u-boot,dm-pre-reloc; +}; + +&scmi1_clk { + u-boot,dm-pre-reloc; +}; + +&scmi1_shm { + u-boot,dm-pre-reloc; +}; + +&scmi_sram { + status = "okay"; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 2bc92ef3ae..fb9300fcb1 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -99,3 +99,12 @@ pinctrl-2 = <&usart2_idle_pins_c>; status = "disabled"; }; + +&optee { + status = "okay"; +}; + +&scmi0 { + compatible = "linaro,scmi-optee"; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 408abaf52f..e2e1769d97 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -32,6 +32,8 @@ optee { compatible = "linaro,optee-tz"; method = "smc"; + u-boot,dm-pre-reloc; + status = "okay"; }; }; @@ -39,6 +41,7 @@ optee@fe000000 { reg = <0xfe000000 0x02000000>; no-map; + u-boot,dm-pre-reloc; }; }; #endif @@ -53,10 +56,6 @@ }; }; -&clk_hse { - st,digbypass; -}; - &i2c4 { u-boot,dm-pre-reloc; }; @@ -72,98 +71,6 @@ u-boot,dm-pre-reloc; }; -&rcc { - st,clksrc = < - CLK_MPU_PLL1P - CLK_AXI_PLL2P - CLK_MCU_PLL3P - CLK_PLL12_HSE - CLK_PLL3_HSE - CLK_PLL4_HSE - CLK_RTC_LSE - CLK_MCO1_DISABLED - CLK_MCO2_DISABLED - >; - - st,clkdiv = < - 1 /*MPU*/ - 0 /*AXI*/ - 0 /*MCU*/ - 1 /*APB1*/ - 1 /*APB2*/ - 1 /*APB3*/ - 1 /*APB4*/ - 2 /*APB5*/ - 23 /*RTC*/ - 0 /*MCO1*/ - 0 /*MCO2*/ - >; - - st,pkcs = < - CLK_CKPER_HSE - CLK_FMC_ACLK - CLK_QSPI_ACLK - CLK_ETH_DISABLED - CLK_SDMMC12_PLL4P - CLK_DSI_DSIPLL - CLK_STGEN_HSE - CLK_USBPHY_HSE - CLK_SPI2S1_PLL3Q - CLK_SPI2S23_PLL3Q - CLK_SPI45_HSI - CLK_SPI6_HSI - CLK_I2C46_HSI - CLK_SDMMC3_PLL4P - CLK_USBO_USBPHY - CLK_ADC_CKPER - CLK_CEC_LSE - CLK_I2C12_HSI - CLK_I2C35_HSI - CLK_UART1_HSI - CLK_UART24_HSI - CLK_UART35_HSI - CLK_UART6_HSI - CLK_UART78_HSI - CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4R - CLK_SAI1_PLL3Q - CLK_SAI2_PLL3Q - CLK_SAI3_PLL3Q - CLK_SAI4_PLL3Q - CLK_RNG1_LSI - CLK_RNG2_LSI - CLK_LPTIM1_PCLK1 - CLK_LPTIM23_PCLK3 - CLK_LPTIM45_LSE - >; - - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ - pll2: st,pll@1 { - compatible = "st,stm32mp1-pll"; - reg = <1>; - cfg = < 2 65 1 0 0 PQR(1,1,1) >; - frac = < 0x1400 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ - pll3: st,pll@2 { - compatible = "st,stm32mp1-pll"; - reg = <2>; - cfg = < 1 33 1 16 36 PQR(1,1,1) >; - frac = < 0x1a04 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ - pll4: st,pll@3 { - compatible = "st,stm32mp1-pll"; - reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; - u-boot,dm-pre-reloc; - }; -}; - &sdmmc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 6e89f88a17..eabf00f1fe 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -341,6 +341,11 @@ status = "okay"; }; +&scmi0 { + compatible = "linaro,scmi-optee"; + status = "okay"; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 0e725498dd..9823d5d5ca 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -21,6 +21,20 @@ stdout-path = "serial0:115200n8"; }; + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + }; + led { compatible = "gpio-leds"; blue { diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi index b06a55a2fa..435846883f 100644 --- a/arch/arm/dts/stm32mp15xc.dtsi +++ b/arch/arm/dts/stm32mp15xc.dtsi @@ -10,8 +10,8 @@ compatible = "st,stm32mp1-cryp"; reg = <0x54001000 0x400>; interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; + clocks = <&scmi0_clk CK_SCMI0_CRYP1>; + resets = <&scmi0_reset RST_SCMI0_CRYP1>; status = "disabled"; }; }; diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 4cdaf13582..e02770b98e 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,4 +248,31 @@ #define STM32MP1_LAST_CLK 232 +/* SCMI clock identifiers */ +#define CK_SCMI0_HSE 0 +#define CK_SCMI0_HSI 1 +#define CK_SCMI0_CSI 2 +#define CK_SCMI0_LSE 3 +#define CK_SCMI0_LSI 4 +#define CK_SCMI0_PLL2_Q 5 +#define CK_SCMI0_PLL2_R 6 +#define CK_SCMI0_MPU 7 +#define CK_SCMI0_AXI 8 +#define CK_SCMI0_BSEC 9 +#define CK_SCMI0_CRYP1 10 +#define CK_SCMI0_GPIOZ 11 +#define CK_SCMI0_HASH1 12 +#define CK_SCMI0_I2C4 13 +#define CK_SCMI0_I2C6 14 +#define CK_SCMI0_IWDG1 15 +#define CK_SCMI0_RNG1 16 +#define CK_SCMI0_RTC 17 +#define CK_SCMI0_RTCAPB 18 +#define CK_SCMI0_SPI6 19 +#define CK_SCMI0_USART1 20 + +#define CK_SCMI1_PLL3_Q 0 +#define CK_SCMI1_PLL3_R 1 +#define CK_SCMI1_MCU 2 + #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index 702da37a2e..f3a0ed3178 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -106,4 +106,18 @@ #define GPIOJ_R 19785 #define GPIOK_R 19786 +/* SCMI reset domain identifiers */ +#define RST_SCMI0_SPI6 0 +#define RST_SCMI0_I2C4 1 +#define RST_SCMI0_I2C6 2 +#define RST_SCMI0_USART1 3 +#define RST_SCMI0_STGEN 4 +#define RST_SCMI0_GPIOZ 5 +#define RST_SCMI0_CRYP1 6 +#define RST_SCMI0_HASH1 7 +#define RST_SCMI0_RNG1 8 +#define RST_SCMI0_MDMA 9 +#define RST_SCMI0_MCU 10 +#define RST_SCMI0_MCU_HOLD_BOOT 11 + #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ From patchwork Thu Nov 4 14:23:20 2021 Content-Type: text/plain; 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Thu, 04 Nov 2021 07:23:35 -0700 (PDT) Received: from lmecxl0524.lme.st.com ([2a04:cec0:10b3:52ee:40ee:3a6f:5eb8:bd35]) by smtp.gmail.com with ESMTPSA id m34sm9383297wms.25.2021.11.04.07.23.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Nov 2021 07:23:35 -0700 (PDT) From: Etienne Carriere To: u-boot@lists.denx.de Cc: Etienne Carriere Subject: [PATCH 10/14] [WIP] dts: arm: stm32mp15: enable SCMI regulators (PWR & PMIC) on MP15-DK* Date: Thu, 4 Nov 2021 15:23:20 +0100 Message-Id: <20211104142324.2879-10-etienne.carriere@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104142324.2879-1-etienne.carriere@linaro.org> References: <20211104142324.2879-1-etienne.carriere@linaro.org> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Etienne Carriere --- arch/arm/dts/stm32mp151.dtsi | 40 +++++++++- arch/arm/dts/stm32mp15xx-dkx.dtsi | 122 +++++++++++++++++++++++++----- 2 files changed, 138 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index db48077375..cb6a14ec0c 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -5,6 +5,7 @@ */ #include #include +#include #include / { @@ -91,6 +92,37 @@ reg = <0x16>; #reset-cells = <1>; }; + + scmi0_voltd: protocol@17 { + reg = <0x17>; + + scmi0_reguls: regulators { + #address-cells = <1>; + #size-cells = <0>; + + reg11: reg11 { + reg = ; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + voltd-name = "reg18"; + reg = ; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + reg = ; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; }; scmi1: scmi1 { @@ -1190,20 +1222,22 @@ pwr_regulators: pwr@50001000 { compatible = "st,stm32mp1,pwr-reg"; reg = <0x50001000 0x10>; + status = "disabled"; + secure-status = "okay"; - reg11: reg11 { + pwr_reg11: reg11 { regulator-name = "reg11"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; }; - reg18: reg18 { + pwr_reg18: reg18 { regulator-name = "reg18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - usb33: usb33 { + pwr_usb33: usb33 { regulator-name = "usb33"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 68987f64c5..ba196c7a45 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { memory@c0000000 { @@ -261,7 +262,7 @@ interrupt-parent = <&gpioi>; pinctrl-names = "default"; pinctrl-0 = <&stusb1600_pins_a>; - status = "okay"; + status = "disabled"; vdd-supply = <&vin>; connector { @@ -284,7 +285,8 @@ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; - status = "okay"; + status = "disabled"; + secure-status = "okay"; regulators { compatible = "st,stpmic1-regulators"; @@ -292,18 +294,18 @@ buck2-supply = <&vin>; buck3-supply = <&vin>; buck4-supply = <&vin>; - ldo1-supply = <&v3v3>; + ldo1-supply = <&secure_v3v3>; ldo2-supply = <&vin>; - ldo3-supply = <&vdd_ddr>; + ldo3-supply = <&secure_vdd_ddr>; ldo4-supply = <&vin>; ldo5-supply = <&vin>; - ldo6-supply = <&v3v3>; + ldo6-supply = <&secure_v3v3>; vref_ddr-supply = <&vin>; boost-supply = <&vin>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; + pwr_sw1-supply = <&secure_bst_out>; + pwr_sw2-supply = <&secure_bst_out>; - vddcore: buck1 { + secure_vddcore: buck1 { regulator-name = "vddcore"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; @@ -312,7 +314,7 @@ regulator-over-current-protection; }; - vdd_ddr: buck2 { + secure_vdd_ddr: buck2 { regulator-name = "vdd_ddr"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; @@ -321,7 +323,7 @@ regulator-over-current-protection; }; - vdd: buck3 { + secure_vdd: buck3 { regulator-name = "vdd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -331,7 +333,7 @@ regulator-over-current-protection; }; - v3v3: buck4 { + secure_v3v3: buck4 { regulator-name = "v3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -340,7 +342,7 @@ regulator-initial-mode = <0>; }; - v1v8_audio: ldo1 { + secure_v1v8_audio: ldo1 { regulator-name = "v1v8_audio"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -348,7 +350,7 @@ interrupts = ; }; - v3v3_hdmi: ldo2 { + secure_v3v3_hdmi: ldo2 { regulator-name = "v3v3_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -356,7 +358,7 @@ interrupts = ; }; - vtt_ddr: ldo3 { + secure_vtt_ddr: ldo3 { regulator-name = "vtt_ddr"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <750000>; @@ -364,12 +366,12 @@ regulator-over-current-protection; }; - vdd_usb: ldo4 { + secure_vdd_usb: ldo4 { regulator-name = "vdd_usb"; interrupts = ; }; - vdda: ldo5 { + secure_vdda: ldo5 { regulator-name = "vdda"; regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; @@ -377,7 +379,7 @@ regulator-boot-on; }; - v1v2_hdmi: ldo6 { + secure_v1v2_hdmi: ldo6 { regulator-name = "v1v2_hdmi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -385,22 +387,22 @@ interrupts = ; }; - vref_ddr: vref_ddr { + secure_vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; }; - bst_out: boost { + secure_bst_out: boost { regulator-name = "bst_out"; interrupts = ; }; - vbus_otg: pwr_sw1 { + secure_vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; }; - vbus_sw: pwr_sw2 { + secure_vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; regulator-active-discharge = <1>; @@ -543,6 +545,84 @@ }; }; +&scmi0_reguls { + vddcore: scmi-vddcore { + reg = ; + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vdd: scmi-vdd { + reg = ; + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v3v3: scmi-v3v3 { + reg = ; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v1v8_audio: scmi-v1v8-audio { + reg = ; + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + v3v3_hdmi: scmi-v3v3-hdmi { + reg = ; + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_usb: scmi-vdd-usb { + reg = ; + regulator-name = "vdd_usb"; + }; + + vdda: scmi-vdda { + reg = ; + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + }; + + v1v2_hdmi: scmi-v1v2-hdmi { + reg = ; + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + bst_out: scmi-bst-out { + reg = ; + regulator-name = "bst_out"; + }; + + vbus_otg: scmi-vbus-otg { + reg = ; + regulator-name = "vbus_otg"; + }; + + vbus_sw: scmi-vbus-sw { + reg = ; + regulator-name = "vbus_sw"; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; From patchwork Thu Nov 4 14:23:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 516812 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp1994811iml; Thu, 4 Nov 2021 07:25:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzub0tsaSlz8dsbZiVoiAlYPTI5Z7L2f9MGPeT718LYZLiR/AQuaP9rTgECb/AmZ4ncKjRW X-Received: by 2002:a50:e142:: with SMTP id i2mr67304707edl.159.1636035912901; Thu, 04 Nov 2021 07:25:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1636035912; cv=none; d=google.com; s=arc-20160816; b=qImn8eBSyISc4CGO2akwrGz+VOARFXgdNvviCr9tAB9YQMPAs8XdkM822YtccTAcTg jBJmvqZQmTTAuLM+P0Y0a34P3FzdjHoie/yxJ5l/EWP6DWbGnXmgtHXUej90GBbRTAsH 2PNcil4gD0beBI/APUWoKPGpIIHqk92/JyTTBBB8ifbaEBvKQBxJerl2lFwmxu2B3tyx tofM1iOGqXeIBKYEf1/YeWNOn1Aq7B0tmS8Rlb6lX0PnF4dgPBapRKqVJFZoGD1g1J6G kS+KwjUY7j4c9EeAskHahE7P82BM1t1HAPxSRpji0yhbHwNNQlzewgIjtz9a37hNdOjX z4zw== ARC-Message-Signature: i=1; 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Signed-off-by: Etienne Carriere --- arch/arm/dts/stm32mp151.dtsi | 5 +++-- arch/arm/dts/stm32mp157c-dk2.dts | 1 - arch/arm/dts/stm32mp157c-ed1.dts | 1 - 3 files changed, 3 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index cb6a14ec0c..6eaf3760bc 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -73,10 +73,11 @@ }; scmi0: scmi0 { - compatible = "linaro,scmi-optee"; + //compatible = "linaro,scmi-optee"; + compatible = "arm,scmi-smc"; #address-cells = <1>; #size-cells = <0>; - linaro,optee-channel-id = <0>; + //linaro,optee-channel-id = <0>; /* Supply properties for arm,scmi-smc compatible */ arm,smc-id = <0x82002000>; shmem = <&scmi0_shm>; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index fb9300fcb1..5f23dba3e3 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -105,6 +105,5 @@ }; &scmi0 { - compatible = "linaro,scmi-optee"; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index eabf00f1fe..26847b5c76 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -342,7 +342,6 @@ }; &scmi0 { - compatible = "linaro,scmi-optee"; status = "okay"; }; From patchwork Thu Nov 4 14:23:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 516816 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp1995648iml; Thu, 4 Nov 2021 07:25:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxRJlMD6RM5/9P+RmQGymmHJ1NfM/YlKxjy7SxXaYZBYVA0XUuImIU4n/NkqFdlSWvH45xt X-Received: by 2002:a05:6402:c18:: with SMTP id co24mr61652367edb.278.1636035956122; Thu, 04 Nov 2021 07:25:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1636035956; cv=none; d=google.com; s=arc-20160816; b=azNUd1kXR3Fjf1VoMJlRdEfw8I8HDWyfaLRQps0jAxWm9FEKQfthPBWAPe65ObE7+c kMGmXGGmeOuKVKoHG/hnEH/G/ypAihWE9eQHAF1Rdf5q1j5ROdUakCrctY5+czrFrEQw fid6BcHk0uffo5/fani1HZIHHmsj3yCDeDRCHrrD11FS7ElCx9Mv1UHh97TSFiAjZDyK LpDK4wpynDoGomc8Tq9NlmChvierIOVxzxJnQT3NVnt9BK0Og4fQA0RYgkMkl0yexfjX qAg0t4/+z9aKumIGRLCGi30UNJRdXN2TyXU53Rt0XANBN06SsX3pxWE+miocoMQN+5Me zriA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=p+ftTxl5c9r9quUZMgS5i4SPSYsKmoro2+VlePlRmxM=; b=vtzQx+NwZbNbLnhMijJsadnPQJZqP7aDSpWMs8uUjnM+AKwLP71eS3JPmIkNbWGIKw 60Tqb7Dc4YZhrRWoevv/Lm7dmnRgyD30d+O3gAulipe41cUsHPvGCFnO2Sz5507I3Upw pniuAisx21gmE2kZxA2/MfAvHY2AO5gVqk6/LPBOZKvCY8RcUfj7nyPeDfd0595bOAlz /VoxsSvwzGypThA/lbSSbjW1+LfUbIspv9RlXoesmMfJ/19Lovbl0HF0Bu6laoQ/cSBP KkOJwPzfGh9qR1t1uxpPknv6HZ0x3sqE6O5/dQzh9DTr5Drf7l7HObqlar15XY8vPoQM DGxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e5Zya2WT; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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When sending a message, the mailbox invokes the Cortex-A Arm Trustzone secure monitor with an SMC or HVC instruction providing a function identifier in register R0/X0 defined by the DTB. Signed-off-by: Etienne Carriere Signed-off-by: Etienne Carriere --- drivers/mailbox/Kconfig | 8 +++ drivers/mailbox/Makefile | 1 + drivers/mailbox/arm-smc-mbox.c | 123 +++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+) create mode 100644 drivers/mailbox/arm-smc-mbox.c -- 2.17.1 diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index dd4b0ac0c3..599d1df1ae 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -47,4 +47,12 @@ config ZYNQMP_IPI help This enables support for the Xilinx ZynqMP Inter Processor Interrupt communication controller. + +config ARM_SMC_MAILBOX + bool "Enable Arm SMC mailbox support" + depends on DM_MAILBOX && ARM_SMCCC + default y + help + Mailbox notification through an Arm SMC or HVC calls. + endmenu diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index d2ace8cd21..7a56a454b8 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -3,6 +3,7 @@ # Copyright (c) 2016, NVIDIA CORPORATION. # +obj-$(CONFIG_ARM_SMC_MAILBOX) += arm-smc-mbox.o obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o diff --git a/drivers/mailbox/arm-smc-mbox.c b/drivers/mailbox/arm-smc-mbox.c new file mode 100644 index 0000000000..d379da490a --- /dev/null +++ b/drivers/mailbox/arm-smc-mbox.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019, Linaro Limited + */ + +#define LOG_CATEGORY UCLASS_MAILBOX + +#include +#include +#include +#include +#include +#include +#include + +#define ARM_SMC_METHOD 0 +#define ARM_HVC_METHOD 1 + +typedef void (invoke_fn_t)(unsigned long); + +struct smc_pdata { + unsigned long func_id; + invoke_fn_t *invoke_fn; +}; + +/* Simple wrapper functions to be able to use a function pointer */ +static void smccc_smc(unsigned long a0) +{ + struct arm_smccc_res res; + + arm_smccc_smc(a0, 0, 0, 0, 0, 0, 0, 0, &res); +} + +static void smccc_hvc(unsigned long a0) +{ + struct arm_smccc_res res; + + arm_smccc_hvc(a0, 0, 0, 0, 0, 0, 0, 0, &res); +} + +static int smc_mbox_send(struct mbox_chan *chan, const void *data) +{ + struct smc_pdata *pdata = dev_get_plat(chan->dev); + + /* + * This mailbox invokes secure world for a channel event. + * Message is already in the channel's shared memory. + */ + pdata->invoke_fn(pdata->func_id); + + return 0; +} + +static int smc_mbox_recv(struct mbox_chan *chan, void *data) +{ + /* Mbox owner already got the return message from shared memory */ + return 0; +} + +static int smc_mbox_request(struct mbox_chan *chan) +{ + return 0; +} + +static int smc_mbox_rfree(struct mbox_chan *chan) +{ + return 0; +} + +static int smc_mbox_of_xlate(struct mbox_chan *chan, + struct ofnode_phandle_args *args) +{ + if (args->args_count) + dev_warn(chan->dev, "Expect no argument to smc-mbox cells\n"); + + chan->id = 0; + + return 0; +} + +static int smc_mbox_ofdata_to_platdata(struct udevice *dev) +{ + ulong compat_data = dev_get_driver_data(dev); + struct smc_pdata *pdata = dev_get_plat(dev); + u32 func_id; + + if (dev_read_u32(dev, "arm,func-id", &func_id)) { + dev_err(dev, "Missing property arm,func-id\n"); + return -EINVAL; + } + + pdata->func_id = func_id; + + if (compat_data == ARM_SMC_METHOD) + pdata->invoke_fn = smccc_smc; + else + pdata->invoke_fn = smccc_hvc; + + return 0; +} + +static const struct udevice_id smc_mbox_ids[] = { + { .compatible = "arm,smc-mbox", .data = ARM_SMC_METHOD, }, + { .compatible = "arm,hvc-mbox", .data = ARM_HVC_METHOD, }, + { } +}; + +struct mbox_ops smc_mbox_ops = { + .of_xlate = smc_mbox_of_xlate, + .request = smc_mbox_request, + .rfree = smc_mbox_rfree, + .send = smc_mbox_send, + .recv = smc_mbox_recv, +}; + +U_BOOT_DRIVER(smc_mbox) = { + .name = "arm_smc_mbox", + .id = UCLASS_MAILBOX, + .of_match = smc_mbox_ids, + .of_to_plat = smc_mbox_ofdata_to_platdata, + .plat_auto = sizeof(struct smc_pdata), + .ops = &smc_mbox_ops, +}; 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Thu, 04 Nov 2021 07:23:38 -0700 (PDT) Received: from lmecxl0524.lme.st.com ([2a04:cec0:10b3:52ee:40ee:3a6f:5eb8:bd35]) by smtp.gmail.com with ESMTPSA id m34sm9383297wms.25.2021.11.04.07.23.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Nov 2021 07:23:38 -0700 (PDT) From: Etienne Carriere To: u-boot@lists.denx.de Cc: Etienne Carriere Subject: [PATCH 13/14] [TEST] dts: stm32mp15: scmi mailbox transport Date: Thu, 4 Nov 2021 15:23:23 +0100 Message-Id: <20211104142324.2879-13-etienne.carriere@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104142324.2879-1-etienne.carriere@linaro.org> References: <20211104142324.2879-1-etienne.carriere@linaro.org> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Etienne Carriere --- arch/arm/dts/stm32mp15-u-boot.dtsi | 4 ++++ arch/arm/dts/stm32mp151.dtsi | 21 ++++++++++++++++----- 2 files changed, 20 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index 6fd204c635..d69b2df419 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -151,6 +151,10 @@ u-boot,dm-pre-reloc; }; +&scmi0_mbox { + u-boot,dm-pre-reloc; +}; + &scmi0_reset { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 6eaf3760bc..8fcce4aa2a 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -65,6 +65,12 @@ }; }; + scmi0_mbox: mailbox-0 { + #mbox-cells = <0>; + compatible = "arm,smc-mbox"; + arm,func-id = <0x82002000>; + }; + firmware { optee: optee { compatible = "linaro,optee-tz"; @@ -73,17 +79,22 @@ }; scmi0: scmi0 { - //compatible = "linaro,scmi-optee"; - compatible = "arm,scmi-smc"; #address-cells = <1>; #size-cells = <0>; - //linaro,optee-channel-id = <0>; - /* Supply properties for arm,scmi-smc compatible */ - arm,smc-id = <0x82002000>; shmem = <&scmi0_shm>; /* Enable only if stm32mp15x RCC[TZEN]=1 */ status = "disabled"; + //compatible = "linaro,scmi-optee"; + //linaro,optee-channel-id = <0>; + + //compatible = "arm,scmi-smc"; + //arm,smc-id = <0x82002000>; + + compatible = "arm,scmi"; + mboxes = <&scmi0_mbox>; + mbox-names = "txrx"; + scmi0_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>; From patchwork Thu Nov 4 14:23:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 516813 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp1994952iml; Thu, 4 Nov 2021 07:25:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyunagYdCCe7ZnbMLknC7NoX04f2wgXY+mz5ru3ApMx3MtPWb1jqCDJz39tSpZIyINL0VtU X-Received: by 2002:a17:907:d94:: with SMTP id go20mr3048932ejc.78.1636035922238; Thu, 04 Nov 2021 07:25:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1636035922; cv=none; d=google.com; s=arc-20160816; b=Cs+6LZf7ao7MXQeQSo2Py/OUjrDN4CjoRBBnrxRVkN3ZeDq7lq5HoJlBZyEDEcxv3V cCpxGaBbKQPSeTpSBthmP6jo7YwnVig3MLW5nRrXP3txVNLW4a1AkxCE1avqkQP0LUfy DSmeVho3+N3mJoxbCTTmcOmBm7YoK9gycsOcYU8KcEt/TU7qf3eSC+hAwZbHqC/4OKce BG42DUGQPAFSqULJuzKfRi+GUizOiMmHKb3ox58510Bo2UflLkbr6NH8rjwNCz4u0UQe 2ONIWh/jjcYg/ziVMLR2mQMk7jLy5B/7xi9lMEV3ON5N8QV7OaL9yJVOVATqbVbjZp9R p7Ug== ARC-Message-Signature: i=1; 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[85.214.62.61]) by mx.google.com with ESMTPS id b5si8377944ejb.4.2021.11.04.07.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Nov 2021 07:25:22 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JwIGXOtJ; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 437AD836E7; Thu, 4 Nov 2021 15:24:19 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="JwIGXOtJ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 329C7836EC; Thu, 4 Nov 2021 15:23:49 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 13198836E6 for ; Thu, 4 Nov 2021 15:23:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=etienne.carriere@linaro.org Received: by mail-wm1-x32c.google.com with SMTP id d72-20020a1c1d4b000000b00331140f3dc8so4418479wmd.1 for ; Thu, 04 Nov 2021 07:23:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VKiGdgMXVc/bC4naPpuxgPcaihEmojJ6kwF86j9MZ9s=; b=JwIGXOtJxZSjGICuHh/inmRYTkH9s+ZSzUaN3UR86nUAyfEidzv7B16icKTVWGuiKX GjkUb+NDeqQcH6e9uAV2LWQedG1IwjpIjb2N0DvmoXE8cN5sz3nePxK1isvxV6fTZCvy dGOlv7td/0MeNLsp8OqAycD8tWunmQm8ha/+kw7j6aLy5Gqqo9ZLvZUNRoL1JfhRoyca TOVhDTDp5c13P9cpEbCAeK0dGu9ZRL0+AW9vLSYYd0nbRWbuCYPB0gNpLrR2w8BKeND8 hXJXnYnzUSwG2a8Q3qxLmDhV1+m+owzRZiSqHhc0gqC5AO0MorpiOGUZoUEYakBSlvLU gz+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VKiGdgMXVc/bC4naPpuxgPcaihEmojJ6kwF86j9MZ9s=; b=vSo4+oVOqVyr69ab5mcKsXMchaJmyvKhHCARICw5FZP3Rr2l41GTDd8esp8fqRUE/3 4Gitdn5f950jBsI8tZaUcEtZ/dTIo/YpbED39sLqcvE91jgE3R7YSeTT5RMrFXuFYdnN OvUYPdGmnNnkJirWb3XcQXju9dZI2gDk+B+Ge2iZaNSJs3EM+hBYjvLIj59v2ydpq21f P5AFLSsVS3kFeB5afj7aglmo4qXbEaLq5jyljU8/FmhnqGq7Mt2UCvD0xUKF52uDzH0I uu7EjAc0Ibx1S2Hr+tM9Bucvf3ZImQpOGKHwbabBKbqEyfAKo8xEnNzZGROVkJjuE0Eh TTQg== X-Gm-Message-State: AOAM533zuLVKL1nlJyPSpCETfp/7idfW4ywMtoDZ6ZBVVzLCVyLl6gGd Mey3mrmeC4BwGCkIR7oQpDiJbyZ3eZ0aQw== X-Received: by 2002:a1c:27c3:: with SMTP id n186mr23726536wmn.192.1636035819453; Thu, 04 Nov 2021 07:23:39 -0700 (PDT) Received: from lmecxl0524.lme.st.com ([2a04:cec0:10b3:52ee:40ee:3a6f:5eb8:bd35]) by smtp.gmail.com with ESMTPSA id m34sm9383297wms.25.2021.11.04.07.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Nov 2021 07:23:39 -0700 (PDT) From: Etienne Carriere To: u-boot@lists.denx.de Cc: Etienne Carriere Subject: [PATCH 14/14] [HACK] configs: stm32mp15: enable earlyprintk Date: Thu, 4 Nov 2021 15:23:24 +0100 Message-Id: <20211104142324.2879-14-etienne.carriere@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104142324.2879-1-etienne.carriere@linaro.org> References: <20211104142324.2879-1-etienne.carriere@linaro.org> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Increase CONFIG_SYS_MALLOC_F_LEN for pre-reloc trace buffers and enable earlyprintk config for STM32. Change-Id: Ibcfcff1f0e6af7eb73b5c53c717bfc6ea20881af Signed-off-by: Etienne Carriere --- configs/stm32mp15_trusted_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index dc1f48c518..b5608bec42 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y CONFIG_TFABOOT=y -CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SYS_MALLOC_F_LEN=0x40000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_OFFSET=0x280000 @@ -159,3 +159,5 @@ CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 +CONFIG_DEBUG_UART_STM32=y +CONFIG_DEBUG_UART=y