From patchwork Sat May 27 06:33:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 100589 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp574133qge; Fri, 26 May 2017 23:33:21 -0700 (PDT) X-Received: by 10.99.103.68 with SMTP id b65mr6885965pgc.30.1495866801539; Fri, 26 May 2017 23:33:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495866801; cv=none; d=google.com; s=arc-20160816; b=Ug8Z2VvN4uYIikOD/NnBiB+dkjbt9bQbb+YEK37MCTik3YkkaALvdukTyMAZho6SIB KOPzZTgY47nz12nDwbKhyvwMil5dmHnP/lHlczw4btgBcgp4+WejNXuFdBZDV2P4d/oj i+Q4UgJn1QJ47fe1ZMx/3cfzDcMsjFyw4N3EMIqaPXXiaNZwFxUN6FigCsSL5xXCUppY LYdrj+pp6MCfLc5CNNj7OA9GTkK8hPaev/QdqyiFw1euhobcPmqF3hvMugwtVmfuTY3K P35ybV9xtxb3ln2RMhtApnZ/E/TJNhvlQM01UBOqiMZRyzqZFOZ8CkxVJtoV9pkxb50S Qktw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=qqJ/fQkQWSTraINIuroxXiylxZWcfEl2fbP1TblPWSQ=; b=dFQh7o0w+YGyWa/h/uxK4lvYL1wRmcDHCJfP0hnmTFmEhU9aZJbYFFnvam+B7o8PJa xiVqNXQgFcqNuy8rBtNMEiO6Y9AflASnuBd0ttAIPSF9PfOG7KJlFceM96VVl4V6JaGa Ai85quFWz9f4XEv+8fjx1kPNqwJWJu3FQGzBvXeQ00BEzVqMZdAt+uN35P8Shj2MJyIY ROPlk3ef7+Cd7J3eyVU27r0WM7wIxTqYk1OiSNeZOnehrXl17l4AOxyU8ij2e2tSBQSp yregwbJ7k28R5S504OWV1fOcZq9679jx50lGPuN3hk5wiie1plHqYETeqKftM1i3dMP3 w7RA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.111.223.48]) by smtp.gmail.com with ESMTPSA id g27sm5243346pfg.63.2017.05.26.23.33.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 May 2017 23:33:12 -0700 (PDT) From: Bjorn Andersson To: Andy Gross Cc: Stephen Boyd , Rob Herring , Mark Rutland , David Brown , Srinivas Kandagatla , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/3] firmware: qcom: scm: Expose secure IO service Date: Fri, 26 May 2017 23:33:06 -0700 Message-Id: <20170527063308.10483-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.12.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The secure IO service provides operations for reading and writing secure memory from non-secure mode, expose this API through SCM. Signed-off-by: Bjorn Andersson --- Changes since v1: - Correct scm-call return value handling - Make scm_io_readl() return data by reference drivers/firmware/qcom_scm-32.c | 18 ++++++++++++++++++ drivers/firmware/qcom_scm-64.c | 31 +++++++++++++++++++++++++++++++ drivers/firmware/qcom_scm.c | 12 ++++++++++++ drivers/firmware/qcom_scm.h | 6 ++++++ include/linux/qcom_scm.h | 4 ++++ 5 files changed, 71 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Stephen Boyd diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 93e3b96b6dfa..11fdb1584823 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -596,3 +596,21 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, { return -ENODEV; } + +int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, + unsigned int *val) +{ + int ret; + + ret = qcom_scm_call_atomic1(QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, addr); + if (ret >= 0) + *val = ret; + + return ret < 0 ? ret : 0; +} + +int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) +{ + return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE, + addr, val); +} diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 6e6d561708e2..bf50fb59852e 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -439,3 +439,34 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, return ret; } + +int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, + unsigned int *val) +{ + struct qcom_scm_desc desc = {0}; + struct arm_smccc_res res; + int ret; + + desc.args[0] = addr; + desc.arginfo = QCOM_SCM_ARGS(1); + + ret = qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, + &desc, &res); + if (ret >= 0) + *val = res.a1; + + return ret < 0 ? ret : 0; +} + +int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) +{ + struct qcom_scm_desc desc = {0}; + struct arm_smccc_res res; + + desc.args[0] = addr; + desc.args[1] = val; + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE, + &desc, &res); +} diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index bb16510d75ba..e18d63935648 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -333,6 +333,18 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) } EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init); +int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) +{ + return __qcom_scm_io_readl(__scm->dev, addr, val); +} +EXPORT_SYMBOL(qcom_scm_io_readl); + +int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) +{ + return __qcom_scm_io_writel(__scm->dev, addr, val); +} +EXPORT_SYMBOL(qcom_scm_io_writel); + /** * qcom_scm_is_available() - Checks if SCM is available */ diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 9bea691f30fb..a60e4b9b1394 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -30,6 +30,12 @@ extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus); #define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10 extern void __qcom_scm_cpu_power_down(u32 flags); +#define QCOM_SCM_SVC_IO 0x5 +#define QCOM_SCM_IO_READ 0x1 +#define QCOM_SCM_IO_WRITE 0x2 +extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val); +extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val); + #define QCOM_SCM_SVC_INFO 0x6 #define QCOM_IS_CALL_AVAIL_CMD 0x1 extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index e5380471c2cd..e8357f570695 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -43,6 +43,8 @@ extern int qcom_scm_set_remote_state(u32 state, u32 id); extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); +extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); +extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); #else static inline int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) @@ -73,5 +75,7 @@ qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; } static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; } static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; } static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; } +static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; } +static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; } #endif #endif From patchwork Sat May 27 06:33:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 100590 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp574202qge; 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[68.111.223.48]) by smtp.gmail.com with ESMTPSA id g27sm5243346pfg.63.2017.05.26.23.33.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 May 2017 23:33:15 -0700 (PDT) From: Bjorn Andersson To: Andy Gross Cc: Stephen Boyd , Rob Herring , Mark Rutland , David Brown , Srinivas Kandagatla , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/3] arm64: dts: qcom: Specify dload address for msm8916 and msm8996 Date: Fri, 26 May 2017 23:33:08 -0700 Message-Id: <20170527063308.10483-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170527063308.10483-1-bjorn.andersson@linaro.org> References: <20170527063308.10483-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On msm8916 and msm8996 boards a secure io-write is used to write the magic for selecting "download mode", specify this address in the DeviceTree. Note that qcom_scm.download_mode=1 must be specified on the kernel command line for the kernel to attempt selecting download mode. Signed-off-by: Bjorn Andersson --- Changes since v1: - Add msm8916 to the patch arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++ arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 ++ 2 files changed, 4 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index ab3093995ded..33013835639d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -241,6 +241,8 @@ clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; clock-names = "core", "bus", "iface"; #reset-cells = <1>; + + qcom,dload-mode-addr = <0x0 0x193d100>; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 9bc9c857a000..7e64884ab7c7 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -261,6 +261,8 @@ firmware { scm { compatible = "qcom,scm-msm8996"; + + qcom,dload-mode-addr = <0x0 0x7b3000>; }; };