From patchwork Thu Dec 2 15:37:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 520006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1172C43217 for ; Thu, 2 Dec 2021 15:35:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359041AbhLBPjH (ORCPT ); Thu, 2 Dec 2021 10:39:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347887AbhLBPjG (ORCPT ); Thu, 2 Dec 2021 10:39:06 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44F98C061758 for ; Thu, 2 Dec 2021 07:35:43 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id r9-20020a7bc089000000b00332f4abf43fso2928198wmh.0 for ; Thu, 02 Dec 2021 07:35:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q0TCZqUsV/OIZaKtPIfEAHhmhGteHpwoYWq5Gwb4DW8=; b=ZvKpOqDVar+z5isWT5ORUbVcqILDip7BT1fVgdEIj/p6Xn8TIHjYqV4+A9kjyiS0SJ uBSZIdpXRfPi/LQLcgPFUK1OxfEB1M8TGv+ct+7TPKHw4gAF4RA9R9Zxj05PVFz1Jvnu S10a8R6QAFb2FhKFGteizCjqFmaLWsP1hPGGZIXqyYN1+rPfXOpouwJ8D7g86tjSrqJ9 jiU4xt/KqNB83csduHK2ihqXo4WGjd2xigaydaKTUWxymgmFsiUxcO5T9e3731If00Ln YX+yGsbzY5KwtcFPqMTmstJ2kKGUu+ZWy/7XAnmxQ4bh4XslXJLKZ5hXIXRhPlQiSP2v bavA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q0TCZqUsV/OIZaKtPIfEAHhmhGteHpwoYWq5Gwb4DW8=; b=26k3IHdi6rCo/BN3V0gCwv14QNwuRjvGZmW+gX0JmpPmJta5scGDRcPoS7e8N2GREW e7CaWMuoidPkXseZ3NlXByuVdH4oomJAqa1bt9cIwJwPhBTW9BjagRfZId7kv/CsaSjV fDAC1YwY4RMSOTz+V90I0qmklKB5G21F6CKB+GvTOCG/CjLEeuRbi0QeNdwVleHco73z 8o4YHO+UOWZ1v7t9UY/iR+VSxelMi5e1kNgKAvvOiOSKbx3hDrvE9fNkrAGBF3u7MXcn up1U3nKH+KJcU/nrTTKo+UsHxsHGrbpjxan1luuxlFgtaZKrbA2jXJcwFpW5Y3m1gPsr CvVQ== X-Gm-Message-State: AOAM531hRkAmbHR/ipNejrIW7zgca02Hay2rg+T+LwiI52UW0LbWjw2F XewRcalkqQQrWmZxvKnP3yLFPuyeGyv8P03A X-Google-Smtp-Source: ABdhPJwIufOZNY2Pj7UFXSxzwL2hirPQMReAdTc37UkXXPnRGCAc2cEp+wxsMODg/5PfwM86cPXxcQ== X-Received: by 2002:a7b:cbd1:: with SMTP id n17mr7239291wmi.145.1638459341782; Thu, 02 Dec 2021 07:35:41 -0800 (PST) Received: from sagittarius-a.chello.ie (188-141-3-169.dynamic.upc.ie. [188.141.3.169]) by smtp.gmail.com with ESMTPSA id bd18sm3662wmb.43.2021.12.02.07.35.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Dec 2021 07:35:41 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, robert.foss@linaro.org, jonathan@marek.ca Cc: andrey.konovalov@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, jgrahsl@snap.com, hfink@snap.com, bryan.odonoghue@linaro.org, devicetree@vger.kernel.org Subject: [RESEND PATCH v2 01/19] media: dt-bindings: media: camss: Add qcom,sm8250-camss binding Date: Thu, 2 Dec 2021 15:37:11 +0000 Message-Id: <20211202153729.3362372-2-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> References: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jonathan Marek Add bindings for qcom,sm8250-camss in order to support the camera subsystem for SM8250. Cc: devicetree@vger.kernel.org Signed-off-by: Jonathan Marek Signed-off-by: Bryan O'Donoghue --- .../bindings/media/qcom,sm8250-camss.yaml | 450 ++++++++++++++++++ 1 file changed, 450 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml new file mode 100644 index 000000000000..af877d61b607 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml @@ -0,0 +1,450 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm CAMSS ISP + +maintainers: + - Robert Foss + +description: | + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm8250-camss + + clocks: + minItems: 37 + maxItems: 37 + + clock-names: + items: + - const: cam_ahb_clk + - const: cam_hf_axi + - const: cam_sf_axi + - const: camnoc_axi + - const: camnoc_axi_src + - const: core_ahb + - const: cpas_ahb + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: slow_ahb_src + - const: vfe0_ahb + - const: vfe0_axi + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe0_csid + - const: vfe0_areg + - const: vfe1_ahb + - const: vfe1_axi + - const: vfe1 + - const: vfe1_cphy_rx + - const: vfe1_csid + - const: vfe1_areg + - const: vfe_lite_ahb + - const: vfe_lite_axi + - const: vfe_lite + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + minItems: 14 + maxItems: 14 + + interrupt-names: + items: + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid3 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + + iommus: + minItems: 8 + maxItems: 8 + + interconnects: + minItems: 4 + maxItems: 4 + + interconnect-names: + items: + - const: cam_ahb + - const: cam_hf_0_mnoc + - const: cam_sf_0_mnoc + - const: cam_sf_icp_mnoc + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@4: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@5: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + reg: + minItems: 10 + maxItems: 10 + + reg-names: + items: + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + +required: + - clock-names + - clocks + - compatible + - interconnects + - interconnect-names + - interrupts + - interrupt-names + - iommus + - power-domains + - reg + - reg-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: camss@ac6a000 { + compatible = "qcom,sm8250-camss"; + + reg = <0 0xac6a000 0 0x2000>, + <0 0xac6c000 0 0x2000>, + <0 0xac6e000 0 0x1000>, + <0 0xac70000 0 0x1000>, + <0 0xac72000 0 0x1000>, + <0 0xac74000 0 0x1000>, + <0 0xacb4000 0 0xd000>, + <0 0xacc3000 0 0xd000>, + <0 0xacd9000 0 0x2200>, + <0 0xacdb200 0 0x2200>; + reg-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csid0", + "csid1", + "csid2", + "csid3", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_0_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_0_AREG_CLK>, + <&camcc CAM_CC_IFE_1_AHB_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_1_AREG_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_AXI_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "cam_ahb_clk", + "cam_hf_axi", + "cam_sf_axi", + "camnoc_axi", + "camnoc_axi_src", + "core_ahb", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "slow_ahb_src", + "vfe0_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe0_areg", + "vfe1_ahb", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe1_areg", + "vfe_lite_ahb", + "vfe_lite_axi", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + iommus = <&apps_smmu 0x800 0x400>, + <&apps_smmu 0x801 0x400>, + <&apps_smmu 0x840 0x400>, + <&apps_smmu 0x841 0x400>, + <&apps_smmu 0xC00 0x400>, + <&apps_smmu 0xC01 0x400>, + <&apps_smmu 0xC40 0x400>, + <&apps_smmu 0xC41 0x400>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, + <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "cam_ahb", + "cam_hf_0_mnoc", + "cam_sf_0_mnoc", + "cam_sf_icp_mnoc"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; From patchwork Thu Dec 2 15:37:14 2021 Content-Type: text/plain; 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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id bd18sm3662wmb.43.2021.12.02.07.35.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Dec 2021 07:35:44 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, robert.foss@linaro.org, jonathan@marek.ca Cc: andrey.konovalov@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, jgrahsl@snap.com, hfink@snap.com, bryan.odonoghue@linaro.org Subject: [RESEND PATCH v2 04/19] media: camss: csiphy-3ph: add support for SM8250 CSI DPHY Date: Thu, 2 Dec 2021 15:37:14 +0000 Message-Id: <20211202153729.3362372-5-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> References: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jonathan Marek Add support for CSIPHY (2PH/DPHY mode) found on SM8250 hardware. Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss Tested-by: Julian Grahsl Tested-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue --- .../qcom/camss/camss-csiphy-3ph-1-0.c | 147 ++++++++++++++++-- drivers/media/platform/qcom/camss/camss.h | 1 + 2 files changed, 139 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 783b65295d20..c5b0a91b36f8 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -62,6 +62,7 @@ struct csiphy_reg_t { u32 csiphy_param_type; }; +/* GEN2 1.0 2PH */ static const struct csiphy_reg_t lane_regs_sdm845[5][14] = { { @@ -146,6 +147,121 @@ csiphy_reg_t lane_regs_sdm845[5][14] = { }, }; +/* GEN2 1.2.1 2PH */ +static const struct +csiphy_reg_t lane_regs_sm8250[5][20] = { + { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + static void csiphy_hw_version_read(struct csiphy_device *csiphy, struct device *dev) { @@ -298,13 +414,25 @@ static void csiphy_gen1_config_lanes(struct csiphy_device *csiphy, static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, u8 settle_cnt) { - int i, l; + const struct csiphy_reg_t *r; + int i, l, array_size; u32 val; - for (l = 0; l < 5; l++) { - for (i = 0; i < 14; i++) { - const struct csiphy_reg_t *r = &lane_regs_sdm845[l][i]; + switch (csiphy->camss->version) { + case CAMSS_845: + r = &lane_regs_sdm845[0][0]; + array_size = ARRAY_SIZE(lane_regs_sdm845[0]); + break; + case CAMSS_8250: + r = &lane_regs_sm8250[0][0]; + array_size = ARRAY_SIZE(lane_regs_sm8250[0]); + break; + default: + unreachable(); + } + for (l = 0; l < 5; l++) { + for (i = 0; i < array_size; i++, r++) { switch (r->csiphy_param_type) { case CSIPHY_SETTLE_CNT_LOWER_BYTE: val = settle_cnt & 0xff; @@ -325,13 +453,15 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, s64 link_freq, u8 lane_mask) { struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; + bool is_gen2 = (csiphy->camss->version == CAMSS_845 || + csiphy->camss->version == CAMSS_8250); u8 settle_cnt; u8 val; int i; settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); - val = BIT(c->clk.pos); + val = is_gen2 ? BIT(7) : BIT(c->clk.pos); for (i = 0; i < c->num_data; i++) val |= BIT(c->data[i].pos * 2); @@ -346,11 +476,10 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, val = 0x00; writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); - if (csiphy->camss->version == CAMSS_8x16 || - csiphy->camss->version == CAMSS_8x96) - csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt); - else if (csiphy->camss->version == CAMSS_845) + if (is_gen2) csiphy_gen2_config_lanes(csiphy, settle_cnt); + else + csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt); /* IRQ_MASK registers - disable all interrupts */ for (i = 11; i < 22; i++) diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index dc8b4154f92b..377e2474a485 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -69,6 +69,7 @@ enum camss_version { CAMSS_8x96, CAMSS_660, CAMSS_845, + CAMSS_8250, }; struct camss { From patchwork Thu Dec 2 15:37:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 520004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84436C433EF for ; Thu, 2 Dec 2021 15:35:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359049AbhLBPjM (ORCPT ); Thu, 2 Dec 2021 10:39:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359052AbhLBPjL (ORCPT ); Thu, 2 Dec 2021 10:39:11 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA225C06174A for ; Thu, 2 Dec 2021 07:35:48 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id i5so60479028wrb.2 for ; Thu, 02 Dec 2021 07:35:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g6xr95bY7KJM6r6ZUUp3Xp8tqiGSbIaSx1KljDmxxqw=; b=jpg1IFQNoGuLiwNilu1teXwIqs46pSv7okEiWpdb3d6dlVv74DcbMXq7iUzjWI5N/8 v6TgoKkHqUQiTRXCuAMhjpYv4AA9pdthJjtOq6oPEU+ln1llpQXG3qvPNRbqEyWtARSM BtAqii29xJZQ0i6pe5ZT844wzJqu/bL71trNXgrzKhlDg2jC5/YTObp+EUbx0EnRlSJf x2lsin5SkNelEht8/2dyOs7AFAQlASKWRkcxS8dMSLzxaHpAMUEMEhUi+h5L6NW+p3JZ 7der8u4jmyYiri1uDp00P/Nh+tc323QtZI78Vhm4OvPELjoeIu/fZYCTURFodk1EJ2+A NUPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g6xr95bY7KJM6r6ZUUp3Xp8tqiGSbIaSx1KljDmxxqw=; b=AHr2gQqGt3OiNNfMFyAR99aX0YoD2j75fhdn7LEow1z2mhcPii802OrNEZHh+cdBEY CqGboIV9JQpEl/F/sdF6DGCiQNnS+CnNzmFX2BrRVGWWlRR+7SwxEzfKcMxLbe4telZ/ +icrQ1hpH+NU0R55UF7evc6bJc4uvHPhD6k6WWGO9ccTvtfOVjAGQXmla11No89Oll69 9r2M/7LeQVg69lJSBg14bmUgNmugk0oCjnhZEi/s9A4mVeJ9HbGKAyc6TBOQvDfptSDn J8koO0Ak7JCoLH3OwFMr08gsr+XbybBmDHRUij1CiPPaUbljkp9MYZReNqJrd6CDUM8t +Eng== X-Gm-Message-State: AOAM5334yKpWlBUPKYuqy1t9VLEa7GAHSUbBM5WLPjxHsq2zRCWyGNyl f/sLjWVEGjMw3tmaf1C9VdlQQtxw03Fa7nmp X-Google-Smtp-Source: ABdhPJxHLDYXtr6gDEfcoYXSX1xnzvEqHNaFqR9bv3fUU9dtYUON0HWwLgG1IHoiI6gI2KSxp3xlqA== X-Received: by 2002:adf:fb4f:: with SMTP id c15mr15436011wrs.507.1638459347389; Thu, 02 Dec 2021 07:35:47 -0800 (PST) Received: from sagittarius-a.chello.ie (188-141-3-169.dynamic.upc.ie. [188.141.3.169]) by smtp.gmail.com with ESMTPSA id bd18sm3662wmb.43.2021.12.02.07.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Dec 2021 07:35:47 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, robert.foss@linaro.org, jonathan@marek.ca Cc: andrey.konovalov@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, jgrahsl@snap.com, hfink@snap.com, bryan.odonoghue@linaro.org Subject: [RESEND PATCH v2 06/19] media: camss: csid-170: don't enable unused irqs Date: Thu, 2 Dec 2021 15:37:16 +0000 Message-Id: <20211202153729.3362372-7-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> References: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jonathan Marek csid_isr() only checks for the reset irq, so enabling any other irqs doesn't make sense. The "RDI irq" comment is also wrong, the register should be CSID_CSI2_RDIN_IRQ_MASK. Without this fix there may be an excessive amount of irqs. Fixes: eebe6d00e9bf ("media: camss: Add support for CSID hardware version Titan 170") Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss Tested-by: Julian Grahsl Tested-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss-csid-170.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid-170.c b/drivers/media/platform/qcom/camss/camss-csid-170.c index aa65043c3303..a006c8dbceb1 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-170.c +++ b/drivers/media/platform/qcom/camss/camss-csid-170.c @@ -444,12 +444,6 @@ static void csid_configure_stream(struct csid_device *csid, u8 enable) val |= 1 << CSI2_RX_CFG1_MISR_EN; writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1); // csi2_vc_mode_shift_val ? - /* error irqs start at BIT(11) */ - writel_relaxed(~0u, csid->base + CSID_CSI2_RX_IRQ_MASK); - - /* RDI irq */ - writel_relaxed(~0u, csid->base + CSID_TOP_IRQ_MASK); - val = 1 << RDI_CTRL_HALT_CMD; writel_relaxed(val, csid->base + CSID_RDI_CTRL(0)); } From patchwork Thu Dec 2 15:37:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 520003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68453C433FE for ; Thu, 2 Dec 2021 15:35:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233254AbhLBPjP (ORCPT ); Thu, 2 Dec 2021 10:39:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359061AbhLBPjN (ORCPT ); Thu, 2 Dec 2021 10:39:13 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0ACBFC06174A for ; Thu, 2 Dec 2021 07:35:51 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id d9so39652368wrw.4 for ; Thu, 02 Dec 2021 07:35:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=buYviz0EsUgobZTb1+UWjhyi7czeVNwVeTqZcQGLq9E=; b=WP/G16nYvYwVx321K3Tq1Wz0WLMeElSFSZTiVJdITyDfcTbKGA7hsob6eX5lVcJv77 tDgVf9EwBV7Ubr30zhtUov3tISzskOpDBfqP01lh1tOfCr35Q4L9ZTD7+06tWk7H4KS3 tI43FllkNu2bUIbvWRBwoeecu54adzW6bE9Jywo2aBkY+yLh27ckbXaxRw9iP5JqBaM3 KOP1mgUu8O2XcH6z2Bo5T7DjgPyy07HlmT2LdJe+QAmqvT/9yzgT+vxm+fW3jCWjjDTh y5nhmJHngWWvat1x92q9OdvdBHDOT5urPnVBWcbuqS9JX3fmy6Qh2ptiCWeJ3GJtGvuD Bixw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=buYviz0EsUgobZTb1+UWjhyi7czeVNwVeTqZcQGLq9E=; b=yEH/chIo2QhKzlvg4TkZ7vL4Pa/RKDwZAaN1nQ1yhe+9IUWiEvpU8U9HpvC83Y7fPh l5eo1VwDSXJYHjx0Dl9PrUL97V3S5GbvT9AIU+wOOaRdKi5wCBiBkC9OulkyXXKb1dlW MPtBpkCFWBhTdcoUWAV3Ip3c6yIwfz4gPJpAiStFiMGZScexQAxCORIV1IKs2Z7Fhau3 ktMF5Q3XGUksHCI48bW6CMl7dasesLXnfRPzNfgopZ0bRwurBpY41ANOj23wZcqC3iFt 0w1cCzQexfIxATj+MlzXzmqAlgWZn+wmapchshpRVPobjyfRjxvQbrPx7siT8sCWtTko B1jg== X-Gm-Message-State: AOAM5333jTQzQwY/t11JHRWBYQrQW3ZEMm8J3fUtSZIra6oB6kZgwpWM ufBDeHUvf3hutrSb/LxReXWbGw== X-Google-Smtp-Source: ABdhPJx4LuPssUtAQzFBiTiKROrkJrvqat90+HTsE4jPjBB7T1vp6Et2t+6r2T9Yl+nKI72vZge2vw== X-Received: by 2002:a5d:49c3:: with SMTP id t3mr15283010wrs.207.1638459349626; Thu, 02 Dec 2021 07:35:49 -0800 (PST) Received: from sagittarius-a.chello.ie (188-141-3-169.dynamic.upc.ie. [188.141.3.169]) by smtp.gmail.com with ESMTPSA id bd18sm3662wmb.43.2021.12.02.07.35.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Dec 2021 07:35:49 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, robert.foss@linaro.org, jonathan@marek.ca Cc: andrey.konovalov@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, jgrahsl@snap.com, hfink@snap.com, bryan.odonoghue@linaro.org Subject: [RESEND PATCH v2 08/19] media: camss: csid-170: support more than one lite vfe Date: Thu, 2 Dec 2021 15:37:18 +0000 Message-Id: <20211202153729.3362372-9-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> References: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jonathan Marek Change the IS_LITE condition so that it returns true for the second lite vfe found on titan 480 hardware (8250), which will have id == 3. Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss Tested-by: Julian Grahsl Tested-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss-csid-170.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid-170.c b/drivers/media/platform/qcom/camss/camss-csid-170.c index f0c6a72592f9..2c84d40fe3e0 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-170.c +++ b/drivers/media/platform/qcom/camss/camss-csid-170.c @@ -21,7 +21,7 @@ * interface support. As a result of that it has an * alternate register layout. */ -#define IS_LITE (csid->id == 2 ? 1 : 0) +#define IS_LITE (csid->id >= 2 ? 1 : 0) #define CSID_HW_VERSION 0x0 #define HW_VERSION_STEPPING 0 From patchwork Thu Dec 2 15:37:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 520002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49E55C433FE for ; Thu, 2 Dec 2021 15:35:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359070AbhLBPjR (ORCPT ); Thu, 2 Dec 2021 10:39:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359068AbhLBPjP (ORCPT ); Thu, 2 Dec 2021 10:39:15 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25B96C06174A for ; Thu, 2 Dec 2021 07:35:53 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id d24so60590344wra.0 for ; Thu, 02 Dec 2021 07:35:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nltQSFm14iSoAMbvdkFyYA24qQ389OopP2NKU0dRRk4=; b=zwl5Ep3jlqggtOD2HbIQx5FL9JDlZXvVZfMQtiUsvzw+jQHf4jUhqfRGof5MBzqy1b GTyA8IU9zUaVOt6oz1D8PB350U+QAsQos6yNS/eZU6tRWQ+WcL6l/2utn1YKccQLcz5N c1Iop26GQCT7FsWFY0IGjP9yDEQUJV6oHBMfprl+TE3eZYfImR8Od1xHlcA6+ReUvW4B 1a3Yr6CNMC3TD5JiEjEKFyAy+lVdTFGJ2x0uGkWyoUYWlvh10PCBjxF8ssLJ+yIfsTYd FyOmti1/NlmWNdYOOwAX/FGls0Jv1LI7zvUf8dSFUENPTwLj3JqQbG0ZuLMNQ/a0hTUw XcTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nltQSFm14iSoAMbvdkFyYA24qQ389OopP2NKU0dRRk4=; b=NZkzNcVcx/UXNwwEHuNbzkGGKw36bmJLtb+czQEo/HPnR3SXI7nBtU6pJjkAHEXuEa nbiO2LEaCXs6Rl/bwqNAU9YzpjAxgnElV+tr9Q81wqPNMtQdHVW/qTZ7ei1Uvej/zUFI 2ReRNlyCg9agoAWHg8X/apORM3I7gihA48TMOchbFwGR/sbJDTlDgKqVMG4KPzjjKxB5 87PFIAfhHt18yZvPPBEtWCqCXpPIP2sakSMEr/dIzWRkSc6uOaBg4o+9rNPLvVE4OmPF 9dP8XEpYS6emplg6/MMG4A8P/H/ZEqqaviY2xTWQpJFlo6UDq8aIVCjia6tbLuMsV6Na MkmA== X-Gm-Message-State: AOAM533F19UmyYbH89pfX7B5y5w0bpX9U0ek8bYy+ScOU3B9Tu29hrw/ SdVI1NLGwvIeda6bZS0YlAKX7g== X-Google-Smtp-Source: ABdhPJyylTxFMNTBGC+X2JZhW8gOkej7tFVAn4lrLaHytTcldSH40AOSBiTkYLrs5VK7NAG8ZF1gKg== X-Received: by 2002:a5d:468f:: with SMTP id u15mr15066154wrq.171.1638459351741; Thu, 02 Dec 2021 07:35:51 -0800 (PST) Received: from sagittarius-a.chello.ie (188-141-3-169.dynamic.upc.ie. [188.141.3.169]) by smtp.gmail.com with ESMTPSA id bd18sm3662wmb.43.2021.12.02.07.35.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Dec 2021 07:35:51 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, robert.foss@linaro.org, jonathan@marek.ca Cc: andrey.konovalov@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, jgrahsl@snap.com, hfink@snap.com, bryan.odonoghue@linaro.org Subject: [RESEND PATCH v2 10/19] media: camss: csid: allow csid to work without a regulator Date: Thu, 2 Dec 2021 15:37:20 +0000 Message-Id: <20211202153729.3362372-11-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> References: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jonathan Marek At least for titan HW, CSID don't have an associated regulator. This change is necessary to be able to model this in the CSID resources. Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss Tested-by: Julian Grahsl Tested-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss-csid.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index a1637b78568b..1226913c623b 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -160,7 +160,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) if (ret < 0) return ret; - ret = regulator_enable(csid->vdda); + ret = csid->vdda ? regulator_enable(csid->vdda) : 0; if (ret < 0) { pm_runtime_put_sync(dev); return ret; @@ -168,14 +168,16 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) ret = csid_set_clock_rates(csid); if (ret < 0) { - regulator_disable(csid->vdda); + if (csid->vdda) + regulator_disable(csid->vdda); pm_runtime_put_sync(dev); return ret; } ret = camss_enable_clocks(csid->nclocks, csid->clock, dev); if (ret < 0) { - regulator_disable(csid->vdda); + if (csid->vdda) + regulator_disable(csid->vdda); pm_runtime_put_sync(dev); return ret; } @@ -186,7 +188,8 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) if (ret < 0) { disable_irq(csid->irq); camss_disable_clocks(csid->nclocks, csid->clock); - regulator_disable(csid->vdda); + if (csid->vdda) + regulator_disable(csid->vdda); pm_runtime_put_sync(dev); return ret; } @@ -195,7 +198,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) } else { disable_irq(csid->irq); camss_disable_clocks(csid->nclocks, csid->clock); - ret = regulator_disable(csid->vdda); + ret = csid->vdda ? regulator_disable(csid->vdda) : 0; pm_runtime_put_sync(dev); } @@ -631,7 +634,9 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, /* Regulator */ - csid->vdda = devm_regulator_get(dev, res->regulator[0]); + csid->vdda = NULL; + if (res->regulator[0]) + csid->vdda = devm_regulator_get(dev, res->regulator[0]); if (IS_ERR(csid->vdda)) { dev_err(dev, "could not get regulator\n"); return PTR_ERR(csid->vdda); From patchwork Thu Dec 2 15:37:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 520001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1A87C433EF for ; Thu, 2 Dec 2021 15:35:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359080AbhLBPjT (ORCPT ); Thu, 2 Dec 2021 10:39:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359067AbhLBPjS (ORCPT ); Thu, 2 Dec 2021 10:39:18 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45D45C06174A for ; Thu, 2 Dec 2021 07:35:55 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id q3so37611954wru.5 for ; Thu, 02 Dec 2021 07:35:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4rv/fyUIkZmcgUL4jWnd5ZJeQoQ3nVOUW2jLjnzBt8o=; b=qB4wRdgN1wDHIxQ4lxLDY6ooYNKGghkt7HHr71C2fFf5FOLr1P5OdYbMNw/eThwK92 Bh+AYwksSq/5y76g9fuE69TIwYNV/7URXpwoRmmS792SlUve++AO42zD4zdA9Gbg8Pd8 So5gIPJ9QS5q/MSdI3hRawZHt9rmLmqtrkk2VfWjwGk5SCX7xiPl1xCtDLKxr2o2EufJ ldxrGsuFe/udOxfy0hfaZB1zWCGQwTb1Fmzmp1vmCp4c3nN0oU0XGGb7a6/yh2biRFlI D9BzWQSJ+66gCbn/YhIZbw4Oa1eSoQPbge+TkG1GGu/3RFfCHEe9IyGYhAnjiJh0/aPd VQDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4rv/fyUIkZmcgUL4jWnd5ZJeQoQ3nVOUW2jLjnzBt8o=; b=2PAhcHPifqZN06mivIvJTMRjMQK8HJQghYLoOdTHoa787VebJjQNDPppoN1C0/7Llx 7JYn50UuibX6odVUJkxRkmhjemR9m4dxvzJqW9tRcW9atQPAOZSc80IgyseMQlMnG/MT ZYQA25v/NmUQH5+axhrk55OX7F9wblzLAZLz6mBd10E7c6M2aIYODg5FTzZi9a3OyUwg pi5sc9qNfVdYTvb8cxuu2hBF9YPh4p+0y933p19yC7Z5j0Wd7C+toIi+ENJZet6yKiJn nvvzNGQZpzOXzpbspgMkof620A0uAXb5EXlIlzxI8ZBMYCLFlytdEWrNENWieFRrx4hp Ft5A== X-Gm-Message-State: AOAM531+gYE06EhVUFM51MCaUhyjoboMerwHf8o9j8yzi9wOvRbAauZd EM0NJdVLnhx7ZH4eNgOgcvi0/g== X-Google-Smtp-Source: ABdhPJwXyGW/c1ON9gIyLRYmizCqx9vd6q4BAOMeRIO5q9uB5fEPGgCDMbH/4CT+NX6UzQp2Ucxz8Q== X-Received: by 2002:a5d:59a2:: with SMTP id p2mr15198316wrr.252.1638459353896; Thu, 02 Dec 2021 07:35:53 -0800 (PST) Received: from sagittarius-a.chello.ie (188-141-3-169.dynamic.upc.ie. [188.141.3.169]) by smtp.gmail.com with ESMTPSA id bd18sm3662wmb.43.2021.12.02.07.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Dec 2021 07:35:53 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, robert.foss@linaro.org, jonathan@marek.ca Cc: andrey.konovalov@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, jgrahsl@snap.com, hfink@snap.com, bryan.odonoghue@linaro.org Subject: [RESEND PATCH v2 12/19] media: camss: fix VFE irq name Date: Thu, 2 Dec 2021 15:37:22 +0000 Message-Id: <20211202153729.3362372-13-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> References: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jonathan Marek vfe->id isn't set yet, so use "id" instead here. Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss Tested-by: Julian Grahsl Tested-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss-vfe.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 71f78b40e7f5..165b404761db 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -1293,7 +1293,6 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe, case CAMSS_660: vfe->ops = &vfe_ops_4_8; break; - case CAMSS_845: vfe->ops = &vfe_ops_170; break; @@ -1321,7 +1320,7 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe, vfe->irq = r->start; snprintf(vfe->irq_name, sizeof(vfe->irq_name), "%s_%s%d", - dev_name(dev), MSM_VFE_NAME, vfe->id); + dev_name(dev), MSM_VFE_NAME, id); ret = devm_request_irq(dev, vfe->irq, vfe->ops->isr, IRQF_TRIGGER_RISING, vfe->irq_name, vfe); if (ret < 0) { From patchwork Thu Dec 2 15:37:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 520000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 694ACC433EF for ; Thu, 2 Dec 2021 15:36:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359089AbhLBPjW (ORCPT ); Thu, 2 Dec 2021 10:39:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359073AbhLBPjU (ORCPT ); Thu, 2 Dec 2021 10:39:20 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFDD4C061757 for ; Thu, 2 Dec 2021 07:35:57 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id s13so60532374wrb.3 for ; Thu, 02 Dec 2021 07:35:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W375PjxodEzMCvf0sE1R6X6POVIILHpLPZlaAy/T4Zs=; b=Q8+8Vq2MoIzWfZKfTRUGOF7W+o/fsPrm5UnD6O6w9fo52cWEqbluSYuvNePrvg1Oxs vkseEutQ7mTMrY0VoyRn6mBSpBSeAwq5WOk7DbrbGdxQ5nmtfP5Aeq4imKNmcGUhc0bl MaxBxr9FtMtg+FmzEXz4GscNntARvFJO0RnkBZXz9ctRsaEFaTpf4XBOPk6BuNellj1Y ZN+ppLBWIdmF+wG3BoDSnxbwi4mdHygk4cV+Dcoky6yNaUNGV9VHjdpehzSUM6xFX3JZ kYgwxSRtlH47Ft1et3SrOnsBqDN+gPpJ1BECcL1FiVwNb397aWHB9sq57Lufd7gAjkJO 1kYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W375PjxodEzMCvf0sE1R6X6POVIILHpLPZlaAy/T4Zs=; b=ebIgehIa0Ch12BBKt+qnL3MTh+NPLpl8fuv4fK7LzsgrQ4Lm7D6pDdUl/TCS9UpE+h Q8uBwP9iNLrutA90g5XfzriC3keOxW8mHeAn6A8o9Q9ytxw+wSzE4k/6oVzzICMQFXsf 9I5W6k+DW5qf2SWKpiTz2BtLF0Grbet4SoTM5AFy5Ldz7S0dh61kEMtM+ROuFb1CO+/Q RnR0wjWtPGyfK7+7V0NmjQjGlKibMxuxztiWJ1MksKqQ+MzBWCBNPzXsiT/rkPoJwxTG H88vGoMEDb7OniFPboOmYVRjrTeCrrSdbljPXCgNdkW2q5dOn33nS2mHrjswfkP1h423 saDQ== X-Gm-Message-State: AOAM530AYiN8yx5OsEwjYXvfhhllc4OcDrARdDYWf1r/cxFwun4YTehD h7cdXPgqRrCMzlEZFsRsDPikWg== X-Google-Smtp-Source: ABdhPJwde781AA7UqzYo3vGTXxY4Aaop/v9dQI/JbwqSJbXUZ7mxkxU80+VjdZwXCryS0Zubj2DDmA== X-Received: by 2002:a5d:6151:: with SMTP id y17mr15355108wrt.275.1638459356297; Thu, 02 Dec 2021 07:35:56 -0800 (PST) Received: from sagittarius-a.chello.ie (188-141-3-169.dynamic.upc.ie. [188.141.3.169]) by smtp.gmail.com with ESMTPSA id bd18sm3662wmb.43.2021.12.02.07.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Dec 2021 07:35:55 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, robert.foss@linaro.org, jonathan@marek.ca Cc: andrey.konovalov@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, jgrahsl@snap.com, hfink@snap.com, bryan.odonoghue@linaro.org Subject: [RESEND PATCH v2 14/19] media: camss: Add initial support for VFE hardware version Titan 480 Date: Thu, 2 Dec 2021 15:37:24 +0000 Message-Id: <20211202153729.3362372-15-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> References: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jonathan Marek Add support for VFE found on SM8250 (Titan 480). This implementation is based on the titan 170 implementation. It supports the normal and lite VFE, and only supports the RDI0 capture path. [bod: Updates hw_version callback] [bod: Use static inline for macros reusing parameters checkpatch --strict] Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss Tested-by: Julian Grahsl Tested-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/Makefile | 1 + .../media/platform/qcom/camss/camss-vfe-480.c | 564 ++++++++++++++++++ drivers/media/platform/qcom/camss/camss-vfe.h | 1 + 3 files changed, 566 insertions(+) create mode 100644 drivers/media/platform/qcom/camss/camss-vfe-480.c diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index 0752c46ea37b..81dd56aff0f2 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -15,6 +15,7 @@ qcom-camss-objs += \ camss-vfe-4-7.o \ camss-vfe-4-8.o \ camss-vfe-170.o \ + camss-vfe-480.o \ camss-vfe-gen1.o \ camss-vfe.o \ camss-video.o \ diff --git a/drivers/media/platform/qcom/camss/camss-vfe-480.c b/drivers/media/platform/qcom/camss/camss-vfe-480.c new file mode 100644 index 000000000000..129585110393 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-vfe-480.c @@ -0,0 +1,564 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-vfe-480.c + * + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v480 (SM8250) + * + * Copyright (C) 2020-2021 Linaro Ltd. + * Copyright (C) 2021 Jonathan Marek + */ + +#include +#include +#include +#include + +#include "camss.h" +#include "camss-vfe.h" + +/* VFE 2/3 are lite and have a different register layout */ +#define IS_LITE (vfe->id >= 2 ? 1 : 0) + +#define VFE_HW_VERSION (0x00) + +#define VFE_GLOBAL_RESET_CMD (IS_LITE ? 0x0c : 0x1c) +#define GLOBAL_RESET_HW_AND_REG (IS_LITE ? BIT(1) : BIT(0)) + +#define VFE_REG_UPDATE_CMD (IS_LITE ? 0x20 : 0x34) +static inline int reg_update_rdi(struct vfe_device *vfe, int n) +{ + return IS_LITE ? BIT(n) : BIT(1 + (n)); +} + +#define REG_UPDATE_RDI reg_update_rdi +#define VFE_IRQ_CMD (IS_LITE ? 0x24 : 0x38) +#define IRQ_CMD_GLOBAL_CLEAR BIT(0) + +#define VFE_IRQ_MASK(n) ((IS_LITE ? 0x28 : 0x3c) + (n) * 4) +#define IRQ_MASK_0_RESET_ACK (IS_LITE ? BIT(17) : BIT(0)) +#define IRQ_MASK_0_BUS_TOP_IRQ (IS_LITE ? BIT(4) : BIT(7)) +#define VFE_IRQ_CLEAR(n) ((IS_LITE ? 0x34 : 0x48) + (n) * 4) +#define VFE_IRQ_STATUS(n) ((IS_LITE ? 0x40 : 0x54) + (n) * 4) + +#define BUS_REG_BASE (IS_LITE ? 0x1a00 : 0xaa00) + +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) +#define WM_CGC_OVERRIDE_ALL (0x3FFFFFF) + +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xdc) + +#define VFE_BUS_IRQ_MASK(n) (BUS_REG_BASE + 0x18 + (n) * 4) +static inline int bus_irq_mask_0_rdi_rup(struct vfe_device *vfe, int n) +{ + return IS_LITE ? BIT(n) : BIT(3 + (n)); +} + +#define BUS_IRQ_MASK_0_RDI_RUP bus_irq_mask_0_rdi_rup +static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n) +{ + return IS_LITE ? BIT(4 + (n)) : BIT(6 + (n)); +} + +#define BUS_IRQ_MASK_0_COMP_DONE bus_irq_mask_0_comp_done +#define VFE_BUS_IRQ_CLEAR(n) (BUS_REG_BASE + 0x20 + (n) * 4) +#define VFE_BUS_IRQ_STATUS(n) (BUS_REG_BASE + 0x28 + (n) * 4) +#define VFE_BUS_IRQ_CLEAR_GLOBAL (BUS_REG_BASE + 0x30) + +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) +#define WM_CFG_EN (0) +#define WM_CFG_MODE (16) +#define MODE_QCOM_PLAIN (0) +#define MODE_MIPI_RAW (1) +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100) +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100) +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100) +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) +#define VFE_BUS_WM_IMAGE_CFG_1(n) (BUS_REG_BASE + 0x210 + (n) * 0x100) +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100) +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100) +#define VFE_BUS_WM_HEADER_ADDR(n) (BUS_REG_BASE + 0x220 + (n) * 0x100) +#define VFE_BUS_WM_HEADER_INCR(n) (BUS_REG_BASE + 0x224 + (n) * 0x100) +#define VFE_BUS_WM_HEADER_CFG(n) (BUS_REG_BASE + 0x228 + (n) * 0x100) + +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100) +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100) +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100) +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100) + +#define VFE_BUS_WM_SYSTEM_CACHE_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100) +#define VFE_BUS_WM_BURST_LIMIT(n) (BUS_REG_BASE + 0x264 + (n) * 0x100) + +/* for titan 480, each bus client is hardcoded to a specific path + * and each bus client is part of a hardcoded "comp group" + */ +#define RDI_WM(n) ((IS_LITE ? 0 : 23) + (n)) +#define RDI_COMP_GROUP(n) ((IS_LITE ? 0 : 11) + (n)) + +static u32 vfe_hw_version(struct vfe_device *vfe) +{ + u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION); + + u32 gen = (hw_version >> 28) & 0xF; + u32 rev = (hw_version >> 16) & 0xFFF; + u32 step = hw_version & 0xFFFF; + + dev_dbg(vfe->camss->dev, "VFE HW Version = %u.%u.%u\n", gen, rev, step); + + return hw_version; +} + +static void vfe_global_reset(struct vfe_device *vfe) +{ + writel_relaxed(IRQ_MASK_0_RESET_ACK, vfe->base + VFE_IRQ_MASK(0)); + writel_relaxed(GLOBAL_RESET_HW_AND_REG, vfe->base + VFE_GLOBAL_RESET_CMD); +} + +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) +{ + struct v4l2_pix_format_mplane *pix = + &line->video_out.active_fmt.fmt.pix_mp; + + wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ + + /* no clock gating at bus input */ + writel_relaxed(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); + + writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); + + writel_relaxed(pix->plane_fmt[0].bytesperline * pix->height, + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); + writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm)); + writel_relaxed(WM_IMAGE_CFG_0_DEFAULT_WIDTH, + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); + writel_relaxed(pix->plane_fmt[0].bytesperline, + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); + writel_relaxed(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); + + /* no dropped frames, one irq per frame */ + writel_relaxed(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); + writel_relaxed(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); + writel_relaxed(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); + writel_relaxed(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); + + writel_relaxed(1 << WM_CFG_EN | MODE_MIPI_RAW << WM_CFG_MODE, + vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) +{ + wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ + writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, + struct vfe_line *line) +{ + wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ + writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); +} + +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) +{ + vfe->reg_update |= REG_UPDATE_RDI(vfe, line_id); + writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD); +} + +static inline void vfe_reg_update_clear(struct vfe_device *vfe, + enum vfe_line_id line_id) +{ + vfe->reg_update &= ~REG_UPDATE_RDI(vfe, line_id); +} + +static void vfe_enable_irq_common(struct vfe_device *vfe) +{ + /* enable only the IRQs used: rup and comp_done irqs for RDI0 */ + writel_relaxed(IRQ_MASK_0_RESET_ACK | IRQ_MASK_0_BUS_TOP_IRQ, + vfe->base + VFE_IRQ_MASK(0)); + writel_relaxed(BUS_IRQ_MASK_0_RDI_RUP(vfe, 0) | + BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(0)), + vfe->base + VFE_BUS_IRQ_MASK(0)); +} + +static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id); +static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm); + +/* + * vfe_isr - VFE module interrupt handler + * @irq: Interrupt line + * @dev: VFE device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t vfe_isr(int irq, void *dev) +{ + struct vfe_device *vfe = dev; + u32 status; + + status = readl_relaxed(vfe->base + VFE_IRQ_STATUS(0)); + writel_relaxed(status, vfe->base + VFE_IRQ_CLEAR(0)); + writel_relaxed(IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD); + + if (status & IRQ_MASK_0_RESET_ACK) + vfe_isr_reset_ack(vfe); + + if (status & IRQ_MASK_0_BUS_TOP_IRQ) { + u32 status = readl_relaxed(vfe->base + VFE_BUS_IRQ_STATUS(0)); + + writel_relaxed(status, vfe->base + VFE_BUS_IRQ_CLEAR(0)); + writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL); + + if (status & BUS_IRQ_MASK_0_RDI_RUP(vfe, 0)) + vfe_isr_reg_update(vfe, 0); + + if (status & BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(0))) + vfe_isr_wm_done(vfe, 0); + } + + return IRQ_HANDLED; +} + +/* + * vfe_halt - Trigger halt on VFE module and wait to complete + * @vfe: VFE device + * + * Return 0 on success or a negative error code otherwise + */ +static int vfe_halt(struct vfe_device *vfe) +{ + /* rely on vfe_disable_output() to stop the VFE */ + return 0; +} + +static int vfe_get_output(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + struct vfe_output *output; + unsigned long flags; + int wm_idx; + + spin_lock_irqsave(&vfe->output_lock, flags); + + output = &line->output; + if (output->state != VFE_OUTPUT_OFF) { + dev_err(vfe->camss->dev, "Output is running\n"); + goto error; + } + + output->wm_num = 1; + + wm_idx = vfe_reserve_wm(vfe, line->id); + if (wm_idx < 0) { + dev_err(vfe->camss->dev, "Can not reserve wm\n"); + goto error_get_wm; + } + output->wm_idx[0] = wm_idx; + + output->drop_update_idx = 0; + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return 0; + +error_get_wm: + vfe_release_wm(vfe, output->wm_idx[0]); + output->state = VFE_OUTPUT_OFF; +error: + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return -EINVAL; +} + +static int vfe_enable_output(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + struct vfe_output *output = &line->output; + unsigned long flags; + unsigned int i; + + spin_lock_irqsave(&vfe->output_lock, flags); + + vfe_reg_update_clear(vfe, line->id); + + if (output->state != VFE_OUTPUT_OFF) { + dev_err(vfe->camss->dev, "Output is not in reserved state %d\n", + output->state); + spin_unlock_irqrestore(&vfe->output_lock, flags); + return -EINVAL; + } + + WARN_ON(output->gen2.active_num); + + output->state = VFE_OUTPUT_ON; + + output->sequence = 0; + output->wait_reg_update = 0; + reinit_completion(&output->reg_update); + + vfe_wm_start(vfe, output->wm_idx[0], line); + + for (i = 0; i < 2; i++) { + output->buf[i] = vfe_buf_get_pending(output); + if (!output->buf[i]) + break; + output->gen2.active_num++; + vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); + } + + vfe_reg_update(vfe, line->id); + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return 0; +} + +static int vfe_disable_output(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + struct vfe_output *output = &line->output; + unsigned long flags; + unsigned int i; + bool done; + int timeout = 0; + + do { + spin_lock_irqsave(&vfe->output_lock, flags); + done = !output->gen2.active_num; + spin_unlock_irqrestore(&vfe->output_lock, flags); + usleep_range(10000, 20000); + + if (timeout++ == 100) { + dev_err(vfe->camss->dev, "VFE idle timeout - resetting\n"); + vfe_reset(vfe); + output->gen2.active_num = 0; + return 0; + } + } while (!done); + + spin_lock_irqsave(&vfe->output_lock, flags); + for (i = 0; i < output->wm_num; i++) + vfe_wm_stop(vfe, output->wm_idx[i]); + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return 0; +} + +/* + * vfe_enable - Enable streaming on VFE line + * @line: VFE line + * + * Return 0 on success or a negative error code otherwise + */ +static int vfe_enable(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + int ret; + + mutex_lock(&vfe->stream_lock); + + if (!vfe->stream_count) + vfe_enable_irq_common(vfe); + + vfe->stream_count++; + + mutex_unlock(&vfe->stream_lock); + + ret = vfe_get_output(line); + if (ret < 0) + goto error_get_output; + + ret = vfe_enable_output(line); + if (ret < 0) + goto error_enable_output; + + vfe->was_streaming = 1; + + return 0; + +error_enable_output: + vfe_put_output(line); + +error_get_output: + mutex_lock(&vfe->stream_lock); + + vfe->stream_count--; + + mutex_unlock(&vfe->stream_lock); + + return ret; +} + +/* + * vfe_disable - Disable streaming on VFE line + * @line: VFE line + * + * Return 0 on success or a negative error code otherwise + */ +static int vfe_disable(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + + vfe_disable_output(line); + + vfe_put_output(line); + + mutex_lock(&vfe->stream_lock); + + vfe->stream_count--; + + mutex_unlock(&vfe->stream_lock); + + return 0; +} + +/* + * vfe_isr_reg_update - Process reg update interrupt + * @vfe: VFE Device + * @line_id: VFE line + */ +static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) +{ + struct vfe_output *output; + unsigned long flags; + + spin_lock_irqsave(&vfe->output_lock, flags); + vfe_reg_update_clear(vfe, line_id); + + output = &vfe->line[line_id].output; + + if (output->wait_reg_update) { + output->wait_reg_update = 0; + complete(&output->reg_update); + } + + spin_unlock_irqrestore(&vfe->output_lock, flags); +} + +/* + * vfe_isr_wm_done - Process write master done interrupt + * @vfe: VFE Device + * @wm: Write master id + */ +static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm) +{ + struct vfe_line *line = &vfe->line[vfe->wm_output_map[wm]]; + struct camss_buffer *ready_buf; + struct vfe_output *output; + unsigned long flags; + u32 index; + u64 ts = ktime_get_ns(); + + spin_lock_irqsave(&vfe->output_lock, flags); + + if (vfe->wm_output_map[wm] == VFE_LINE_NONE) { + dev_err_ratelimited(vfe->camss->dev, + "Received wm done for unmapped index\n"); + goto out_unlock; + } + output = &vfe->line[vfe->wm_output_map[wm]].output; + + ready_buf = output->buf[0]; + if (!ready_buf) { + dev_err_ratelimited(vfe->camss->dev, + "Missing ready buf %d!\n", output->state); + goto out_unlock; + } + + ready_buf->vb.vb2_buf.timestamp = ts; + ready_buf->vb.sequence = output->sequence++; + + index = 0; + output->buf[0] = output->buf[1]; + if (output->buf[0]) + index = 1; + + output->buf[index] = vfe_buf_get_pending(output); + + if (output->buf[index]) + vfe_wm_update(vfe, output->wm_idx[0], output->buf[index]->addr[0], line); + else + output->gen2.active_num--; + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + + return; + +out_unlock: + spin_unlock_irqrestore(&vfe->output_lock, flags); +} + +/* + * vfe_pm_domain_off - Disable power domains specific to this VFE. + * @vfe: VFE Device + */ +static void vfe_pm_domain_off(struct vfe_device *vfe) +{ + /* nop */ +} + +/* + * vfe_pm_domain_on - Enable power domains specific to this VFE. + * @vfe: VFE Device + */ +static int vfe_pm_domain_on(struct vfe_device *vfe) +{ + return 0; +} + +/* + * vfe_queue_buffer - Add empty buffer + * @vid: Video device structure + * @buf: Buffer to be enqueued + * + * Add an empty buffer - depending on the current number of buffers it will be + * put in pending buffer queue or directly given to the hardware to be filled. + * + * Return 0 on success or a negative error code otherwise + */ +static int vfe_queue_buffer(struct camss_video *vid, + struct camss_buffer *buf) +{ + struct vfe_line *line = container_of(vid, struct vfe_line, video_out); + struct vfe_device *vfe = to_vfe(line); + struct vfe_output *output; + unsigned long flags; + + output = &line->output; + + spin_lock_irqsave(&vfe->output_lock, flags); + + if (output->state == VFE_OUTPUT_ON && output->gen2.active_num < 2) { + output->buf[output->gen2.active_num++] = buf; + vfe_wm_update(vfe, output->wm_idx[0], buf->addr[0], line); + } else { + vfe_buf_add_pending(output, buf); + } + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return 0; +} + +static const struct camss_video_ops vfe_video_ops_480 = { + .queue_buffer = vfe_queue_buffer, + .flush_buffers = vfe_flush_buffers, +}; + +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) +{ + vfe->video_ops = vfe_video_ops_480; + vfe->line_num = 1; +} + +const struct vfe_hw_ops vfe_ops_480 = { + .global_reset = vfe_global_reset, + .hw_version = vfe_hw_version, + .isr = vfe_isr, + .pm_domain_off = vfe_pm_domain_off, + .pm_domain_on = vfe_pm_domain_on, + .subdev_init = vfe_subdev_init, + .vfe_disable = vfe_disable, + .vfe_enable = vfe_enable, + .vfe_halt = vfe_halt, +}; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h index f166d176cb77..6500474a749e 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -201,5 +201,6 @@ extern const struct vfe_hw_ops vfe_ops_4_1; extern const struct vfe_hw_ops vfe_ops_4_7; extern const struct vfe_hw_ops vfe_ops_4_8; extern const struct vfe_hw_ops vfe_ops_170; +extern const struct vfe_hw_ops vfe_ops_480; #endif /* QC_MSM_CAMSS_VFE_H */ From patchwork Thu Dec 2 15:37:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 519999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6209BC4167D for ; Thu, 2 Dec 2021 15:36:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359095AbhLBPjZ (ORCPT ); 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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id bd18sm3662wmb.43.2021.12.02.07.35.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Dec 2021 07:35:59 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, robert.foss@linaro.org, jonathan@marek.ca Cc: andrey.konovalov@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, jgrahsl@snap.com, hfink@snap.com, bryan.odonoghue@linaro.org Subject: [RESEND PATCH v2 17/19] media: camss: Add SM8250 bandwdith configuration support Date: Thu, 2 Dec 2021 15:37:27 +0000 Message-Id: <20211202153729.3362372-18-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> References: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Downstream makes some pretty explicit comments about voting for bus bandwidth prior to camcc_camnoc_axi_clk_src. Working with camx downstream also shows that the bandwidth vote is required to get that root clock working. Add a simple mechanism to declare set and unset named NOCs. Whereas the objective is to enable the sm8250 specifically the code has been implemented to allow setting of whatever NOCs different SoCs using this driver may require. Tested-by: Julian Grahsl Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss.c | 81 +++++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 17 +++++ 2 files changed, 98 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 066639db9f18..d9905e737d88 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -8,6 +8,7 @@ * Copyright (C) 2015-2018 Linaro Ltd. */ #include +#include #include #include #include @@ -841,6 +842,29 @@ static const struct resources vfe_res_8250[] = { }, }; +static const struct resources_icc icc_res_sm8250[] = { + { + .name = "cam_ahb", + .icc_bw_tbl.avg = 38400, + .icc_bw_tbl.peak = 76800, + }, + { + .name = "cam_hf_0_mnoc", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, + { + .name = "cam_sf_0_mnoc", + .icc_bw_tbl.avg = 0, + .icc_bw_tbl.peak = 2097152, + }, + { + .name = "cam_sf_icp_mnoc", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, +}; + /* * camss_add_clock_margin - Add margin to clock frequency rate * @rate: Clock frequency rate @@ -1470,6 +1494,29 @@ static int camss_configure_pd(struct camss *camss) return ret; } +static int camss_icc_get(struct camss *camss) +{ + const struct resources_icc *icc_res; + int nbr_icc_paths = 0; + int i; + + if (camss->version == CAMSS_8250) { + icc_res = &icc_res_sm8250[0]; + nbr_icc_paths = ICC_SM8250_COUNT; + } + + for (i = 0; i < nbr_icc_paths; i++) { + camss->icc_path[i] = devm_of_icc_get(camss->dev, + icc_res[i].name); + if (IS_ERR(camss->icc_path[i])) + return PTR_ERR(camss->icc_path[i]); + + camss->icc_bw_tbl[i] = icc_res[i].icc_bw_tbl; + } + + return 0; +} + /* * camss_probe - Probe CAMSS platform device * @pdev: Pointer to CAMSS platform device @@ -1562,6 +1609,10 @@ static int camss_probe(struct platform_device *pdev) goto err_cleanup; } + ret = camss_icc_get(camss); + if (ret < 0) + goto err_cleanup; + ret = camss_init_subdevices(camss); if (ret < 0) goto err_cleanup; @@ -1695,11 +1746,41 @@ MODULE_DEVICE_TABLE(of, camss_dt_match); static int __maybe_unused camss_runtime_suspend(struct device *dev) { + struct camss *camss = dev_get_drvdata(dev); + int nbr_icc_paths = 0; + int i; + int ret; + + if (camss->version == CAMSS_8250) + nbr_icc_paths = ICC_SM8250_COUNT; + + for (i = 0; i < nbr_icc_paths; i++) { + ret = icc_set_bw(camss->icc_path[i], 0, 0); + if (ret) + return ret; + } + return 0; } static int __maybe_unused camss_runtime_resume(struct device *dev) { + struct camss *camss = dev_get_drvdata(dev); + int nbr_icc_paths = 0; + int i; + int ret; + + if (camss->version == CAMSS_8250) + nbr_icc_paths = ICC_SM8250_COUNT; + + for (i = 0; i < nbr_icc_paths; i++) { + ret = icc_set_bw(camss->icc_path[i], + camss->icc_bw_tbl[i].avg, + camss->icc_bw_tbl[i].peak); + if (ret) + return ret; + } + return 0; } diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 377e2474a485..9c644e638a94 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -56,6 +56,16 @@ struct resources_ispif { char *interrupt; }; +struct icc_bw_tbl { + u32 avg; + u32 peak; +}; + +struct resources_icc { + char *name; + struct icc_bw_tbl icc_bw_tbl; +}; + enum pm_domain { PM_DOMAIN_VFE0 = 0, PM_DOMAIN_VFE1 = 1, @@ -72,6 +82,11 @@ enum camss_version { CAMSS_8250, }; +enum icc_count { + ICC_DEFAULT_COUNT = 0, + ICC_SM8250_COUNT = 4, +}; + struct camss { enum camss_version version; struct v4l2_device v4l2_dev; @@ -88,6 +103,8 @@ struct camss { atomic_t ref_count; struct device *genpd[PM_DOMAIN_GEN2_COUNT]; struct device_link *genpd_link[PM_DOMAIN_GEN2_COUNT]; + struct icc_path *icc_path[ICC_SM8250_COUNT]; + struct icc_bw_tbl icc_bw_tbl[ICC_SM8250_COUNT]; }; struct camss_camera_interface { From patchwork Thu Dec 2 15:37:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 519998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2212CC4167E for ; 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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id bd18sm3662wmb.43.2021.12.02.07.35.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Dec 2021 07:36:00 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, robert.foss@linaro.org, jonathan@marek.ca Cc: andrey.konovalov@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, jgrahsl@snap.com, hfink@snap.com, bryan.odonoghue@linaro.org Subject: [RESEND PATCH v2 18/19] media: camss: Do vfe_get/vfe_put for csid on sm8250 Date: Thu, 2 Dec 2021 15:37:28 +0000 Message-Id: <20211202153729.3362372-19-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> References: <20211202153729.3362372-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The sm8250 CAMSS CSID depends on the VFE it is attached to being powered on and clocked prior to taking the CSID out of reset. It is possible to open just the CSID subdev from libcamera and attempt to bring the CSID block up. If we do not first bring up the VFE the CSID will fail to come out of reset. Tested-by: Julian Grahsl Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss-csid.c | 12 +++++++++++- drivers/media/platform/qcom/camss/camss-vfe.c | 4 ++-- drivers/media/platform/qcom/camss/camss-vfe.h | 3 +++ 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index 9ef6fbbeeddf..e6835b92695b 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -156,10 +156,18 @@ static int csid_set_clock_rates(struct csid_device *csid) static int csid_set_power(struct v4l2_subdev *sd, int on) { struct csid_device *csid = v4l2_get_subdevdata(sd); - struct device *dev = csid->camss->dev; + struct camss *camss = csid->camss; + struct device *dev = camss->dev; + struct vfe_device *vfe = &camss->vfe[csid->id]; int ret; if (on) { + if (camss->version == CAMSS_8250) { + ret = vfe_get(vfe); + if (ret < 0) + return ret; + } + ret = pm_runtime_resume_and_get(dev); if (ret < 0) return ret; @@ -204,6 +212,8 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) camss_disable_clocks(csid->nclocks, csid->clock); ret = csid->vdda ? regulator_disable(csid->vdda) : 0; pm_runtime_put_sync(dev); + if (camss->version == CAMSS_8250) + vfe_put(vfe); } return ret; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 5b5fe620914d..703ea39f1262 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -575,7 +575,7 @@ static int vfe_check_clock_rates(struct vfe_device *vfe) * * Return 0 on success or a negative error code otherwise */ -static int vfe_get(struct vfe_device *vfe) +int vfe_get(struct vfe_device *vfe) { int ret; @@ -637,7 +637,7 @@ static int vfe_get(struct vfe_device *vfe) * vfe_put - Power down VFE module * @vfe: VFE Device */ -static void vfe_put(struct vfe_device *vfe) +void vfe_put(struct vfe_device *vfe) { mutex_lock(&vfe->power_lock); diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h index 6500474a749e..0eba04eb9b77 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -203,4 +203,7 @@ extern const struct vfe_hw_ops vfe_ops_4_8; extern const struct vfe_hw_ops vfe_ops_170; extern const struct vfe_hw_ops vfe_ops_480; +int vfe_get(struct vfe_device *vfe); +void vfe_put(struct vfe_device *vfe); + #endif /* QC_MSM_CAMSS_VFE_H */