From patchwork Thu Nov 8 12:16:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 150502 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp752174ljp; Thu, 8 Nov 2018 04:20:38 -0800 (PST) X-Google-Smtp-Source: AJdET5cn5pB+Pdi58eJodA0uzOn7KZEgfLVTYvCDKk30uInVHKTFlBMyaeL+UKYyaq5i1gHXRSvg X-Received: by 2002:a37:a3c6:: with SMTP id m189mr3869991qke.173.1541679638588; Thu, 08 Nov 2018 04:20:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541679638; cv=none; d=google.com; s=arc-20160816; b=eV7/Bvl3xPNYUFfw5frd23PgqS32KrhPfTmCFom0dfLy91m9ab4nQkEmyTH7zO4Qup WvOMCj4MQrS6mnwisFrVuRoHs/bmd0xLO6Dnq3ODtJO+GHbuHPVv/9fRHNblW5hudf/m LhJegSRHiQdOCxq1yXiskkbGXSdX6M0szAMPPpqxia/jnN0iTlpYHT4TQHnXr8WYYj+d iZUCdCp9oY4o6ybx35PSY8HfOZ9FDcOSs8Elql30wZpScK7pBkUY2svlDotOrIHrQsP3 gNPs6iaOkX7HESBdDsFE4X4OZMYIF5ZmpJ1oI32NIqL/J5rU5tpuOpZGV4cRPEred4gc rEmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=TsrtDyL64HPKPkB/TApwvW9vBv3B8YkR88TWw/ChI6E=; b=SudeFBWUQZDuebYxBJIZIL7xB1HwowcN3kI9t6mLmBAWbV/VDtoCVdFpJkYXVU/Dqi ncl2O14kq61Q3accu31Clw8pqLCQfB+s6Y2skrm2iADVt2gbK10j6VOrBsrPvF64skCT IatQpLIecNZ7iZZTtHz9eKeQw3U4rG5kqwesvle6MxafzPByREBW/Qq5EvGTpfCeMOfo g2ifRj1J41aG9l6mf9j0GV8D8BBiJbw5/hc+Vrhrob0F19TDlYqOCVVd193MvhnPNqx3 EQSaRxss/YW9xZ6mF2igqa0+t46MO7u0OKgwd/vdGYi5lAd3hb0APDoeJHM8BOMXrf64 /Q/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=ccoVQZxK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q8-v6si2865516qtl.393.2018.11.08.04.20.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Nov 2018 04:20:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=ccoVQZxK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56268 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjIb-000863-Ty for patch@linaro.org; Thu, 08 Nov 2018 07:20:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43285) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjF8-00058p-Tq for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKjF3-0003ac-EA for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:02 -0500 Received: from ozlabs.org ([203.11.71.1]:47591) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKjF2-0003N5-4O; Thu, 08 Nov 2018 07:16:57 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 42rMhz1L4Sz9sCX; Thu, 8 Nov 2018 23:16:51 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1541679411; bh=IfOiPzpbfGvZHKXNIZYEO/DT8zI29YjxUf3nKJYzH18=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ccoVQZxKvmn7DY76JasFZ/R2+p1GHvxIfw6SkCLxKfMc7VeDrQJaWZqIot8B7C7f1 I/I9G4nI9OD5EEEqqizMPzCwJnvIRbgE3hsKoywYINmRF9pS84CNyJYxrcwNyeRVY6 YckN9u1Y2tubsHLdnQGkxwqmsVjVcDR0CuZkQqFc= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 8 Nov 2018 23:16:30 +1100 Message-Id: <20181108121646.26173-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108121646.26173-1-david@gibson.dropbear.id.au> References: <20181108121646.26173-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 06/22] target/ppc: Split up float_invalid_op_excp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Richard Henderson , agraf@suse.de, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The always_inline trick only works if the function is always called from the outer-most helper. But it isn't, so pass in the outer-most return address. There's no need for a switch statement whose argument is always a constant. Unravel the switch and goto via more helpers. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 344 +++++++++++++++++++++------------------- 1 file changed, 181 insertions(+), 163 deletions(-) -- 2.19.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index b9bb1b856e..6ec5227dd5 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -170,96 +170,120 @@ COMPUTE_FPRF(float64) COMPUTE_FPRF(float128) /* Floating-point invalid operations exception */ -static inline __attribute__((__always_inline__)) -uint64_t float_invalid_op_excp(CPUPPCState *env, int op, int set_fpcc) +static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); - uint64_t ret = 0; - int ve; + /* Update the floating-point invalid operation summary */ + env->fpscr |= 1 << FPSCR_VX; + /* Update the floating-point exception summary */ + env->fpscr |= FP_FX; + if (fpscr_ve != 0) { + /* Update the floating-point enabled exception summary */ + env->fpscr |= 1 << FPSCR_FEX; + if (fp_exceptions_enabled(env)) { + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_FP | op, retaddr); + } + } +} - ve = fpscr_ve; - switch (op) { - case POWERPC_EXCP_FP_VXSNAN: - env->fpscr |= 1 << FPSCR_VXSNAN; - break; - case POWERPC_EXCP_FP_VXSOFT: - env->fpscr |= 1 << FPSCR_VXSOFT; - break; - case POWERPC_EXCP_FP_VXISI: - /* Magnitude subtraction of infinities */ - env->fpscr |= 1 << FPSCR_VXISI; - goto update_arith; - case POWERPC_EXCP_FP_VXIDI: - /* Division of infinity by infinity */ - env->fpscr |= 1 << FPSCR_VXIDI; - goto update_arith; - case POWERPC_EXCP_FP_VXZDZ: - /* Division of zero by zero */ - env->fpscr |= 1 << FPSCR_VXZDZ; - goto update_arith; - case POWERPC_EXCP_FP_VXIMZ: - /* Multiplication of zero by infinity */ - env->fpscr |= 1 << FPSCR_VXIMZ; - goto update_arith; - case POWERPC_EXCP_FP_VXVC: - /* Ordered comparison of NaN */ - env->fpscr |= 1 << FPSCR_VXVC; +static void finish_invalid_op_arith(CPUPPCState *env, int op, + bool set_fpcc, uintptr_t retaddr) +{ + env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); + if (fpscr_ve == 0) { if (set_fpcc) { env->fpscr &= ~(0xF << FPSCR_FPCC); env->fpscr |= 0x11 << FPSCR_FPCC; } - /* We must update the target FPR before raising the exception */ - if (ve != 0) { - cs->exception_index = POWERPC_EXCP_PROGRAM; - env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; - /* Update the floating-point enabled exception summary */ - env->fpscr |= 1 << FPSCR_FEX; - /* Exception is differed */ - ve = 0; - } - break; - case POWERPC_EXCP_FP_VXSQRT: - /* Square root of a negative number */ - env->fpscr |= 1 << FPSCR_VXSQRT; - update_arith: - env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); - if (ve == 0) { - /* Set the result to quiet NaN */ - ret = 0x7FF8000000000000ULL; - if (set_fpcc) { - env->fpscr &= ~(0xF << FPSCR_FPCC); - env->fpscr |= 0x11 << FPSCR_FPCC; - } - } - break; - case POWERPC_EXCP_FP_VXCVI: - /* Invalid conversion */ - env->fpscr |= 1 << FPSCR_VXCVI; - env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); - if (ve == 0) { - /* Set the result to quiet NaN */ - ret = 0x7FF8000000000000ULL; - if (set_fpcc) { - env->fpscr &= ~(0xF << FPSCR_FPCC); - env->fpscr |= 0x11 << FPSCR_FPCC; - } - } - break; + } + finish_invalid_op_excp(env, op, retaddr); +} + +/* Signalling NaN */ +static void float_invalid_op_vxsnan(CPUPPCState *env, uintptr_t retaddr) +{ + env->fpscr |= 1 << FPSCR_VXSNAN; + finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, retaddr); +} + +/* Magnitude subtraction of infinities */ +static void float_invalid_op_vxisi(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |= 1 << FPSCR_VXISI; + finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXISI, set_fpcc, retaddr); +} + +/* Division of infinity by infinity */ +static void float_invalid_op_vxidi(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |= 1 << FPSCR_VXIDI; + finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIDI, set_fpcc, retaddr); +} + +/* Division of zero by zero */ +static void float_invalid_op_vxzdz(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |= 1 << FPSCR_VXZDZ; + finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXZDZ, set_fpcc, retaddr); +} + +/* Multiplication of zero by infinity */ +static void float_invalid_op_vximz(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |= 1 << FPSCR_VXIMZ; + finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIMZ, set_fpcc, retaddr); +} + +/* Square root of a negative number */ +static void float_invalid_op_vxsqrt(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |= 1 << FPSCR_VXSQRT; + finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXSQRT, set_fpcc, retaddr); +} + +/* Ordered comparison of NaN */ +static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |= 1 << FPSCR_VXVC; + if (set_fpcc) { + env->fpscr &= ~(0xF << FPSCR_FPCC); + env->fpscr |= 0x11 << FPSCR_FPCC; } /* Update the floating-point invalid operation summary */ env->fpscr |= 1 << FPSCR_VX; /* Update the floating-point exception summary */ env->fpscr |= FP_FX; - if (ve != 0) { + /* We must update the target FPR before raising the exception */ + if (fpscr_ve != 0) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + + cs->exception_index = POWERPC_EXCP_PROGRAM; + env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; - if (fp_exceptions_enabled(env)) { - /* GETPC() works here because this is inline */ - raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, - POWERPC_EXCP_FP | op, GETPC()); + /* Exception is differed */ + } +} + +/* Invalid conversion */ +static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |= 1 << FPSCR_VXCVI; + env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); + if (fpscr_ve == 0) { + if (set_fpcc) { + env->fpscr &= ~(0xF << FPSCR_FPCC); + env->fpscr |= 0x11 << FPSCR_FPCC; } } - return ret; + finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, retaddr); } static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr) @@ -632,11 +656,11 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) if (unlikely(status & float_flag_invalid)) { if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { /* Magnitude subtraction of infinities */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + float_invalid_op_vxisi(env, 1, GETPC()); } else if (float64_is_signaling_nan(arg1, &env->fp_status) || float64_is_signaling_nan(arg2, &env->fp_status)) { /* sNaN addition */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } @@ -652,11 +676,11 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) if (unlikely(status & float_flag_invalid)) { if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { /* Magnitude subtraction of infinities */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + float_invalid_op_vxisi(env, 1, GETPC()); } else if (float64_is_signaling_nan(arg1, &env->fp_status) || float64_is_signaling_nan(arg2, &env->fp_status)) { /* sNaN addition */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } @@ -673,11 +697,11 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) if ((float64_is_infinity(arg1) && float64_is_zero(arg2)) || (float64_is_zero(arg1) && float64_is_infinity(arg2))) { /* Multiplication of zero by infinity */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); + float_invalid_op_vximz(env, 1, GETPC()); } else if (float64_is_signaling_nan(arg1, &env->fp_status) || float64_is_signaling_nan(arg2, &env->fp_status)) { /* sNaN multiplication */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } @@ -695,14 +719,14 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) /* Determine what kind of invalid operation was seen. */ if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { /* Division of infinity by infinity */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1); + float_invalid_op_vxidi(env, 1, GETPC()); } else if (float64_is_zero(arg1) && float64_is_zero(arg2)) { /* Division of zero by zero */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1); + float_invalid_op_vxzdz(env, 1, GETPC()); } else if (float64_is_signaling_nan(arg1, &env->fp_status) || float64_is_signaling_nan(arg2, &env->fp_status)) { /* sNaN division */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } if (status & float_flag_divbyzero) { @@ -724,14 +748,14 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \ \ if (unlikely(env->fp_status.float_exception_flags)) { \ if (float64_is_any_nan(arg)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \ + float_invalid_op_vxcvi(env, 1, GETPC()); \ if (float64_is_signaling_nan(arg, &env->fp_status)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ farg.ll = nanval; \ } else if (env->fp_status.float_exception_flags & \ float_flag_invalid) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \ + float_invalid_op_vxcvi(env, 1, GETPC()); \ } \ float_check_status(env); \ } \ @@ -776,7 +800,7 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg, if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { /* sNaN round */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); farg.ll = arg | 0x0008000000000000ULL; } else { int inexact = get_float_exception_flags(&env->fp_status) & @@ -817,18 +841,18 @@ uint64_t helper_frim(CPUPPCState *env, uint64_t arg) #define FPU_MADDSUB_UPDATE(NAME, TP) \ static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \ - unsigned int madd_flags) \ + unsigned int madd_flags, uintptr_t retaddr) \ { \ if (TP##_is_signaling_nan(arg1, &env->fp_status) || \ TP##_is_signaling_nan(arg2, &env->fp_status) || \ TP##_is_signaling_nan(arg3, &env->fp_status)) { \ /* sNaN operation */ \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \ + float_invalid_op_vxsnan(env, retaddr); \ } \ if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \ (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \ /* Multiplication of zero by infinity */ \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); \ + float_invalid_op_vximz(env, 1, retaddr); \ } \ if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \ TP##_is_infinity(arg3)) { \ @@ -841,7 +865,7 @@ static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \ cSign ^= 1; \ } \ if (aSign ^ bSign ^ cSign) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); \ + float_invalid_op_vxisi(env, 1, retaddr); \ } \ } \ } @@ -859,7 +883,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \ if (flags) { \ if (flags & float_flag_invalid) { \ float64_maddsub_update_excp(env, arg1, arg2, arg3, \ - madd_flags); \ + madd_flags, GETPC()); \ } \ float_check_status(env); \ } \ @@ -885,8 +909,7 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) farg.ll = arg; if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - /* sNaN square root */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } f32 = float64_to_float32(farg.d, &env->fp_status); farg.d = float32_to_float64(f32, &env->fp_status); @@ -904,11 +927,11 @@ float64 helper_fsqrt(CPUPPCState *env, float64 arg) if (unlikely(float64_is_any_nan(arg))) { if (unlikely(float64_is_signaling_nan(arg, &env->fp_status))) { /* sNaN square root */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } else { /* Square root of a negative nonzero number */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); + float_invalid_op_vxsqrt(env, 1, GETPC()); } } @@ -926,7 +949,7 @@ float64 helper_fre(CPUPPCState *env, float64 arg) if (status & float_flag_invalid) { if (float64_is_signaling_nan(arg, &env->fp_status)) { /* sNaN reciprocal */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } if (status & float_flag_divbyzero) { @@ -949,7 +972,7 @@ uint64_t helper_fres(CPUPPCState *env, uint64_t arg) if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { /* sNaN reciprocal */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } farg.d = float64_div(float64_one, farg.d, &env->fp_status); f32 = float64_to_float32(farg.d, &env->fp_status); @@ -970,10 +993,10 @@ float64 helper_frsqrte(CPUPPCState *env, float64 arg) if (status & float_flag_invalid) { if (float64_is_signaling_nan(arg, &env->fp_status)) { /* sNaN reciprocal */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } else { /* Square root of a negative nonzero number */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); + float_invalid_op_vxsqrt(env, 1, GETPC()); } } if (status & float_flag_divbyzero) { @@ -1095,7 +1118,7 @@ void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2, && (float64_is_signaling_nan(farg1.d, &env->fp_status) || float64_is_signaling_nan(farg2.d, &env->fp_status)))) { /* sNaN comparison */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } @@ -1123,14 +1146,11 @@ void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2, env->fpscr |= ret << FPSCR_FPRF; env->crf[crfD] = ret; if (unlikely(ret == 0x01UL)) { + float_invalid_op_vxvc(env, 1, GETPC()); if (float64_is_signaling_nan(farg1.d, &env->fp_status) || float64_is_signaling_nan(farg2.d, &env->fp_status)) { /* sNaN comparison */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | - POWERPC_EXCP_FP_VXVC, 1); - } else { - /* qNaN comparison */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 1); + float_invalid_op_vxsnan(env, GETPC()); } } } @@ -1783,10 +1803,10 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \ + float_invalid_op_vxisi(env, sfprf, GETPC()); \ } else if (tp##_is_signaling_nan(xa.fld, &tstat) || \ tp##_is_signaling_nan(xb.fld, &tstat)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ } \ \ @@ -1832,10 +1852,10 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode) if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + float_invalid_op_vxisi(env, 1, GETPC()); } else if (float128_is_signaling_nan(xa.f128, &tstat) || float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } @@ -1872,10 +1892,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) || \ (tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf); \ + float_invalid_op_vximz(env, sfprf, GETPC()); \ } else if (tp##_is_signaling_nan(xa.fld, &tstat) || \ tp##_is_signaling_nan(xb.fld, &tstat)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ } \ \ @@ -1919,10 +1939,10 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opcode) if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if ((float128_is_infinity(xa.f128) && float128_is_zero(xb.f128)) || (float128_is_infinity(xb.f128) && float128_is_zero(xa.f128))) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); + float_invalid_op_vximz(env, 1, GETPC()); } else if (float128_is_signaling_nan(xa.f128, &tstat) || float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } helper_compute_fprf_float128(env, xt.f128); @@ -1957,13 +1977,12 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf); \ - } else if (tp##_is_zero(xa.fld) && \ - tp##_is_zero(xb.fld)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf); \ + float_invalid_op_vxidi(env, sfprf, GETPC()); \ + } else if (tp##_is_zero(xa.fld) && tp##_is_zero(xb.fld)) { \ + float_invalid_op_vxzdz(env, sfprf, GETPC()); \ } else if (tp##_is_signaling_nan(xa.fld, &tstat) || \ - tp##_is_signaling_nan(xb.fld, &tstat)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ + tp##_is_signaling_nan(xb.fld, &tstat)) { \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ } \ if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \ @@ -2009,13 +2028,12 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode) if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1); - } else if (float128_is_zero(xa.f128) && - float128_is_zero(xb.f128)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1); + float_invalid_op_vxidi(env, 1, GETPC()); + } else if (float128_is_zero(xa.f128) && float128_is_zero(xb.f128)) { + float_invalid_op_vxzdz(env, 1, GETPC()); } else if (float128_is_signaling_nan(xa.f128, &tstat) || - float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float128_is_signaling_nan(xb.f128, &tstat)) { + float_invalid_op_vxsnan(env, GETPC()); } } if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { @@ -2046,7 +2064,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ \ for (i = 0; i < nels; i++) { \ if (unlikely(tp##_is_signaling_nan(xb.fld, &env->fp_status))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ xt.fld = tp##_div(tp##_one, xb.fld, &env->fp_status); \ \ @@ -2093,9 +2111,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \ + float_invalid_op_vxsqrt(env, sfprf, GETPC()); \ } else if (tp##_is_signaling_nan(xb.fld, &tstat)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ } \ \ @@ -2143,9 +2161,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \ + float_invalid_op_vxsqrt(env, sfprf, GETPC()); \ } else if (tp##_is_signaling_nan(xb.fld, &tstat)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ } \ \ @@ -2329,7 +2347,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - tp##_maddsub_update_excp(env, xa.fld, b->fld, c->fld, maddflgs); \ + tp##_maddsub_update_excp(env, xa.fld, b->fld, \ + c->fld, maddflgs, GETPC()); \ } \ \ if (r2sp) { \ @@ -2407,10 +2426,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ float64_is_quiet_nan(xb.VsrD(0), &env->fp_status); \ } \ if (vxsnan_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ if (vxvc_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \ + float_invalid_op_vxvc(env, 0, GETPC()); \ } \ vex_flag = fpscr_ve && (vxvc_flag || vxsnan_flag); \ \ @@ -2522,10 +2541,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ } \ if (vxsnan_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ if (vxvc_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \ + float_invalid_op_vxvc(env, 0, GETPC()); \ } \ \ if (float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) { \ @@ -2572,10 +2591,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ } \ if (vxsnan_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ if (vxvc_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \ + float_invalid_op_vxvc(env, 0, GETPC()); \ } \ \ if (float128_lt(xa.f128, xb.f128, &env->fp_status)) { \ @@ -2617,7 +2636,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ xt.fld = tp##_##op(xa.fld, xb.fld, &env->fp_status); \ if (unlikely(tp##_is_signaling_nan(xa.fld, &env->fp_status) || \ tp##_is_signaling_nan(xb.fld, &env->fp_status))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ } \ \ @@ -2660,7 +2679,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ \ vex_flag = fpscr_ve & vxsnan_flag; \ if (vxsnan_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ if (!vex_flag) { \ putVSR(rD(opcode) + 32, &xt, env); \ @@ -2715,7 +2734,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ \ vex_flag = fpscr_ve & vxsnan_flag; \ if (vxsnan_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ if (!vex_flag) { \ putVSR(rD(opcode) + 32, &xt, env); \ @@ -2751,10 +2770,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ tp##_is_any_nan(xb.fld))) { \ if (tp##_is_signaling_nan(xa.fld, &env->fp_status) || \ tp##_is_signaling_nan(xb.fld, &env->fp_status)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ if (svxvc) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \ + float_invalid_op_vxvc(env, 0, GETPC()); \ } \ xt.fld = 0; \ all_true = 0; \ @@ -2807,7 +2826,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \ if (unlikely(stp##_is_signaling_nan(xb.sfld, \ &env->fp_status))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ xt.tfld = ttp##_snan_to_qnan(xt.tfld); \ } \ if (sfprf) { \ @@ -2846,7 +2865,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \ if (unlikely(stp##_is_signaling_nan(xb.sfld, \ &env->fp_status))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ xt.tfld = ttp##_snan_to_qnan(xt.tfld); \ } \ if (sfprf) { \ @@ -2883,7 +2902,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ xt.tfld = stp##_to_##ttp(xb.sfld, 1, &env->fp_status); \ if (unlikely(stp##_is_signaling_nan(xb.sfld, \ &env->fp_status))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ xt.tfld = ttp##_snan_to_qnan(xt.tfld); \ } \ if (sfprf) { \ @@ -2919,9 +2938,8 @@ void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode) xt.VsrD(0) = float128_to_float64(xb.f128, &tstat); env->fp_status.float_exception_flags |= tstat.float_exception_flags; - if (unlikely(float128_is_signaling_nan(xb.f128, - &tstat))) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); + if (unlikely(float128_is_signaling_nan(xb.f128, &tstat))) { + float_invalid_op_vxsnan(env, GETPC()); xt.VsrD(0) = float64_snan_to_qnan(xt.VsrD(0)); } helper_compute_fprf_float64(env, xt.VsrD(0)); @@ -2967,15 +2985,15 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ for (i = 0; i < nels; i++) { \ if (unlikely(stp##_is_any_nan(xb.sfld))) { \ if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \ + float_invalid_op_vxcvi(env, 0, GETPC()); \ xt.tfld = rnan; \ } else { \ xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \ &env->fp_status); \ if (env->fp_status.float_exception_flags & float_flag_invalid) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \ + float_invalid_op_vxcvi(env, 0, GETPC()); \ } \ } \ } \ @@ -3020,15 +3038,15 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ \ if (unlikely(stp##_is_any_nan(xb.sfld))) { \ if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \ + float_invalid_op_vxcvi(env, 0, GETPC()); \ xt.tfld = rnan; \ } else { \ xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \ &env->fp_status); \ if (env->fp_status.float_exception_flags & float_flag_invalid) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \ + float_invalid_op_vxcvi(env, 0, GETPC()); \ } \ } \ \ @@ -3144,7 +3162,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ for (i = 0; i < nels; i++) { \ if (unlikely(tp##_is_signaling_nan(xb.fld, \ &env->fp_status))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ xt.fld = tp##_snan_to_qnan(xb.fld); \ } else { \ xt.fld = tp##_round_to_int(xb.fld, &env->fp_status); \ @@ -3373,7 +3391,7 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode) if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); + float_invalid_op_vxsnan(env, GETPC()); xt.f128 = float128_snan_to_qnan(xt.f128); } } @@ -3433,7 +3451,7 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode) if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); + float_invalid_op_vxsnan(env, GETPC()); xt.f128 = float128_snan_to_qnan(xt.f128); } } @@ -3464,12 +3482,12 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode) if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); xt.f128 = float128_snan_to_qnan(xb.f128); } else if (float128_is_quiet_nan(xb.f128, &tstat)) { xt.f128 = xb.f128; } else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); + float_invalid_op_vxsqrt(env, 1, GETPC()); xt.f128 = float128_default_nan(&env->fp_status); } } @@ -3500,10 +3518,10 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode) if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + float_invalid_op_vxisi(env, 1, GETPC()); } else if (float128_is_signaling_nan(xa.f128, &tstat) || float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } From patchwork Thu Nov 8 12:16:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 150507 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp759839ljp; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id d1si240751qka.240.2018.11.08.04.28.59 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Nov 2018 04:29:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=VuqRUr4M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56314 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjQh-0005YX-D5 for patch@linaro.org; Thu, 08 Nov 2018 07:28:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43378) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjFI-0005Gf-Mu for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKjFG-0003kN-HV for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:12 -0500 Received: from ozlabs.org ([203.11.71.1]:43145) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKjF8-0003ak-Vr; Thu, 08 Nov 2018 07:17:04 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 42rMhz3Qdkz9sCs; Thu, 8 Nov 2018 23:16:51 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1541679411; bh=73da2Pmp+oN/tQlWl8w/MCB2NnvAmIjr6vEPqK3MPvk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VuqRUr4MyQev5/eLYDbXbHFa9XtDL4hLJMx275/aYNiVqkWFH1RdPHkpYEwnb48Wy nc1nrAyxsvTHaV+8dY5xltHNTJM+pM8funs04jel94leyu12dCZ5sSTcqsIqGUOLQ1 As6eg198GDs1UJ/hFB8ELJ7l3NErcCW4MpuuC5lk= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 8 Nov 2018 23:16:31 +1100 Message-Id: <20181108121646.26173-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108121646.26173-1-david@gibson.dropbear.id.au> References: <20181108121646.26173-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 07/22] target/ppc: Remove float_check_status X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Richard Henderson , agraf@suse.de, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Use do_float_check_status directly, so that we don't get confused about which return address we're using. And definitely don't use helper_float_check_status. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 77 +++++++++++++++++++---------------------- 1 file changed, 35 insertions(+), 42 deletions(-) -- 2.19.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 6ec5227dd5..c9198f826d 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -630,13 +630,6 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) } } -static inline __attribute__((__always_inline__)) -void float_check_status(CPUPPCState *env) -{ - /* GETPC() works here because this is inline */ - do_float_check_status(env, GETPC()); -} - void helper_float_check_status(CPUPPCState *env) { do_float_check_status(env, GETPC()); @@ -757,7 +750,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \ float_flag_invalid) { \ float_invalid_op_vxcvi(env, 1, GETPC()); \ } \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } \ return farg.ll; \ } @@ -782,7 +775,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \ } else { \ farg.d = cvtr(arg, &env->fp_status); \ } \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ return farg.ll; \ } @@ -815,7 +808,7 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg, env->fp_status.float_exception_flags &= ~float_flag_inexact; } } - float_check_status(env); + do_float_check_status(env, GETPC()); return farg.ll; } @@ -885,7 +878,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \ float64_maddsub_update_excp(env, arg1, arg2, arg3, \ madd_flags, GETPC()); \ } \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } \ return ret; \ } @@ -1819,7 +1812,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ } \ } \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0) @@ -1862,7 +1855,7 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode) helper_compute_fprf_float128(env, xt.f128); putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } /* VSX_MUL - VSX floating point multiply @@ -1909,7 +1902,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0) @@ -1948,7 +1941,7 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opcode) helper_compute_fprf_float128(env, xt.f128); putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } /* VSX_DIV - VSX floating point divide @@ -1999,7 +1992,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0) @@ -2042,7 +2035,7 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode) helper_compute_fprf_float128(env, xt.f128); putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } /* VSX_RE - VSX floating point reciprocal estimate @@ -2078,7 +2071,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0) @@ -2127,7 +2120,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0) @@ -2177,7 +2170,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0) @@ -2360,7 +2353,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ } \ putVSR(xT(opcode), &xt_out, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0) @@ -2443,7 +2436,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ } \ putVSR(xT(opcode), &xt, env); \ - helper_float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0) @@ -2480,7 +2473,7 @@ void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode) env->fpscr |= cc << FPSCR_FPRF; env->crf[BF(opcode)] = cc; - helper_float_check_status(env); + do_float_check_status(env, GETPC()); } void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode) @@ -2512,7 +2505,7 @@ void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode) env->fpscr |= cc << FPSCR_FPRF; env->crf[BF(opcode)] = cc; - helper_float_check_status(env); + do_float_check_status(env, GETPC()); } #define VSX_SCALAR_CMP(op, ordered) \ @@ -2559,7 +2552,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ env->fpscr |= cc << FPSCR_FPRF; \ env->crf[BF(opcode)] = cc; \ \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_SCALAR_CMP(xscmpodp, 1) @@ -2609,7 +2602,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ env->fpscr |= cc << FPSCR_FPRF; \ env->crf[BF(opcode)] = cc; \ \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_SCALAR_CMPQ(xscmpoqp, 1) @@ -2641,7 +2634,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0)) @@ -2792,7 +2785,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ if ((opcode >> (31-21)) & 1) { \ env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \ } \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0, 1) @@ -2835,7 +2828,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1) @@ -2874,7 +2867,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(rD(opcode) + 32, &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1) @@ -2911,7 +2904,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1) @@ -2945,7 +2938,7 @@ void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode) helper_compute_fprf_float64(env, xt.VsrD(0)); putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb) @@ -2999,7 +2992,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \ @@ -3051,7 +3044,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(rD(opcode) + 32, &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \ @@ -3092,7 +3085,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0) @@ -3127,7 +3120,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ helper_compute_fprf_##ttp(env, xt.tfld); \ \ putVSR(xT(opcode) + 32, &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128) @@ -3181,7 +3174,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_ties_away, 1) @@ -3209,7 +3202,7 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb) uint64_t xt = helper_frsp(env, xb); helper_compute_fprf_float64(env, xt); - float_check_status(env); + do_float_check_status(env, GETPC()); return xt; } @@ -3401,7 +3394,7 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode) } helper_compute_fprf_float128(env, xt.f128); - float_check_status(env); + do_float_check_status(env, GETPC()); putVSR(rD(opcode) + 32, &xt, env); } @@ -3458,7 +3451,7 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode) helper_compute_fprf_float128(env, xt.f128); putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode) @@ -3494,7 +3487,7 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode) helper_compute_fprf_float128(env, xt.f128); putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } void helper_xssubqp(CPUPPCState *env, uint32_t opcode) @@ -3527,5 +3520,5 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode) helper_compute_fprf_float128(env, xt.f128); putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } From patchwork Thu Nov 8 12:16:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 150508 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp760254ljp; Thu, 8 Nov 2018 04:29:27 -0800 (PST) X-Google-Smtp-Source: AJdET5ckzTrVfN4sbLSmPiv50V/6ZS63MCPJhAFSB4OzjyHpkhcGyd+C1oXApcQ7AXmacg84wgKG X-Received: by 2002:aed:23d8:: with SMTP id k24-v6mr4136662qtc.39.1541680167222; Thu, 08 Nov 2018 04:29:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541680167; cv=none; d=google.com; s=arc-20160816; b=wiuwz3QWIHN6DvrjQm0E1kdrGLBFGNOACBYrxScRrHwrQ6x0Z9vBx3ni1x8jw6jJn1 HqqAHUIwUt0SRlyp3ns1HM9zI1keKPw9DTcCipZPuSat84djwEtE5Q3cLtJezldHXDgs 8gQABQgxOrIs8+OnyB5+SXnsbyeLCqa2k/06tRaA8pUVriJSTWUL/AMCEOOJmNau+OHs DaEFa1bZ5CuGayhMo+4x5bphWu0wkKfBleM9XxPH/xwR8E2IRWRq0HYcBo2Ij9tbwJGA MkAyrFEGAe9pCAu1DjrRA5EzGv9d0WMPNRmikT9B4x3mfNJKqA5n8LAgkERSj55lGNCY cLYA== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id c7si3079020qkj.67.2018.11.08.04.29.26 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Nov 2018 04:29:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=NxaTcFV1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56315 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjR8-0005dY-7M for patch@linaro.org; Thu, 08 Nov 2018 07:29:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43373) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjFI-0005Gc-LZ for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKjFF-0003iw-VE for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:12 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:44029) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKjF8-0003at-S6; Thu, 08 Nov 2018 07:17:04 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 42rMj01wrmz9sDT; Thu, 8 Nov 2018 23:16:51 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1541679412; bh=SEgsqD9Kv2vjT3C3MPL+PuFeLmBYOgNwhYJnA0LjKkI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NxaTcFV1mUGOD5OUodWx2ipSTDiNrdw1SrZZOda6zaBNx9QoqZYOQW2bMNEJ3TjmK xdEuR5ToWyuczLfxU6h/MWJjMSxd3phS3C55lwK0dEI2G+m47BObzI3zAjjgbH7GoC 59f1zSXAN8SFPjjCYLIYU5HxYRFTHJpzNoTAtymg= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 8 Nov 2018 23:16:32 +1100 Message-Id: <20181108121646.26173-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108121646.26173-1-david@gibson.dropbear.id.au> References: <20181108121646.26173-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 08/22] target/ppc: Introduce fp number classification X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Richard Henderson , agraf@suse.de, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Having a separate, logical classifiation of numbers will unify more error paths for different formats. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 94 ++++++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 43 deletions(-) -- 2.19.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c9198f826d..9ae55b1e93 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -114,54 +114,62 @@ static inline int ppc_float64_get_unbiased_exp(float64 f) return ((f >> 52) & 0x7FF) - 1023; } -#define COMPUTE_FPRF(tp) \ -void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ +/* Classify a floating-point number. */ +enum { + is_normal = 1, + is_zero = 2, + is_denormal = 4, + is_inf = 8, + is_qnan = 16, + is_snan = 32, + is_neg = 64, +}; + +#define COMPUTE_CLASS(tp) \ +static int tp##_classify(tp arg) \ { \ - int isneg; \ - int fprf; \ - \ - isneg = tp##_is_neg(arg); \ + int ret = tp##_is_neg(arg) * is_neg; \ if (unlikely(tp##_is_any_nan(arg))) { \ - if (tp##_is_signaling_nan(arg, &env->fp_status)) { \ - /* Signaling NaN: flags are undefined */ \ - fprf = 0x00; \ - } else { \ - /* Quiet NaN */ \ - fprf = 0x11; \ - } \ + float_status dummy = { }; /* snan_bit_is_one = 0 */ \ + ret |= (tp##_is_signaling_nan(arg, &dummy) \ + ? is_snan : is_qnan); \ } else if (unlikely(tp##_is_infinity(arg))) { \ - /* +/- infinity */ \ - if (isneg) { \ - fprf = 0x09; \ - } else { \ - fprf = 0x05; \ - } \ + ret |= is_inf; \ + } else if (tp##_is_zero(arg)) { \ + ret |= is_zero; \ + } else if (tp##_is_zero_or_denormal(arg)) { \ + ret |= is_denormal; \ } else { \ - if (tp##_is_zero(arg)) { \ - /* +/- zero */ \ - if (isneg) { \ - fprf = 0x12; \ - } else { \ - fprf = 0x02; \ - } \ - } else { \ - if (tp##_is_zero_or_denormal(arg)) { \ - /* Denormalized numbers */ \ - fprf = 0x10; \ - } else { \ - /* Normalized numbers */ \ - fprf = 0x00; \ - } \ - if (isneg) { \ - fprf |= 0x08; \ - } else { \ - fprf |= 0x04; \ - } \ - } \ + ret |= is_normal; \ } \ - /* We update FPSCR_FPRF */ \ - env->fpscr &= ~(0x1F << FPSCR_FPRF); \ - env->fpscr |= fprf << FPSCR_FPRF; \ + return ret; \ +} + +COMPUTE_CLASS(float16) +COMPUTE_CLASS(float32) +COMPUTE_CLASS(float64) +COMPUTE_CLASS(float128) + +static void set_fprf_from_class(CPUPPCState *env, int class) +{ + static const uint8_t fprf[6][2] = { + { 0x04, 0x08 }, /* normalized */ + { 0x02, 0x12 }, /* zero */ + { 0x14, 0x18 }, /* denormalized */ + { 0x05, 0x09 }, /* infinity */ + { 0x11, 0x11 }, /* qnan */ + { 0x00, 0x00 }, /* snan -- flags are undefined */ + }; + bool isneg = class & is_neg; + + env->fpscr &= ~(0x1F << FPSCR_FPRF); + env->fpscr |= fprf[ctz32(class)][isneg] << FPSCR_FPRF; +} + +#define COMPUTE_FPRF(tp) \ +void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ +{ \ + set_fprf_from_class(env, tp##_classify(arg)); \ } COMPUTE_FPRF(float16) From patchwork Thu Nov 8 12:16:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 150503 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp752713ljp; Thu, 8 Nov 2018 04:21:11 -0800 (PST) X-Google-Smtp-Source: AJdET5cCUvbq/LeOoAcgPvzJxghU3NfyGwd1DWeKBH36BJDbkYbIJEQsviI0yU9KsPg5AetNQC4Z X-Received: by 2002:ac8:246:: with SMTP id o6mr4077835qtg.0.1541679671744; Thu, 08 Nov 2018 04:21:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541679671; cv=none; d=google.com; s=arc-20160816; b=vNVZCuZIhBWsbca1R1w9q5HzoeIIKcVHOXZ+pdOvpgJ0ItUYpRDv/rKxyqqMPmdplI JlC2Kic9F+15R7w5TEAOPXZR4vu4JF/3jTcFWih4P2xpbd/ZTNe3aXNBhueJ9CPn9MmA p5100X20dusnKPwgcuV2IFpuaMgxybQ6M4VG7biC7Fphhw9SXRdiP3snLS1jqZoDkKeb hOrn43r40CL/R8Gj5xOLcTb4vAtHb1tRbjgHVDGSo5pri/ewFRg++BM5CnD789CaAZtW B7cDo/exIEsSPVz3txMnYJYYADXNXbZtwsAa6HtY0XDUUgO6PzdsXSdYZBWhvFHjpdTW Q94g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=eOSlclc5WlQi7RQaBw3P8AjMBZXitdBmgje/QQLJ0KM=; b=obzaL3ulxkMlsKwLcf6FeKsedqxeJ9QGVuaVEQgF3OP0p4ZBt4N+TEz+vUlWWA6zhM KB7ee/3/LgiX/zVADF8wZ/kfIdwzR4Rxli+iemUPTZSbMx+khbnz1ZT2Vhl7RQjXyGdk QDcSHqWo+qMwFi9rM67YaW3HRa16TUL3/dwcexH8XAojRNqBwo/KEJVZw9cQlwAoe6Ew wWu+MsGSChgzDrBEGcPQuBUQAwkp3QgrzdyekuIBM9N9NHcxCmaHvFO+ubh0H9pNVHOK JbSwj3kosbky6JIZB2eEXX6/idNJ9jSXCz2af30lFesbrH2l+RUotuQfz0Oe8vi/ZIfs B1Tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=dYwGR8iM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id d2-v6si134609qtl.189.2018.11.08.04.21.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Nov 2018 04:21:11 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=dYwGR8iM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56271 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjJ8-0008EW-S7 for patch@linaro.org; Thu, 08 Nov 2018 07:21:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43374) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjFI-0005Gd-M8 for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKjFF-0003j1-Vd for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:12 -0500 Received: from ozlabs.org ([203.11.71.1]:39955) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKjF9-0003ai-1e; Thu, 08 Nov 2018 07:17:04 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 42rMhz4w9Nz9sC7; Thu, 8 Nov 2018 23:16:51 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1541679411; bh=ZtKJfw/x7B+A3VaIRZRTqMq0uSMST9WuJyiAqZyLuiI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dYwGR8iM3kLwSHsoRw8AOy1vtSiUh965PEjQKND5DMozF7KbUwomOVL2pdFYoA0JO S2ncq2PqrTGe6ntis7dXkwZ4L8zl23qwzSoYHWQfux+QGj3teh58FkAw/TBiKStXFg Z3/9CDDH7SblnNWy/FJ/R9nTcwxng28NdJlGhGIM= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 8 Nov 2018 23:16:33 +1100 Message-Id: <20181108121646.26173-10-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108121646.26173-1-david@gibson.dropbear.id.au> References: <20181108121646.26173-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 09/22] target/ppc: Split out float_invalid_op_addsub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Richard Henderson , agraf@suse.de, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 60 ++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 34 deletions(-) -- 2.19.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 9ae55b1e93..111ce12a37 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -648,6 +648,17 @@ void helper_reset_fpstatus(CPUPPCState *env) set_float_exception_flags(0, &env->fp_status); } +static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr, int classes) +{ + if ((classes & ~is_neg) == is_inf) { + /* Magnitude subtraction of infinities */ + float_invalid_op_vxisi(env, set_fpcc, retaddr); + } else if (classes & is_snan) { + float_invalid_op_vxsnan(env, retaddr); + } +} + /* fadd - fadd. */ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) { @@ -655,14 +666,9 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) int status = get_float_exception_flags(&env->fp_status); if (unlikely(status & float_flag_invalid)) { - if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { - /* Magnitude subtraction of infinities */ - float_invalid_op_vxisi(env, 1, GETPC()); - } else if (float64_is_signaling_nan(arg1, &env->fp_status) || - float64_is_signaling_nan(arg2, &env->fp_status)) { - /* sNaN addition */ - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_addsub(env, 1, GETPC(), + float64_classify(arg1) | + float64_classify(arg2)); } return ret; @@ -675,14 +681,9 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) int status = get_float_exception_flags(&env->fp_status); if (unlikely(status & float_flag_invalid)) { - if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { - /* Magnitude subtraction of infinities */ - float_invalid_op_vxisi(env, 1, GETPC()); - } else if (float64_is_signaling_nan(arg1, &env->fp_status) || - float64_is_signaling_nan(arg2, &env->fp_status)) { - /* sNaN addition */ - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_addsub(env, 1, GETPC(), + float64_classify(arg1) | + float64_classify(arg2)); } return ret; @@ -1803,12 +1804,9 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \ - float_invalid_op_vxisi(env, sfprf, GETPC()); \ - } else if (tp##_is_signaling_nan(xa.fld, &tstat) || \ - tp##_is_signaling_nan(xb.fld, &tstat)) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ + float_invalid_op_addsub(env, sfprf, GETPC(), \ + tp##_classify(xa.fld) | \ + tp##_classify(xb.fld)); \ } \ \ if (r2sp) { \ @@ -1852,12 +1850,9 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode) env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) { - float_invalid_op_vxisi(env, 1, GETPC()); - } else if (float128_is_signaling_nan(xa.f128, &tstat) || - float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_addsub(env, 1, GETPC(), + float128_classify(xa.f128) | + float128_classify(xb.f128)); } helper_compute_fprf_float128(env, xt.f128); @@ -3518,12 +3513,9 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode) env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) { - float_invalid_op_vxisi(env, 1, GETPC()); - } else if (float128_is_signaling_nan(xa.f128, &tstat) || - float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_addsub(env, 1, GETPC(), + float128_classify(xa.f128) | + float128_classify(xb.f128)); } helper_compute_fprf_float128(env, xt.f128); From patchwork Thu Nov 8 12:16:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 150504 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp754938ljp; Thu, 8 Nov 2018 04:23:30 -0800 (PST) X-Google-Smtp-Source: AJdET5ctraAgIYDfjkyWd7fDJgDu0ftMjEHwoUZgfHyn/zmJjl23SxuRhLfxpjtRk0GlEf3qU/lh X-Received: by 2002:a37:73c4:: with SMTP id o187mr3965908qkc.157.1541679810315; Thu, 08 Nov 2018 04:23:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541679810; cv=none; d=google.com; s=arc-20160816; b=bPHXKVhHcjJ6lFZeLiES1uFAI/TRApEfaAeJ4EYGiufQ1y4xQ4NLDuUb1bTw4AJABi 2CIsEdInHrhK07Mgr1fShk4O9/nQWv4Si4CYP7NLkGS/AG82RS1unj1wxSDYavbqAQ73 OjH6cVBKu9tugDf4rdWEIQ6TVdaLpLctpa/UJiQdFI6jzAM2N3Gab0awpsBLxv6gJ/hc GWAsegPfN+Pu5flTysA22BHS+Sd0NdIFhnya6ziFOLmQRRdjJS/OTlD02JluLTkcRxgT DgdWMN7Byxn/sR8g35D50AOyrFS4JZBvhXYG8PRbpboI7yHqsNvBB6S1/1AZvvRkQs78 O1Ng== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id q2si2497915qve.72.2018.11.08.04.23.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Nov 2018 04:23:30 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=E570JAZy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56281 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjLN-0006Ph-I5 for patch@linaro.org; Thu, 08 Nov 2018 07:23:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43380) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjFI-0005Gg-Nj for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKjFF-0003j5-Vr for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:12 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:38587) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKjF9-0003aq-5H; Thu, 08 Nov 2018 07:17:04 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 42rMhz6t7Bz9sDN; Thu, 8 Nov 2018 23:16:51 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1541679411; bh=A9yasmUbAMHyjZjx3e23I9I/soQHZlkIHlHFmejeMn4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E570JAZyUrf2hzo1JKOEMuTL5+nDl0GgKcUDou+QcTpeN7TD1gAUC2u1TEtK1BEAR FsqoxQ2h7b+8ZpkPE+BVqc14Pv3SI6r3An/5b8Pg8J2WWVV9UXQQXN2VIMhwC/L4yq HHbR0v83ns4Z+JzDY+WXSEXvLBbUrRL45mj2a/uQ= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 8 Nov 2018 23:16:34 +1100 Message-Id: <20181108121646.26173-11-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108121646.26173-1-david@gibson.dropbear.id.au> References: <20181108121646.26173-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 10/22] target/ppc: Split out float_invalid_op_mul X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Richard Henderson , agraf@suse.de, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 43 +++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 23 deletions(-) -- 2.19.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 111ce12a37..ef251d062f 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -689,6 +689,17 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) return ret; } +static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc, + uintptr_t retaddr, int classes) +{ + if ((classes & (is_zero | is_inf)) == (is_zero | is_inf)) { + /* Multiplication of zero by infinity */ + float_invalid_op_vximz(env, set_fprc, retaddr); + } else if (classes & is_snan) { + float_invalid_op_vxsnan(env, retaddr); + } +} + /* fmul - fmul. */ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) { @@ -696,15 +707,9 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) int status = get_float_exception_flags(&env->fp_status); if (unlikely(status & float_flag_invalid)) { - if ((float64_is_infinity(arg1) && float64_is_zero(arg2)) || - (float64_is_zero(arg1) && float64_is_infinity(arg2))) { - /* Multiplication of zero by infinity */ - float_invalid_op_vximz(env, 1, GETPC()); - } else if (float64_is_signaling_nan(arg1, &env->fp_status) || - float64_is_signaling_nan(arg2, &env->fp_status)) { - /* sNaN multiplication */ - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_mul(env, 1, GETPC(), + float64_classify(arg1) | + float64_classify(arg2)); } return ret; @@ -1886,13 +1891,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) || \ - (tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) { \ - float_invalid_op_vximz(env, sfprf, GETPC()); \ - } else if (tp##_is_signaling_nan(xa.fld, &tstat) || \ - tp##_is_signaling_nan(xb.fld, &tstat)) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ + float_invalid_op_mul(env, sfprf, GETPC(), \ + tp##_classify(xa.fld) | \ + tp##_classify(xb.fld)); \ } \ \ if (r2sp) { \ @@ -1933,13 +1934,9 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opcode) env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if ((float128_is_infinity(xa.f128) && float128_is_zero(xb.f128)) || - (float128_is_infinity(xb.f128) && float128_is_zero(xa.f128))) { - float_invalid_op_vximz(env, 1, GETPC()); - } else if (float128_is_signaling_nan(xa.f128, &tstat) || - float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_mul(env, 1, GETPC(), + float128_classify(xa.f128) | + float128_classify(xb.f128)); } helper_compute_fprf_float128(env, xt.f128); From patchwork Thu Nov 8 12:16:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 150506 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp757711ljp; Thu, 8 Nov 2018 04:26:38 -0800 (PST) X-Google-Smtp-Source: AJdET5d/6+3+UIJDQMpxWQ6+cORzZh75sp/MTGoyNJZ0c/oIt6KrSLSv+drMOne7eyFmzBxu0PXh X-Received: by 2002:a0c:89b4:: with SMTP id 49mr4123142qvr.85.1541679998539; Thu, 08 Nov 2018 04:26:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541679998; cv=none; d=google.com; s=arc-20160816; b=gE0FtAvbpPDijVD2bTZlQIjq/rNnkkOnFcVp7fUrO5J5DDKUjlE+q6CNrf+tJNBZgS OrtH44IhpsJEmvoRFii7CpEFC1oaHnh/EkPSwzMPx2dA+3TMGV4kXsxlHWxQX9no3CZz nFZoaxctAu9sWzK4WCF9Gw+tLwse2EgdizEzD7zgjnadFw8s87RaMR5EqNnyu2YkUixw mi3KO7HsBrFgIAiNPkUYrfR7nQT5e+PRZ36h67P5cH190romSOI2Id6VRpKE6prV5Sr0 Ff6g4Egbyh2D9HeWd2S2p5sp+1ar6hBq2gLqG2vrBddnVdmfF+apbzzzSwyyTWpQT7iA t5eg== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id r1si1207880qkk.116.2018.11.08.04.26.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Nov 2018 04:26:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=TaCScD6m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56303 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjOP-0000uk-U0 for patch@linaro.org; Thu, 08 Nov 2018 07:26:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43377) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjFI-0005Ge-Mx for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKjFF-0003ip-V2 for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:12 -0500 Received: from ozlabs.org ([203.11.71.1]:50525) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKjF9-0003aj-32; Thu, 08 Nov 2018 07:17:04 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 42rMj03d8Sz9sDL; Thu, 8 Nov 2018 23:16:51 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1541679412; bh=9Ghs4VDqjT0LmDD+Kg69o+dW1vEFBTpBw5cMo2oSpn0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TaCScD6mixbICuyU/TdOohKublI+qg7OqpwWZlDRPki2BneLnE0vPB6Pb+dX20mIP G1eFmur38IHDbOSl/hxoQd7ApbzEZUsJAhSIw0Cx03YXgjIbvrv8W+JVCZm1EPdUHC 9rHDkg3SivWqvCiKtkMOcA4VGVIpGNtIaS4Loupo= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 8 Nov 2018 23:16:35 +1100 Message-Id: <20181108121646.26173-12-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108121646.26173-1-david@gibson.dropbear.id.au> References: <20181108121646.26173-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 11/22] target/ppc: Split out float_invalid_op_div X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Richard Henderson , agraf@suse.de, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 52 +++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 28 deletions(-) -- 2.19.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index ef251d062f..127c08bcec 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -715,6 +715,21 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) return ret; } +static void float_invalid_op_div(CPUPPCState *env, bool set_fprc, + uintptr_t retaddr, int classes) +{ + classes &= ~is_neg; + if (classes == is_inf) { + /* Division of infinity by infinity */ + float_invalid_op_vxidi(env, set_fprc, retaddr); + } else if (classes == is_zero) { + /* Division of zero by zero */ + float_invalid_op_vxzdz(env, set_fprc, retaddr); + } else if (classes & is_snan) { + float_invalid_op_vxsnan(env, retaddr); + } +} + /* fdiv - fdiv. */ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) { @@ -723,18 +738,9 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) if (unlikely(status)) { if (status & float_flag_invalid) { - /* Determine what kind of invalid operation was seen. */ - if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { - /* Division of infinity by infinity */ - float_invalid_op_vxidi(env, 1, GETPC()); - } else if (float64_is_zero(arg1) && float64_is_zero(arg2)) { - /* Division of zero by zero */ - float_invalid_op_vxzdz(env, 1, GETPC()); - } else if (float64_is_signaling_nan(arg1, &env->fp_status) || - float64_is_signaling_nan(arg2, &env->fp_status)) { - /* sNaN division */ - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_div(env, 1, GETPC(), + float64_classify(arg1) | + float64_classify(arg2)); } if (status & float_flag_divbyzero) { float_zero_divide_excp(env, GETPC()); @@ -1969,14 +1975,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \ - float_invalid_op_vxidi(env, sfprf, GETPC()); \ - } else if (tp##_is_zero(xa.fld) && tp##_is_zero(xb.fld)) { \ - float_invalid_op_vxzdz(env, sfprf, GETPC()); \ - } else if (tp##_is_signaling_nan(xa.fld, &tstat) || \ - tp##_is_signaling_nan(xb.fld, &tstat)) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ + float_invalid_op_div(env, sfprf, GETPC(), \ + tp##_classify(xa.fld) | \ + tp##_classify(xb.fld)); \ } \ if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \ float_zero_divide_excp(env, GETPC()); \ @@ -2020,14 +2021,9 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode) env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) { - float_invalid_op_vxidi(env, 1, GETPC()); - } else if (float128_is_zero(xa.f128) && float128_is_zero(xb.f128)) { - float_invalid_op_vxzdz(env, 1, GETPC()); - } else if (float128_is_signaling_nan(xa.f128, &tstat) || - float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_div(env, 1, GETPC(), + float128_classify(xa.f128) | + float128_classify(xb.f128)); } if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { float_zero_divide_excp(env, GETPC()); From patchwork Thu Nov 8 12:16:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 150505 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp757341ljp; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id y67-v6si2943710qkc.226.2018.11.08.04.26.13 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Nov 2018 04:26:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=hDLZoQug; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56299 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjO0-0000aj-VQ for patch@linaro.org; Thu, 08 Nov 2018 07:26:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43331) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjFC-0005CN-Hz for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKjF9-0003d1-0k for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:04 -0500 Received: from ozlabs.org ([203.11.71.1]:57209) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKjF6-0003b1-Td; Thu, 08 Nov 2018 07:17:02 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 42rMj05dBRz9sDb; Thu, 8 Nov 2018 23:16:51 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1541679412; bh=iXOPmoumeT7MYxOFsMfjvZCL4rocs4bFD6l7jrFX8fw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hDLZoQug8r9MNcWtmTAFzd1/DBXSeOWU7Pwge2C85N9uZhnCW37L+FHsfJx7rik3t T+DWsnKLyDDt9d4Amc/DOytnLEUiSzPsKijObHd+y5HcOx4ZDLtGwI/j24jt2VJz/0 U1JuYNXOVXD9t4qc2yRqy3yFURqNxqd7tAW6YBeM= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 8 Nov 2018 23:16:36 +1100 Message-Id: <20181108121646.26173-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108121646.26173-1-david@gibson.dropbear.id.au> References: <20181108121646.26173-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 12/22] target/ppc: Split out float_invalid_cvt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Richard Henderson , agraf@suse.de, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 67 +++++++++++++++++------------------------ 1 file changed, 28 insertions(+), 39 deletions(-) -- 2.19.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 127c08bcec..2ed4f42275 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -750,30 +750,30 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) return ret; } +static void float_invalid_cvt(CPUPPCState *env, bool set_fprc, + uintptr_t retaddr, int class1) +{ + float_invalid_op_vxcvi(env, set_fprc, retaddr); + if (class1 & is_snan) { + float_invalid_op_vxsnan(env, retaddr); + } +} #define FPU_FCTI(op, cvt, nanval) \ -uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \ +uint64_t helper_##op(CPUPPCState *env, float64 arg) \ { \ - CPU_DoubleU farg; \ - \ - farg.ll = arg; \ - farg.ll = float64_to_##cvt(farg.d, &env->fp_status); \ + uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \ + int status = get_float_exception_flags(&env->fp_status); \ \ - if (unlikely(env->fp_status.float_exception_flags)) { \ - if (float64_is_any_nan(arg)) { \ - float_invalid_op_vxcvi(env, 1, GETPC()); \ - if (float64_is_signaling_nan(arg, &env->fp_status)) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ - farg.ll = nanval; \ - } else if (env->fp_status.float_exception_flags & \ - float_flag_invalid) { \ - float_invalid_op_vxcvi(env, 1, GETPC()); \ + if (unlikely(status)) { \ + if (status & float_flag_invalid) { \ + float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \ + ret = nanval; \ } \ do_float_check_status(env, GETPC()); \ } \ - return farg.ll; \ - } + return ret; \ +} FPU_FCTI(fctiw, int32, 0x80000000U) FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U) @@ -2965,6 +2965,7 @@ uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb) #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ + int all_flags = env->fp_status.float_exception_flags, flags; \ ppc_vsr_t xt, xb; \ int i; \ \ @@ -2972,22 +2973,18 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ getVSR(xT(opcode), &xt, env); \ \ for (i = 0; i < nels; i++) { \ - if (unlikely(stp##_is_any_nan(xb.sfld))) { \ - if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ - float_invalid_op_vxcvi(env, 0, GETPC()); \ + env->fp_status.float_exception_flags = 0; \ + xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, &env->fp_status); \ + flags = env->fp_status.float_exception_flags; \ + if (unlikely(flags & float_flag_invalid)) { \ + float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb.sfld)); \ xt.tfld = rnan; \ - } else { \ - xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \ - &env->fp_status); \ - if (env->fp_status.float_exception_flags & float_flag_invalid) { \ - float_invalid_op_vxcvi(env, 0, GETPC()); \ - } \ } \ + all_flags |= flags; \ } \ \ putVSR(xT(opcode), &xt, env); \ + env->fp_status.float_exception_flags = all_flags; \ do_float_check_status(env, GETPC()); \ } @@ -3025,18 +3022,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ getVSR(rB(opcode) + 32, &xb, env); \ memset(&xt, 0, sizeof(xt)); \ \ - if (unlikely(stp##_is_any_nan(xb.sfld))) { \ - if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ - float_invalid_op_vxcvi(env, 0, GETPC()); \ + xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, &env->fp_status); \ + if (env->fp_status.float_exception_flags & float_flag_invalid) { \ + float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb.sfld)); \ xt.tfld = rnan; \ - } else { \ - xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \ - &env->fp_status); \ - if (env->fp_status.float_exception_flags & float_flag_invalid) { \ - float_invalid_op_vxcvi(env, 0, GETPC()); \ - } \ } \ \ putVSR(rD(opcode) + 32, &xt, env); \ From patchwork Thu Nov 8 12:16:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 150509 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp760446ljp; Thu, 8 Nov 2018 04:29:40 -0800 (PST) X-Google-Smtp-Source: AJdET5fT8uqXn6acmO/mmqPU325r73O/25QVtHPDbR2v2utVAmM+Y+NmNXYUiYMGSxjmfdC6orFO X-Received: by 2002:a0c:e8cc:: with SMTP id m12mr4303561qvo.186.1541680180207; Thu, 08 Nov 2018 04:29:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541680180; cv=none; d=google.com; s=arc-20160816; b=LA1Ry4q7wbBjOfsBF5LkqVSSyrNbkquUYf93IA7+YupbI1ddDazFKYBGft7B52mw7M 06r3uYaAJs/DaX+QrMxy5bcOTNtHkCZNlMcLoyBfHqANQ1pvS3XxhubIsZbkZVWUTUON RuaoqOVksGrPaeGEQ0qAD6PwJLinU+cSz+7zUJfANvqIaEAWQGy1MulvTlpoeRT6pN12 RWp1rJIYPGqse5x4molGQLC/jduvD0/TmHpzqkbi8wrulBMOGe2tl9EbsmKSiflKck18 RCAbNEmCNwhttA4XUD/rR66UiydV2Nk9BT/5UE5Sk+xlj6RUmcAQXJcWGi6U9MPLZcCq K3Ag== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id n40si225542qtf.91.2018.11.08.04.29.40 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Nov 2018 04:29:40 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b="nnjKs8/H"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56319 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjRL-00064f-L1 for patch@linaro.org; Thu, 08 Nov 2018 07:29:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43460) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjFM-0005Hi-He for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKjFL-0003vh-3z for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:16 -0500 Received: from ozlabs.org ([203.11.71.1]:44299) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKjFI-0003jy-In; Thu, 08 Nov 2018 07:17:14 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 42rMj15YNbz9sNL; Thu, 8 Nov 2018 23:16:52 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1541679413; bh=lnFAh0c0+KxjTYne7Fdk96xTmu8GH4KpqWR5cTEoS/s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nnjKs8/HFi6+7pL8yJll09PZaibXcFRz+HQ7OqYbI4bWpc+iswl2R1T+EcqSz0Mfr QeHk/N0CmNIafbeDEvj0DcjUc1O7FUD6xTBRb1Eny6Mp1wmkrpTw+5oyONfP86cPjV m/YJz/qpEpINxR/g/TwVRBvK4X7nubSyLiIC+DS8= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 8 Nov 2018 23:16:39 +1100 Message-Id: <20181108121646.26173-16-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108121646.26173-1-david@gibson.dropbear.id.au> References: <20181108121646.26173-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 15/22] hw/ppc/mac_newworld: Free openpic_irqs array after use X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, agraf@suse.de, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell In ppc_core99_init(), we allocate an openpic_irqs array, which we then use to collect up the various qemu_irqs which we're going to connect to the interrupt controller. Once we've called sysbus_connect_irq() to connect them all up, the array is no longer required, but we forgot to free it. Since board init is only run once at startup, the memory leak is not a significant one. Spotted by Coverity: CID 1192916. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/ppc/mac_newworld.c | 1 + 1 file changed, 1 insertion(+) -- 2.19.1 diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index a630cb81cd..14273a123e 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -303,6 +303,7 @@ static void ppc_core99_init(MachineState *machine) sysbus_connect_irq(s, k++, openpic_irqs[i][j]); } } + g_free(openpic_irqs); if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { /* 970 gets a U3 bus */ From patchwork Thu Nov 8 12:16:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 150511 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp764499ljp; Thu, 8 Nov 2018 04:33:49 -0800 (PST) X-Google-Smtp-Source: AJdET5fGPjWEsJHinVaqBiT/XDAElkObW7EJmTM5uQnpoHbGBfEwRPa2dWyfgCC7pqzjaWaSTTix X-Received: by 2002:a37:d408:: with SMTP id l8mr3864226qki.315.1541680429248; Thu, 08 Nov 2018 04:33:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541680429; cv=none; d=google.com; s=arc-20160816; b=mDW0LAcd4dUFBNqjo/ZxZATSMQ2yMQLNG0MwRLgnpbqyi9vhb8GAeApUnZGh4cuH6i lQA97ZSb/HhHA7q3kZvlARHJuOW4bmoVQoLHMGLkagGiIyGk59SpTva3wxHQ2N0Q51CR FEm7iQo5Qh4rNNQozDufUJ/GbY0rl3dCqskl8Cy7r9mQAED/eVxkpIyl8+wGLacZEB5S SN70NYS1XBEANPldajf5NJhqCTdNECf6m+KjPI7Ipl8ZeVp0LyRUONrSPVR+FSnHX9m7 LLuViiIg3pZP/d5HZRg4QZtMfbsK/0X+HVSXXtko2ueL+2dF5y7YgPTaOlEtzxPW9Qbr V0GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=vuBeBeQPdf+4KGfDuG4sC/pDG3cyWXTW9nng2Fv3lLw=; b=ATj2fxZ2eS9In/SSJeV1CNPwUhBOoyGcHPlk5XNBgoPYExMaiE1pBG2pPjPmuKZQAE 4asvhEY8aaM15DVntYoLYDe+YDF0lNEvvKel5EdPGmUlP+xDKz6vT2HAkqDFsKkjupON EvU0fCWj667UB11gcZbUACce0Jw/Myy5zox/JCDwyERNQ2JUTuo62Orxyvq70Q9Kk87N CM+Niidbl0rHWBk467FA1WBezmC3Nk5Y4KWw2srFA71T4JDGP057SwDFWoolebkf9U7F 1zQWH3ZRif4ttnY0I5rpDYyBj79XnvOssuc7oMWjZPApvPTXG9/ghpm+ybh4YwXqFyVQ vTBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b="o8/wUXX+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b16si2668791qtp.115.2018.11.08.04.33.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Nov 2018 04:33:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b="o8/wUXX+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56342 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjVM-0003O9-JQ for patch@linaro.org; Thu, 08 Nov 2018 07:33:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjFP-0005K6-8P for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKjFN-00040D-BJ for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:19 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:38285) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKjFM-0003kX-Fb; Thu, 08 Nov 2018 07:17:17 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 42rMj20H0Mz9sNM; Thu, 8 Nov 2018 23:16:53 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1541679414; bh=1dVa4QEej/067z8YOrD22LGI3DB27IwnysQuEc1IdgY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o8/wUXX+3vJr7/WFH758KcNN4yz0rPSvzpWGTYqvIoSsgBbtcIWlRSshmKFIhNRvd m2m/YhRz5zLzVHQLTGN3tx+gJYAZuc/XhlMPYbU4bWwM/lNrseauxXKkfnKxYRPljD dqKkiS8VH1ZPuBZiQXvFbyxKWJ+J7/fn2nznEb7k= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 8 Nov 2018 23:16:42 +1100 Message-Id: <20181108121646.26173-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108121646.26173-1-david@gibson.dropbear.id.au> References: <20181108121646.26173-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 18/22] MAINTAINERS: PPC: Remove myself X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, agraf@suse.de, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alexander Graf I haven't really been maintaining any PowerPC code for quite a while now, so let's reflect reality: David does all the work and embedded PPC is in "Odd Fixes" state rather than supported now. Signed-off-by: Alexander Graf Signed-off-by: David Gibson --- MAINTAINERS | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) -- 2.19.1 diff --git a/MAINTAINERS b/MAINTAINERS index 0499e11593..46772bc0b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -230,7 +230,6 @@ F: tests/tcg/openrisc/ PowerPC M: David Gibson -M: Alexander Graf L: qemu-ppc@nongnu.org S: Maintained F: target/ppc/ @@ -341,7 +340,7 @@ S: Maintained F: target/mips/kvm.c PPC -M: Alexander Graf +M: David Gibson S: Maintained F: target/ppc/kvm.c @@ -779,21 +778,21 @@ F: hw/openrisc/openrisc_sim.c PowerPC Machines ---------------- 405 -M: Alexander Graf +M: David Gibson L: qemu-ppc@nongnu.org S: Odd Fixes F: hw/ppc/ppc405_boards.c Bamboo -M: Alexander Graf +M: David Gibson L: qemu-ppc@nongnu.org S: Odd Fixes F: hw/ppc/ppc440_bamboo.c e500 -M: Alexander Graf +M: David Gibson L: qemu-ppc@nongnu.org -S: Supported +S: Odd Fixes F: hw/ppc/e500.[hc] F: hw/ppc/e500plat.c F: include/hw/ppc/ppc_e500.h @@ -801,16 +800,16 @@ F: include/hw/pci-host/ppce500.h F: pc-bios/u-boot.e500 mpc8544ds -M: Alexander Graf +M: David Gibson L: qemu-ppc@nongnu.org -S: Supported +S: Odd Fixes F: hw/ppc/mpc8544ds.c F: hw/ppc/mpc8544_guts.c New World -M: Alexander Graf +M: David Gibson L: qemu-ppc@nongnu.org -S: Maintained +S: Odd Fixes F: hw/ppc/mac_newworld.c F: hw/pci-host/uninorth.c F: hw/pci-bridge/dec.[hc] @@ -822,9 +821,9 @@ F: include/hw/misc/mos6522.h F: include/hw/ppc/mac_dbdma.h Old World -M: Alexander Graf +M: David Gibson L: qemu-ppc@nongnu.org -S: Maintained +S: Odd Fixes F: hw/ppc/mac_oldworld.c F: hw/pci-host/grackle.c F: hw/misc/macio/ @@ -849,7 +848,6 @@ F: pc-bios/ppc_rom.bin sPAPR M: David Gibson -M: Alexander Graf L: qemu-ppc@nongnu.org S: Supported F: hw/*/spapr* @@ -1124,7 +1122,7 @@ F: tests/acpi-test-data/* F: tests/acpi-test-data/*/* ppc4xx -M: Alexander Graf +M: David Gibson L: qemu-ppc@nongnu.org S: Odd Fixes F: hw/ppc/ppc4*.c @@ -1133,9 +1131,9 @@ F: include/hw/ppc/ppc4xx.h F: include/hw/i2c/ppc4xx_i2c.h ppce500 -M: Alexander Graf +M: David Gibson L: qemu-ppc@nongnu.org -S: Supported +S: Odd Fixes F: hw/ppc/e500* F: hw/pci-host/ppce500.c F: hw/net/fsl_etsec/ From patchwork Thu Nov 8 12:16:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 150510 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp763630ljp; Thu, 8 Nov 2018 04:32:50 -0800 (PST) X-Google-Smtp-Source: AJdET5ewbRcXNLK9iNQiN90lp5bW81e17hkptyiQ3IHatjYd+iOnd3hB7Fd8Jb6zDQrciyNeAZKc X-Received: by 2002:ac8:1bda:: with SMTP id m26mr4106779qtk.239.1541680370317; Thu, 08 Nov 2018 04:32:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541680370; cv=none; d=google.com; s=arc-20160816; b=DDTiF186XwFN7pscQAFU6EIKdSXceZ08/41OJ7pxm0WmoPkz0wNPk2hpxQUSSvS+HS JYnwNJASxgi47AJo1mkd1sj/cle0NpwJkoz1kN/zCpKTH+bz5OIFfq/zjOQdv/Y+GyHO 9jkwTI7KRvZPRV7BdacSgaiWUXaT6JOgxU+ybtkd+nvk3R0I6dKnew8+UwP8q1/v5FZH ZL9zJhESNhCtxyuhSObSHYj/fazdasvlmO5lKcV84/c3kOLl6CckixRv5iKiCzhRiKpm h7ZD/Mwa68f8xE29pDJjj2DJTEMt8Sc34F2hkP+cPRfwWN7bk5M/1ZHQAw2ES+vkj71Q XGPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=NiEaQIwMT66Y+EliiTX0lCRr044rxA5GB3EhfQ5hu1g=; b=MW2ndJHEGXU2d5UYI+Z1frR4QOtjdY/VIQkxW5MD2giJIBdqt3KiQPCzOW5Gpvo/Qi 4ONKA/iB2YHrKy8l0yE+RDXbZtoMWlEx0zwl/UArFA3zHzp/eFzI2fwjOPXrlXmuqvUC okt6y4lKjTHA3iz3HZOUoFznxtKWYgN6eMNWZMumFdvRg/xvFfVfQAZBYair99bRp3wm u3vRO2FZDoU+Zl2APg6eyUQI8zubRU77EhFTrQmt523nFhvp/5JVms5JbJss3rn1yWDx B6w9f2J6RXBgnlTTa+CxZzttAdKSaAf8Y7FOuFvAGEYl49HSX3JEeV8xAAwAEKD/VVWm medg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=RAm2mVK1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s64-v6si11616qkd.110.2018.11.08.04.32.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Nov 2018 04:32:50 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=RAm2mVK1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56338 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjUP-0000g8-Oz for patch@linaro.org; Thu, 08 Nov 2018 07:32:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43537) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKjFP-0005Jz-22 for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKjFN-0003zm-1V for qemu-devel@nongnu.org; Thu, 08 Nov 2018 07:17:18 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:47987) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKjFM-0003kI-Gc; Thu, 08 Nov 2018 07:17:16 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 42rMj13jNQz9sLw; Thu, 8 Nov 2018 23:16:53 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1541679413; bh=r289fCdneoDMxCzgV1MnTiVzTf3yYVE9R2/iKt7jHtY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RAm2mVK1mOjPTsmVsNJCaDMqT+Tmv2d82rv7VMgLRIzQF9iDtChOTq08MiyvyOH8v oW+aR0Hg2Gbfp82CE8x5rc1i7yXQ4kLqlj26Ra6dNVfWMckghkyrCCuTwZymZ6IAHB 7rR1ApfiNEhMOmyYQK4EykDdnZ0FGrCGXzLNUf4g= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 8 Nov 2018 23:16:43 +1100 Message-Id: <20181108121646.26173-20-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108121646.26173-1-david@gibson.dropbear.id.au> References: <20181108121646.26173-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 19/22] hw/ppc/ppc440_uc: Remove dead code in sdram_size() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, agraf@suse.de, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Coverity points out in CID 1390588 that the test for sh == 0 in sdram_size() can never fire, because we calculate sh with sh = 1024 - ((bcr >> 6) & 0x3ff); which must result in a value between 1 and 1024 inclusive. Without the relevant manual for the SoC, we're not completely sure of the correct behaviour here, but we can remove the dead code without changing how QEMU currently behaves. Signed-off-by: Peter Maydell Reviewed-by: Laurent Vivier Signed-off-by: David Gibson --- hw/ppc/ppc440_uc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) -- 2.19.1 diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 09ccda548f..9360f781ce 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -559,11 +559,7 @@ static target_ulong sdram_size(uint32_t bcr) int sh; sh = 1024 - ((bcr >> 6) & 0x3ff); - if (sh == 0) { - size = -1; - } else { - size = 8 * MiB * sh; - } + size = 8 * MiB * sh; return size; }